JPH09223566A - Surge absorption element - Google Patents
Surge absorption elementInfo
- Publication number
- JPH09223566A JPH09223566A JP6505896A JP6505896A JPH09223566A JP H09223566 A JPH09223566 A JP H09223566A JP 6505896 A JP6505896 A JP 6505896A JP 6505896 A JP6505896 A JP 6505896A JP H09223566 A JPH09223566 A JP H09223566A
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- JP
- Japan
- Prior art keywords
- electrodes
- substrate
- pair
- electrode
- microgap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【発明の詳細な説明】 [産業上の利用分野]本発明は、マイクロギャップ或い
はギャップ式サージ吸収素子に関し、特にプリント基板
への自動実装の有利な、サーフェスマウント型サージ吸
収素子に関する。The present invention relates to a microgap or gap type surge absorber, and more particularly to a surface mount type surge absorber which is advantageous for automatic mounting on a printed circuit board.
[従来の技術]電話機、ファクシミリ等通信機器をサー
ジから保護するためのサージ吸収素子は、従来第1図に
示すように、マイクロギャップ2を形成する一対の電極
1a、1bが円柱状の碍子表面に設けられ、碍子上の一
対の電極1a、1b夫れ夫れにリード線付きキャップ電
極3a、3bを取り付け、ガラス管5で、気密に封止さ
れ、内部は減圧された構造である。従来のマイクロギャ
ップ式サージ吸収素子は、第1図に於いて明らかなよう
に、25mm前後のリード線4を有し、プリント基板へ
の実装に当たっては、リード線の適切な長さへの切断、
曲げ加工が必要となり、その後にプリント基板の穴にリ
ード線を挿入し半田付けするものであった。しかし、周
知のように斯かるプリント基板への実装着方法は、工数
のかかる方法であり、多くの電子部品が面実装型のいわ
ゆるサーフェスマウント型電子部品へと移り変わって来
ている。又これら従来のサージ吸収素子は、円柱状の碍
子表面の円周に沿った加工工程があるため、生産性を上
げるための障害となり、原価を引き下げるための足かせ
となっていた。更にサージ吸収時の放電によって発生す
る熱は、主に細いリード線を経由して放熱されるため、
熱抵抗が大きく結果として、素子内の温度上昇を招き、
素子の劣化特にマイクロギャップ或いはギャップ部の電
極の劣化をもたらした。本発明は、実装が容易で更に製
造も容易で且つ長寿命なマイクロギャップ或いはギャッ
プ型サージ吸収素子を提供することを目的としている。[Prior Art] As shown in FIG. 1, a surge absorbing element for protecting a communication device such as a telephone and a facsimile device has a cylindrical insulator surface in which a pair of electrodes 1a and 1b forming a microgap 2 are cylindrical. , A pair of cap electrodes 3a and 3b with lead wires are attached to each of the pair of electrodes 1a and 1b on the insulator, which is hermetically sealed with a glass tube 5 and the inside is depressurized. As is apparent from FIG. 1, the conventional microgap type surge absorbing element has a lead wire 4 having a length of about 25 mm, and when mounted on a printed circuit board, the lead wire is cut to an appropriate length,
Bending is required, and then lead wires are inserted into the holes of the printed circuit board and soldered. However, as is well known, such a mounting and mounting method on a printed circuit board is a labor-intensive method, and many electronic components have been changed to surface mounting type so-called surface mounting type electronic components. Further, these conventional surge absorbing elements have a processing step along the circumference of the surface of a cylindrical insulator, which is an obstacle to improving productivity and is a hindrance to cost reduction. Furthermore, the heat generated by the discharge during surge absorption is radiated mainly through the thin lead wires,
As a result, the thermal resistance is large, which causes a temperature rise in the element.
Deterioration of the device, particularly deterioration of the electrodes in the micro gap or the gap portion was brought about. It is an object of the present invention to provide a microgap or gap type surge absorber that is easy to mount, easy to manufacture, and has a long life.
[問題点を解決するための手段]本発明の要旨とするも
のは、基板の同一平面上に、相互に電気的に絶縁され、
マイクロギャップ或いはギャップを形成するように配置
され、且つマイクロギャップ或いはギャップ近傍に於い
て電気抵抗の高い電極部と、外部電極或いは端子に通ず
る比較的電気抵抗の低い電極部とより成る一対の電極
と、前記マイクロギャップ或いはギャップ及びギャップ
周辺の前記一対の電極を含み、前記基板の前記平面を覆
う気密キャップ又は蓋と、前記基板の両端面近傍に設け
られた一対の電極とを有することを特徴とするマイクロ
ギャップ或いはギャップ式サージ吸収素子である。本発
明では、従来円柱状碍子表面に設けられて、マイクロギ
ャップを形成するように配置されていた一対の電極を、
平面基板上への配置とし、電極とマイクロギャップを覆
うようにして設けた、気密キャップにより放電空間を形
成させることにより、マイクロギャップ式サージ吸収素
子主要部を構成させることにより、同一基板上で整然と
配列された素子材料を、多数個或いは一括加工処理が出
来、従来に比較して極めて高い生産性が実現出来る。更
に平面上に形成された電極は、マイクロギャップ或いは
ギャップ近傍に於いて電気抵抗の高い電極部と、外部電
極或いは端子に通ずる比較的電気抵抗の低い電極部とよ
り成る一対の電極により構成されているため、放電開始
後はマイクロギャップ部の電極に放電電流の集中が防止
でき、電極の劣化が防止出来る。更にプリント基板への
実装用の外部電極を、上記平面基板端面に配することに
よって、同一平面上の一対の外部電極によるプリント基
板への面実装を、可能ならしめたものである。次に本発
明のサージ吸収素子を具体例によって説明するが、本発
明は、その説明に限定されるものではない。[Means for Solving the Problems] The gist of the present invention is to electrically insulate each other on the same plane of a substrate,
A pair of electrodes, which are arranged so as to form a microgap or a gap and have a high electric resistance in the vicinity of the microgap or the gap, and an electrode part having a relatively low electric resistance that communicates with an external electrode or a terminal. An airtight cap or lid that includes the microgap or the gap and the pair of electrodes around the gap and covers the flat surface of the substrate, and a pair of electrodes provided near both end surfaces of the substrate. It is a microgap or a gap type surge absorber. In the present invention, a pair of electrodes, which are conventionally provided on the surface of a cylindrical insulator, are arranged so as to form a microgap,
It is arranged on a flat substrate and the discharge gap is formed by an airtight cap that is provided so as to cover the electrodes and the microgap. It is possible to process a large number of arrayed element materials or to process them all at once, and it is possible to realize extremely high productivity as compared with the prior art. Further, the electrode formed on the plane is composed of a pair of electrodes including an electrode portion having a high electric resistance in the microgap or in the vicinity of the gap and an electrode portion having a relatively low electric resistance communicating with an external electrode or a terminal. Therefore, after the discharge is started, the discharge current can be prevented from concentrating on the electrodes in the microgap portion, and the deterioration of the electrodes can be prevented. Further, by arranging external electrodes for mounting on the printed board on the end surface of the planar board, surface mounting on the printed board by a pair of external electrodes on the same plane is made possible. Next, the surge absorbing element of the present invention will be described by way of specific examples, but the present invention is not limited to the description.
[実施例1]第2図に、本発明にかかるサージ吸収素子
の一例を断面略図A、平面図Bによって示す。ムライ
ト、アルミナ等絶縁基板21主表面にスクリーン印刷等
によって一対の電極22a、22a’、22b、22
b’を設け、一対の電極22a’、22b’間 にマイ
クロギャップ23を設けたものである。これら一対の電
極はマイクロギャップ或いはギャップ近傍に於いて電気
抵抗の高い電極部22a’と22b’と、外部電極或い
は端子に通ずる比較的電気抵抗の低い電極部22A、2
2bとより成っている。一対の電極を覆うように気密キ
ャッ プ25が設けられ電極を有する基板との間に密閉
空間を形成している。気密キャップ25は、コバール等
金属或いはガラス、セラミックが好適である。又気密キ
ャップ25の基板21面への封着には、ガラスフリット
が好適であるが、金属キャップなどの場合、半田を利用
することも可能である。この場合、半田による電極22
aと22bの短絡を防止するため、電極22aと22b
表面をガラス膜等絶縁膜で覆う事が必要である。半田付
け部の基板表面には、予め半田付け可能な銀パラジウ
ム、モリブデン合金、タングステン合金等導電体膜を、
スクリーン印刷・焼成法或いは、蒸着法、スパッタリン
グ法、CVD(ケミカルベーパーデポジション)等によ
って形成しておくことが望ましい。更に封着用半田とし
ては、サージ吸収素子の面実装のときの半田熔融温度に
於いて、熔融しない高温半田を用いることが望ましい。
図において26は、気密キャップ25を基板21面上に
封着するためのガラスフリット、半田等の封着材料であ
る。更に気密キャップ封着時は、真空排気し、その状態
で或いはアルゴンガス等で一部置換したのち所定の圧力
下において加熱し、ガラスフリット或いは半田を熔融し
封着する。以上の説明によって明らかなように、面実装
可能なサージ吸収素子が可能となる。更にかかる素子が
スクリーン印刷技術等量産性の高い膜形成技術が活用で
きる結果、実装面で有利な面実装型サージ吸収素子が、
高い量産性のもとで得られる事も明らかである。さらに
サージ吸収素子の特性面での以下の効果が確認された、
すなわち第1図に示した従来のサージ吸収素子と比較し
た場合、これら素子は熱抵抗の大きい直径0.5mm前
後のリード線により放熱されるのに対して、本実施例の
サージ吸収素子では、リード線によらず、幅広の電極端
子27a、27 bによっている、電極の断面積で比較
しても4倍以上となり、熱放散が改善され、更にマイク
ロギャップ部で開始する放電は、電極上を進展し、22
aと22bに達する、この時マイクロギャップ23近傍
の電極22a’、22b’は高抵抗電極であるため、放
電電流は流れにくくなり、マイクロギャップ部に放電が
集中せず、マイクロギャップに対向する電極の劣化が防
止出来る。これによってサージ吸収素子としての長寿命
化は無論、サージ耐量も従来素子により大幅に改善でき
た。なお図において、高い電気抵抗を有する電極部と2
2a’と22b’は、タングステン・モリブデン等の高
抵抗金属膜をスパッタリング法、電子ビーム蒸着法、C
VD法(ケミカルベーパーデポジション法)等で被着形
成低することが望ましく、低い電気抵抗の電極部22a
と22bは、銅、コバール等半田付けの可能な金属或い
は合金を、前記同様スパッタリング法、電子ビーム蒸着
法、CVD法(ケミカルベーパーデポジション法)等に
よって形成することが望ましい。この場合パターン化
は、フォトエッチングによって行う。更に斯かる薄膜技
術によらず、厚膜技術によっても可能であり、この場合
は、高い電気抵抗の電極部22a’と22b’は、抵抗
膜を印刷・焼成による抵抗膜により形成し、低い電気抵
抗の電極部22aと22bは、印刷・焼成による導電膜
により形成することも可能であり、かかる場合は印刷に
よりハターン化が可能であり、エッチング処理は不要と
なる。[Embodiment 1] FIG. 2 shows an example of a surge absorber according to the present invention by a schematic sectional view A and a plan view B. A pair of electrodes 22a, 22a ', 22b, 22 is formed on the main surface of the insulating substrate 21 such as mullite or alumina by screen printing or the like.
b'is provided, and the micro gap 23 is provided between the pair of electrodes 22a ', 22b'. These pair of electrodes are composed of electrode portions 22a 'and 22b' having a high electric resistance in the microgap or in the vicinity of the gap, and electrode portions 22A having a relatively low electric resistance communicating with external electrodes or terminals.
It consists of 2b. An airtight cap 25 is provided so as to cover the pair of electrodes to form a hermetically sealed space with the substrate having the electrodes. The airtight cap 25 is preferably made of metal such as Kovar, glass, or ceramic. Further, glass frit is suitable for sealing the airtight cap 25 to the surface of the substrate 21, but in the case of a metal cap or the like, solder can also be used. In this case, the electrode 22 made of solder
electrodes 22a and 22b to prevent short circuit between a and 22b
It is necessary to cover the surface with an insulating film such as a glass film. A conductive film such as silver-palladium, molybdenum alloy, or tungsten alloy, which can be soldered in advance, is provided on the substrate surface of the soldering part.
It is desirable to form them by screen printing / firing method, vapor deposition method, sputtering method, CVD (chemical vapor deposition) or the like. Further, as the solder for sealing, it is desirable to use high-temperature solder that does not melt at the solder melting temperature during surface mounting of the surge absorbing element.
In the figure, 26 is a sealing material such as glass frit or solder for sealing the airtight cap 25 on the surface of the substrate 21. Further, at the time of sealing the airtight cap, the glass frit or solder is melted and sealed by evacuating and evacuating and partially heating with argon gas or the like and then heating under a predetermined pressure. As is clear from the above description, a surface mountable surge absorbing element is possible. Furthermore, as a result of the fact that such elements can utilize highly mass-producible film forming technology such as screen printing technology, surface-mount type surge absorption elements, which are advantageous in terms of mounting,
It is also clear that it can be obtained with high mass productivity. Furthermore, the following effects in the characteristics of the surge absorber were confirmed,
That is, when compared with the conventional surge absorbing element shown in FIG. 1, these elements radiate heat through a lead wire having a large thermal resistance and having a diameter of about 0.5 mm, whereas in the surge absorbing element of this embodiment, The cross-sectional area of the electrode is four times or more compared with the cross-sectional area of the electrode, which is formed by the wide electrode terminals 27a and 27b regardless of the lead wire, the heat dissipation is improved, and the discharge started at the microgap portion is generated on the electrode. Progress, 22
Since the electrodes 22a 'and 22b' near the micro gap 23 which reach a and 22b are high resistance electrodes, the discharge current is less likely to flow, the discharge is not concentrated in the micro gap portion, and the electrodes facing the micro gap are provided. Can be prevented from deterioration. As a result, of course, the life of the surge absorbing element was extended, and the surge withstand capability could be greatly improved by the conventional element. In the figure, the electrode portion having a high electric resistance and the electrode portion 2
2a 'and 22b' are formed by sputtering a high resistance metal film of tungsten, molybdenum, etc., electron beam evaporation method, C
It is desirable to reduce deposition by the VD method (chemical vapor deposition method) or the like, and the electrode portion 22a having a low electric resistance.
It is desirable that, and 22b be formed of a solderable metal or alloy such as copper or kovar by the same sputtering method, electron beam evaporation method, CVD method (chemical vapor deposition method) or the like as described above. In this case, patterning is performed by photoetching. Further, it is possible to use not only such a thin film technology but also a thick film technology. In this case, the electrode portions 22a ′ and 22b ′ having a high electric resistance are formed by a resistance film formed by printing and firing, and a low electric resistance is obtained. The electrode portions 22a and 22b of the resistor can be formed of a conductive film by printing / baking. In such a case, the pattern can be formed into a pattern and the etching process is unnecessary.
[実施例2]第3図は、本発明にかかる他の実施例を示
す断面略図であり。本実施例では、基板31にアルミニ
ウム等導電性基板を用いており、導電性のある材料であ
るため、アルミニウム基板の場合は、基板表面を、Al
2O3等アルミニウム酸化膜等絶縁膜38でカバーして
ある。かかる材料を用いた場合、基板自体が高い熱伝導
率を持っているため、サージ吸収素子として動作時、大
電流のサージによって発生する熱の放散が格段に改善さ
れるため、実施例1によって比較してサージ吸収素子と
しての特性の劣化しにくいサージ吸収素子が提供でき
る。なお図において32a、32bは高抵抗電極部であ
り、33はマイクロギャップであり、34aと34bは
低抵抗電極部である、さらに35は気密キャップ、36
は気密キャップ35を気密に接着する接着剤、37a、
37bはコバール等よりなる電極端子である。さらに第
1図に示した従来のサージ吸収素子と比較した場合、こ
れら素子は熱抵抗の大きい直径0.5mm前後のリード
線により放熱されるのに対して、本実施例のサージ吸収
素子では、熱伝導の優れた基板31全面からの熱放散と
なり、放熱の改善は顕著となり、前記実施例2にも述べ
たように、ギャップに対向する高い電気抵抗の電極部へ
の放電電流が抑制され事とも相俟って、放電時の熱によ
る劣化が防止でき、サージ吸収素子としての長寿命化は
無論、サージ耐量も大幅に改善できる。[Embodiment 2] FIG. 3 is a schematic sectional view showing another embodiment of the present invention. In this embodiment, a conductive substrate such as aluminum is used as the substrate 31 and is a conductive material. Therefore, in the case of an aluminum substrate, the surface of the substrate is
It is covered with an insulating film 38 such as an aluminum oxide film such as 2 O 3 . When such a material is used, since the substrate itself has a high thermal conductivity, heat dissipation generated by a surge of a large current is significantly improved during operation as a surge absorbing element. As a result, it is possible to provide a surge absorbing element in which the characteristics of the surge absorbing element are less likely to deteriorate. In the figure, 32a and 32b are high resistance electrode portions, 33 is a microgap, 34a and 34b are low resistance electrode portions, 35 is an airtight cap, and 36
Is an adhesive for airtightly adhering the airtight cap 35, 37a,
37b is an electrode terminal made of Kovar or the like. Further, when compared with the conventional surge absorbing element shown in FIG. 1, these elements radiate heat by a lead wire having a large thermal resistance and having a diameter of about 0.5 mm, whereas in the surge absorbing element of the present embodiment, Since the heat is dissipated from the entire surface of the substrate 31 having excellent heat conduction, the heat dissipation is remarkably improved, and the discharge current to the electrode portion having a high electric resistance facing the gap is suppressed as described in the second embodiment. Together with this, deterioration due to heat during discharge can be prevented, the life of the surge absorbing element can be extended, and surge withstand can be greatly improved.
[実施例3]第4図は、本発明にかかる他の実施例を示
す断面略図あり、図において41は絶縁基板、42a、
42a’、42b、42b’は、絶縁基板上に形成され
た一対の電極、43は一対の電極 42a、42b間に
設けられたギャップである。なお図において、42a’
と42b’は低い電気抵抗の電極部、42a’と42
b’は高い電気抵抗の電極部である。更に44は電極と
キャップ材質によって適応されるガラス膜等絶縁性膜、
45は気密封止用の蓋である。即ち電極は導電性であ
り、半田を封着材として使用したり、金属キャップを使
用すると、一対の電極が、半田とかキャップによって短
絡し、サージ吸収素子として動作しないため、電極を覆
うようにガラス等絶縁性膜を設ける必要がある。実施例
1及び実施例2に比較すると、本実施例は平面の蓋によ
って封止している点が異なっている。平面の蓋によるば
あい、キャップの場合のようなキャップ成型作業が不要
となり高価な金型を必要としないメリットがあるし、平
板なので材料の選定に自由度が大きい。しかし、一対の
電極42a、42bと蓋の間隙を適切にし、形成される
気密空間を確保するため、厚みのある封着材48が必要
である。封着材の厚付けか封着材適用前に予めガラスフ
リット等封着材より融点の高い材料によるかさ上げをし
ておくことが有効である。[Embodiment 3] FIG. 4 is a schematic cross-sectional view showing another embodiment of the present invention, in which 41 is an insulating substrate, 42a,
42a ', 42b, 42b' are a pair of electrodes formed on the insulating substrate, and 43 is a gap provided between the pair of electrodes 42a, 42b. In the figure, 42a '
42a 'and 42b' are electrodes having low electric resistance,
b'is an electrode part having a high electric resistance. Further, 44 is an insulating film such as a glass film adapted to the electrode and the cap material,
Reference numeral 45 is a lid for hermetically sealing. That is, the electrodes are conductive, and when solder is used as a sealing material or a metal cap is used, the pair of electrodes are short-circuited by the solder or the cap and do not operate as a surge absorbing element. It is necessary to provide a uniform insulating film. Compared to the first and second embodiments, the present embodiment is different in that it is sealed by a flat lid. When a flat lid is used, there is an advantage that a cap molding operation unlike the case of a cap is not required and an expensive mold is not required, and since it is a flat plate, there is a large degree of freedom in selecting a material. However, a thick sealing material 48 is necessary in order to make the gap between the pair of electrodes 42a and 42b and the lid appropriate and to secure the airtight space to be formed. It is effective to thicken the sealing material or to raise it with a material having a higher melting point than the sealing material such as glass frit in advance before applying the sealing material.
[実施例4]第5図に本発明にかかる他の実施例を示し
た。実施例1から実施例3における電極端子部の形成に
かかり、当該サージ吸収素子はより低価格化を達成した
実施例である。第5図Aは平面図、第5図Bは断面略図
を示した。多面取りのスルーホールを有するセラミック
基板に対して、印刷、焼成技術により、スルーホールを
介して裏面に一対の電極を取り出した構造であり、この
場合特別な電極端子の取り付けは不必要となり、生産工
数の低減によるコストダウン効果は大きい。図において
51はセラミック基板、52a、52a’、52b、5
2b’は一対の電極(図ではレーザーカットによるギャ
ップ形成前の状態を示す)であり、52a’と52b’
は高い電気抵抗の電極部、52aと52bは低い電気抵
抗の電極部兼外部接続電極であり、59a、59bは基
板51の表裏面の電極を接続する導電膜である。[Embodiment 4] FIG. 5 shows another embodiment of the present invention. This is an example in which the price of the surge absorbing element is further reduced due to the formation of the electrode terminal portion in the examples 1 to 3. FIG. 5A is a plan view and FIG. 5B is a schematic sectional view. This is a structure in which a pair of electrodes are taken out on the back surface through the through holes by a printing and firing technique for a ceramic substrate having multiple through holes. In this case, it is not necessary to attach special electrode terminals, The cost reduction effect is large due to the reduction of man-hours. In the figure, 51 is a ceramic substrate, 52a, 52a ', 52b, 5
2b 'is a pair of electrodes (in the figure, the state before the gap formation by laser cutting is shown), and 52a' and 52b '
Is a high electric resistance electrode portion, 52a and 52b are low electric resistance electrode portions and external connection electrodes, and 59a and 59b are conductive films for connecting electrodes on the front and back surfaces of the substrate 51.
[実施例5]第6A図の断面略図と第6B図の平面図に
よって、本発明にかかる他の実施例を示す。図におい
て、61は基板、62a、62b、62a’、62
b’、は電極をあり、これら電極は抵抗率の異なる部分
で構成されている。即ち電気抵抗の高い電極部62
a’、62b’と、電気抵抗の低い62a、62b電極
部とで構成されている。これによって、ギャップ63部
で開始された放電が、電極上を拡大し、電極62a、6
2b間まで容易に進展し易くすることが可能であり、放
電が集中することを防ぎ、熱的に傷み易いマイクロギゃ
ップ部電極の寿命を向上させることができる。なお図に
おいて65はキャップ、66は封着材、67a、67b
は一対の電極端子である。電極62a’、62b’とし
ては、熱安定性の高いタングステン、モリブテン、タン
タル等高融点金属を、電子ビーム蒸着方法、スパッタリ
ング方法、CVD(ケミカルベーパーデポジション)方
法によって形成する。数十オングストロームから100
0Λの厚さが効果的である。更に不純物のドープ量によ
って、抵抗率が変化し、比較的融点も高いSi等半導体
も有効である。電極62a、62bに関しては、金、
銅、ニッケル等が有効であるが、前記タングステン、タ
ンタル、モリブテン等高融点金属膜厚さを厚くして、抵
抗を低くして使用することも有効であり、この場合材料
として1種類となり、設備投資と工程管理の面から有利
となる。[Embodiment 5] Another embodiment of the present invention is shown by the schematic sectional view of FIG. 6A and the plan view of FIG. 6B. In the figure, 61 is a substrate, 62a, 62b, 62a ', 62.
Reference numeral b'denotes electrodes, and these electrodes are composed of portions having different resistivities. That is, the electrode portion 62 having high electric resistance
a ', 62b', and 62a, 62b having a low electric resistance. As a result, the discharge started at the gap 63 expands on the electrodes, and the electrodes 62a, 6
It is possible to make it easy to progress to the area between 2b, prevent the discharge from being concentrated, and improve the life of the micro gap portion electrode which is easily damaged by heat. In the figure, 65 is a cap, 66 is a sealing material, and 67a and 67b.
Is a pair of electrode terminals. As the electrodes 62a 'and 62b', refractory metals such as tungsten, molybdenum, and tantalum, which have high thermal stability, are formed by an electron beam evaporation method, a sputtering method, and a CVD (chemical vapor deposition) method. Dozens of Angstroms to 100
A thickness of 0Λ is effective. Further, a semiconductor such as Si, which has a relatively high melting point and whose resistivity changes depending on the doping amount of impurities, is also effective. For the electrodes 62a and 62b, gold,
Copper, nickel, etc. are effective, but it is also effective to increase the film thickness of the refractory metal such as tungsten, tantalum, molybdenum to lower the resistance, and in this case, it becomes one kind of material, and equipment It is advantageous in terms of investment and process control.
[実施例6]実施例5に於いて、高い電気抵抗の電極部
62a’と62b’を、印刷・焼成による厚膜抵抗を用
い、低い電気抵抗の電極部62aと62bを、印刷・焼
成による厚膜導電膜を用いた実施例によっても同様の効
果が得られた。かかる場合は、電極62aと62b及び
67aと67bを同一厚膜導電膜で形成することも可能
であり、これによって工程の簡略化が計れる効果があ
る。[Sixth Embodiment] In the fifth embodiment, the electrode portions 62a 'and 62b' having high electric resistance are formed by thick film resistance by printing and firing, and the electrode portions 62a and 62b having low electric resistance are formed by printing and firing. Similar effects were obtained also in the examples using the thick conductive film. In such a case, the electrodes 62a and 62b and 67a and 67b can be formed of the same thick-film conductive film, which has the effect of simplifying the process.
[実施例7]本発明を実現するための電極付基板の形成
方法を具体的に示す。第7A図、第7B図及び第7C図
は、実施例を説明する図であり、図において第7A図と
第7B図は平面図、第7C図は第7A図のa−bの断面
略図である。基板71は、セラミック等絶縁基板又はア
ルマイト等絶縁膜を被覆したアルミニウム等導電性基板
である。第7A図に於いては、基板表面に印刷・焼成技
術により厚膜抵抗72が形成され、続いて第7Bに示す
ように、同様の印刷・焼成技術により一対の厚膜導電体
72aと72bが形成される。厚膜導電体は、スルーホ
ール79を通して裏面に通じ、裏面でプリント基板への
実装時の半田付け用の電極となる。第7C図は、レーザ
ーカッターによって、マイクロギャップ73の形成を示
し、これによってマイクロギャップに於いて対向する、
高い電気抵抗を有する一対の電極部72a’と72b’
が形成される。かかる方法によれば、同一基板上での電
極等パターン形成は、基板単位で一度に行われ、基板の
大きさにもよるが、1基板当たり数百個から数千個が処
理可能となり、本発明によれば極めて高い生産性が実現
出来る。[Embodiment 7] A method for forming a substrate with electrodes for realizing the present invention will be specifically described. 7A, 7B, and 7C are views for explaining the embodiment, in which FIGS. 7A and 7B are plan views, and FIG. 7C is a schematic cross-sectional view taken along line ab of FIG. 7A. is there. The substrate 71 is an insulating substrate such as ceramic or a conductive substrate such as aluminum coated with an insulating film such as alumite. In FIG. 7A, a thick film resistor 72 is formed on the surface of the substrate by a printing / firing technique, and subsequently, as shown in FIG. 7B, a pair of thick film conductors 72a and 72b are formed by the same printing / firing technique. It is formed. The thick film conductor communicates with the back surface through the through hole 79 and serves as an electrode for soldering at the time of mounting on the printed circuit board on the back surface. FIG. 7C shows the formation of the microgap 73 by means of a laser cutter, whereby the microgap is opposed at the microgap,
A pair of electrode portions 72a 'and 72b' having high electric resistance
Is formed. According to such a method, pattern formation of electrodes and the like on the same substrate is performed at a time on a substrate-by-substrate basis, and depending on the size of the substrate, several hundreds to several thousands can be processed per substrate. According to the invention, extremely high productivity can be realized.
[実施例8]本発明を実現するための電極付基板の形成
方法を他の具体的によって示す。第8A図、第8B図及
び第8C図は、実施例を説明する図であり、図において
第8A図と第8B図は平面図、第8C図は第7A図のa
−bの断面略図である。基板81は、セラミック等絶縁
基板又はアルマイト等絶縁膜を被覆したアルミニウム等
導電性基板である。第8A図は、高い電気抵抗の電極部
の形成に係り、図において81は基板、82はスパッタ
リング法、電子ビーム蒸着法、CVD法等によって形成
された薄膜である。実施例で薄膜は、タングステン、モ
リブテン等高融点・高抵抗の金属の第1層と、銅、ニッ
ケル、コバール等半田付け可能な金属膜の第2層から成
っている。第8B図では、上記金属膜がエッチングによ
りパターン形成され、本発明に係る一対の電極となる。
図において82aとと82bは、低い電気抵抗の電極
部、82a’と82b’は、高い電気抵抗の電極部出あ
る。83はマイクロギャップである。第8C図は、印刷
・焼成によって、スルーホル89を介して裏面に接続形
成された電極端子部である。実施例7同様、当該実施例
によっても、薄膜形成が基板単位で実施出来るため、極
めて高い生産性を実現することが可能である。なお本実
施例で薄膜形成として、連続的に2層を形成したが、高
融点・高抵抗の薄膜を形成し且つパターンエッチングし
て後、第2の低い電気抵抗の電極部のための金属膜を形
成することも無論可能であり、同様の効果が得られる。[Embodiment 8] A method of forming a substrate with electrodes for realizing the present invention will be described in detail. 8A, 8B and 8C are views for explaining the embodiment, wherein FIGS. 8A and 8B are plan views and FIG. 8C is a in FIG. 7A.
-B is a schematic cross-sectional view of FIG. The substrate 81 is an insulating substrate such as ceramic or a conductive substrate such as aluminum coated with an insulating film such as alumite. FIG. 8A relates to formation of an electrode portion having a high electric resistance. In the figure, 81 is a substrate, and 82 is a thin film formed by a sputtering method, an electron beam evaporation method, a CVD method or the like. In the embodiment, the thin film is composed of a first layer of a metal having a high melting point and a high resistance such as tungsten and molybdenum, and a second layer of a solderable metal film such as copper, nickel and kovar. In FIG. 8B, the metal film is patterned by etching to form a pair of electrodes according to the present invention.
In the figure, reference numerals 82a and 82b denote electrode portions having a low electric resistance, and reference numerals 82a 'and 82b' denote electrode portions having a high electric resistance. 83 is a microgap. FIG. 8C shows an electrode terminal portion connected and formed on the back surface through the through hole 89 by printing and firing. Similar to the seventh embodiment, also in this embodiment, the thin film formation can be performed in substrate units, so that extremely high productivity can be realized. In this embodiment, two layers were continuously formed as the thin film formation. However, after forming a high melting point and high resistance thin film and pattern etching, a metal film for the second low electric resistance electrode portion is formed. Of course, it is possible to form, and the same effect can be obtained.
[実施例9]本発明に必要な、高い電気抵抗の電極部形
成に関する、他の実施例を示す。単一の層として形成し
た電極を、電極の平面形状(或いは電極面積)を少なく
することによって、高い電気抵抗の電極部を形成するこ
とが可能である。第9A図と第9B図は、本発明にかか
る他の実施例を示す平面図であり、第9C図は、第9A
図a−bの断面略図である。図において、91は基板、
92aと92bは、一対の電極であり、W、Mo等の材
料よりなる数10ÅΛから10,000Å薄膜或いは印
刷・焼成した抵抗体よりなる。本発明では、ギャップ9
3近傍のこれら電極の一部を除去し、電極の平面形状
(或いは断面積)を少なくし、抵抗を高めた構成であ
る。図において、100及び100’は、電極の除去部
であり、これにより、電極72a、72bからギャップ
部に至る72a’、72b’部の抵抗は高くなり、これ
によって放電は、容易に92aと92bに進展し、ギャ
ップ部の電極の寿命が延びることとなった。なおギャッ
プ93形成と除去部100及び100’の形成を、フォ
トエッチング方法によって実施した場合、同一工程で一
括して実施できる。また前記実施例のごとくレーザーカ
ッターで、連続工程として実施することも可能である、
しかしこの場合は、除去部外周をレーザーで囲うように
線状に除去すれば、囲われた部分は周囲電極より分離さ
れるので、除去したと同様な効果が得られ、レーザー加
工時間の短縮が可能となる。無論エッチングによって除
去部に相当する部分の周囲のみをエッチング除去するこ
とも可能であり、全く同様の効果が得られる。[Embodiment 9] Another embodiment relating to the formation of an electrode portion having a high electric resistance necessary for the present invention will be described. By reducing the planar shape (or electrode area) of the electrode formed as a single layer, it is possible to form an electrode portion having high electric resistance. 9A and 9B are plan views showing another embodiment according to the present invention, and FIG. 9C is a plan view showing the other embodiment.
3 is a schematic cross-sectional view of FIG. In the figure, 91 is a substrate,
Numerals 92a and 92b are a pair of electrodes, and are composed of several tens of ÅΛ to 10,000 Å thin films made of materials such as W and Mo or printed and fired resistors. In the present invention, the gap 9
A part of these electrodes near 3 is removed, the planar shape (or cross-sectional area) of the electrodes is reduced, and the resistance is increased. In the figure, 100 and 100 'are electrode removal parts, which increases the resistance of the electrodes 72a, 72b to the gap part at 72a', 72b ', which facilitates discharge easily at 92a and 92b. And the life of the electrode in the gap portion is extended. When the formation of the gap 93 and the formation of the removed portions 100 and 100 ′ are performed by the photoetching method, they can be collectively performed in the same process. It is also possible to carry out as a continuous process with a laser cutter as in the above-mentioned embodiment,
However, in this case, if the outer periphery of the removed portion is linearly removed so as to be surrounded by a laser, the enclosed portion is separated from the surrounding electrode, so that the same effect as that of the removal can be obtained and the laser processing time can be shortened. It will be possible. Of course, it is possible to etch and remove only the periphery of the portion corresponding to the removed portion, and the same effect can be obtained.
[実施例10]第10図は、本発明に係る一対の高い電
気抵抗の電極部の他の実施例を示す断面略図であり、図
に於いて101は基板、102a、102a’、102
b、102b’は薄膜電極であり、103はマイクロギ
ャップである。図において、高い電気抵抗の電極部10
2a’と102b’と低い電気抵抗の電極部102aと
102bは、同一材質からなる薄膜であり、高い電気抵
抗の電極部は、当該部分の薄膜をエッチングにより薄く
して、高抵抗化したものである。かかる構成によっても
本発明の趣旨は達成される。[Embodiment 10] FIG. 10 is a schematic cross-sectional view showing another embodiment of a pair of high electric resistance electrode portions according to the present invention, in which 101 is a substrate, 102a, 102a ', 102.
Reference numerals b and 102b 'are thin film electrodes, and 103 is a microgap. In the figure, the electrode portion 10 having high electrical resistance
The electrode portions 102a and 102b having low electrical resistances 2a 'and 102b' are thin films made of the same material, and the electrode portions having high electrical resistance are those obtained by thinning the thin film of the portions by etching to increase the resistance. is there. The gist of the present invention is also achieved by such a configuration.
[発明の効果]本発明のサージ吸収素子は、2本のリー
ド線を有する従来のサージ吸収素子に比較し、リード線
の無い面実装型のサージ吸収素子として、プリント基板
実装時の大幅な生産性向上が可能となったばかりでな
く、大電流のサージが印加時に発生する熱放散の改善更
には、マイクロギャップ部への放電電流集中が防止出
来、これによって、サージ耐量も大幅に改善、更には素
子寿命の改善されたサージ吸収素子を提供することが出
来る。更に変形しやすいリード線の整列、転がり安い円
柱状電極部とキャップ及びガラ管等と、これらの整列し
たり取り扱うには自動化が困難であり、コストダウンの
大きな障害であった。しかし本発明によれば多面取り基
板をもちいて、同時に大量の素子に厚膜或いは薄膜形成
技術によって電極形成が可能となるり、多面取り基板上
での相互の素子の位置関係は正確であるため、キャップ
とか蓋の装着の時部品が簡単な治具によって整列しやす
く、自動化も容易となり、生産性の向上それにもとずく
コストダウンが可能となった。[Advantages of the Invention] The surge absorbing element of the present invention is a surface-mount type surge absorbing element having no lead wire, and is a large-scale production when mounted on a printed circuit board, as compared with a conventional surge absorbing element having two lead wires. Not only is it possible to improve the performance, but also to improve the heat dissipation that occurs when a large current surge is applied, and to prevent the discharge current from concentrating in the microgap part. It is possible to provide a surge absorbing element having an improved element life. Further, it is difficult to automate the arrangement of the lead wires that are more easily deformed, the cylindrical electrode portion that is cheap to roll, the cap, the glass tube, etc., and to handle them, which is a major obstacle to cost reduction. However, according to the present invention, it is possible to form electrodes on a large number of devices at the same time by a thick film or thin film forming technique using a multi-chamber substrate, and the mutual positional relationship of the devices on the multi-chamber substrate is accurate. , When the cap or lid is attached, the parts can be easily aligned by a simple jig, automation is facilitated, productivity is improved, and cost is reduced accordingly.
【第1図】従来技術によるサージ吸収素子の断面略図、
図中1a、1bは一対の電極、2はマイクロギャップ、
5はガラス管である。FIG. 1 is a schematic sectional view of a surge absorber according to the prior art,
In the figure, 1a and 1b are a pair of electrodes, 2 is a microgap,
5 is a glass tube.
【第2図】本発明にかかるサージ吸収素子の実施例1、
A図は断面略図、B図は平面図であり、図中21は基
板、22a、22bは一対の電極、23はマイクロギャ
ップ、24はガラス膜、25はキャップ、26は封着
材、27a、27bは電極端子である。FIG. 2 is a first embodiment of a surge absorbing element according to the present invention,
A diagram is a schematic sectional view and B diagram is a plan view, in which 21 is a substrate, 22a and 22b are a pair of electrodes, 23 is a microgap, 24 is a glass film, 25 is a cap, 26 is a sealing material, 27a, 27b is an electrode terminal.
【第3図】本発明にかかる他の実施例の断面略図であ
り、図中31は基板、32a、32bは 一対の電極、
33はマイクロギャップ、34はガラス膜、35はキャ
ップ、36は封着材、37a37bは電極端子である。FIG. 3 is a schematic cross-sectional view of another embodiment according to the present invention, in which 31 is a substrate, 32a and 32b are a pair of electrodes,
33 is a micro gap, 34 is a glass film, 35 is a cap, 36 is a sealing material, and 37a and 37b are electrode terminals.
【第4図】本発明にかかる他の実施例の断面略図であ
り、図中41は基板、42a、42bは一対の電極、4
3はマイクロギャップ、44はガラス膜、45は密封用
の蓋、48は封着材である。FIG. 4 is a schematic sectional view of another embodiment according to the present invention, in which 41 is a substrate, 42a and 42b are a pair of electrodes, and 4 is a pair of electrodes.
3 is a microgap, 44 is a glass film, 45 is a lid for sealing, and 48 is a sealing material.
【第5図】本発明にかかる他の実施例、A図は平面図、
B図は断面略図であり、図中51は基板、52a、52
bは一対の電極、59a、59bはそれぞれ基板51の
表裏面の導体を接続する導電膜である。FIG. 5 is another embodiment according to the present invention, FIG.
FIG. B is a schematic sectional view, in which 51 is a substrate, 52a, 52.
Reference numeral b is a pair of electrodes, and reference numerals 59a and 59b are conductive films for connecting conductors on the front and back surfaces of the substrate 51, respectively.
【第6図】本発明に係る他の実施例、A図は断面略図、
B図は平面図であり、図中61は基板62a、62
a’、62b、62b’は電極、67a、67bは電極
端子である。FIG. 6 is another embodiment according to the present invention, FIG.
B is a plan view, and 61 is a substrate 62a, 62 in the figure.
Reference numerals a ′, 62b and 62b ′ are electrodes, and 67a and 67b are electrode terminals.
【第7図】本発明に係る電極付基板製作を段階的に説明
のための断面略図であり、71は基板、72は印刷・焼
成によった抵抗膜、73は印刷・焼成によった導電膜で
あり、79はスルーホール である。FIG. 7 is a schematic cross-sectional view for stepwise explaining the production of a substrate with electrodes according to the present invention, in which 71 is a substrate, 72 is a resistance film formed by printing / baking, and 73 is a conductive film formed by printing / baking. It is a film, and 79 is a through hole.
【第8図】本発明に係る電極付基板製作を段階的に説明
のための断面略図であり、81は基板、82は高抵抗薄
膜、83は薄膜導電膜であり、89はスルーホールであ
る。FIG. 8 is a schematic cross-sectional view for explaining stepwise production of a substrate with electrodes according to the present invention, 81 is a substrate, 82 is a high resistance thin film, 83 is a thin film conductive film, and 89 is a through hole. .
【第9図】本発明に係る他の実施例を示す図であり、A
図、B図は平面図、C図はA図のa−bの断面略図であ
る。図において、91は基板、92a、92a’、92
b、92b’は電極であり、93はマイクロギャップ、
更に100、100’は電極の除去部である。FIG. 9 is a diagram showing another embodiment of the present invention.
Figures B and B are plan views, and C is a schematic cross-sectional view taken along line ab of FIG. In the figure, 91 is a substrate, 92a, 92a ', 92
b and 92b 'are electrodes, 93 is a microgap,
Further, 100 and 100 'are electrode removal parts.
【第10図】本発明に係る他の実施例を示す断面略図で
あり、図において、101は基板、102a、102
a’、102b、102b’は電極であり、103はマ
イクロギャップである。FIG. 10 is a schematic cross-sectional view showing another embodiment according to the present invention, in which 101 is a substrate and 102a, 102.
Reference numerals a ′, 102b, and 102b ′ are electrodes, and 103 is a microgap.
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【手続補正書】[Procedure amendment]
【提出日】平成8年9月26日[Submission date] September 26, 1996
【手続補正1】[Procedure amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】図面の簡単な説明[Correction target item name] Brief description of drawings
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【図面の簡単な説明】[Brief description of drawings]
【第1図】従来技術によるサージ吸収素子の断面略図、
図中1a、1bは一対の電極、2はマイクロギャップ、
5はガラス管である。FIG. 1 is a schematic sectional view of a surge absorber according to the prior art,
In the figure, 1a and 1b are a pair of electrodes, 2 is a microgap,
5 is a glass tube.
【第2A図】本発明にかかるサージ吸収素子の実施例を
示す断面略図であり、図中21は基板、22a、22b
は一対の電極、23はマイクロギャップ、25はキャッ
プ、26は封着剤、27a、27bは電極端子である。FIG. 2A is a schematic sectional view showing an embodiment of a surge absorbing element according to the present invention, in which 21 is a substrate, 22a and 22b.
Is a pair of electrodes, 23 is a microgap, 25 is a cap, 26 is a sealing agent, and 27a and 27b are electrode terminals.
【第2B図】本発明にかかるサージ吸収素子の実施例を
示す基板の平面略図であり、図中22a、22bは一対
の電極、23はマイクロギャップ、25はキャップ、2
7a、27bは電極端子である。FIG. 2B is a schematic plan view of a substrate showing an embodiment of a surge absorber according to the present invention, in which 22a and 22b are a pair of electrodes, 23 is a microgap, 25 is a cap, and 2 is a cap.
7a and 27b are electrode terminals.
【第3図】本発明にかかる他の実施例の断面略図であ
り、図中31は基板、32a、32bは一対の電極、3
3はマイクロギャップ、34a、34bはガラス膜、3
5はキャップ、36は封着剤、37a37bは電極端子
である。FIG. 3 is a schematic sectional view of another embodiment according to the present invention, in which 31 is a substrate, 32a and 32b are a pair of electrodes, and 3 is a pair of electrodes.
3 is a microgap, 34a and 34b are glass films, 3
5 is a cap, 36 is a sealing agent, and 37a and 37b are electrode terminals.
【第4図】本発明にかかる他の実施例の断面略図であ
り、図中41は基板、42a、42bは一対の電極、4
3はマイクロギャップ、44はガラス膜、45は密封用
の蓋、48は封着剤である。FIG. 4 is a schematic sectional view of another embodiment according to the present invention, in which 41 is a substrate, 42a and 42b are a pair of electrodes, and 4 is a pair of electrodes.
3 is a microgap, 44 is a glass film, 45 is a lid for sealing, and 48 is a sealing agent.
【第5A図】本発明にかかる他の実施例を示す平面略図
であり、図中51は基板、52a、52bは一対の電
極、59a、59bはそれぞれ基板51の表裏面の導体
を接続する導電膜である。5A is a schematic plan view showing another embodiment according to the present invention, in which 51 is a substrate, 52a and 52b are a pair of electrodes, and 59a and 59b are conductors for connecting conductors on the front and back surfaces of the substrate 51, respectively. It is a film.
【第5B図】本発明にかかる実施例第5A図のa−bに
沿った断面略図であり、図中51は基板、52a、52
bは一対の電極、59a、59bはそれぞれ基板51の
表裏面の導体を接続する導電膜である。FIG. 5B is a schematic sectional view taken along the line ab in FIG. 5A of the embodiment according to the present invention, in which 51 is a substrate, 52a, 52.
Reference numeral b is a pair of electrodes, and reference numerals 59a and 59b are conductive films for connecting conductors on the front and back surfaces of the substrate 51, respectively.
【第6A図】本発明に係る他の実施例を示す断面略図で
あり、図中61は基板、62a、62a’、62b、6
2b’は電極、67a、67bは電極端子である。FIG. 6A is a schematic sectional view showing another embodiment according to the present invention, in which 61 is a substrate, and 62a, 62a ′, 62b and 6 are shown.
2b 'is an electrode, and 67a and 67b are electrode terminals.
【第6B図】本発明に係る他の実施例第6A図の平面略
図であり、62a、62a’、62b、62b’は電
極、67a、67bは電極端子である。[Fig. 6B] Fig. 6B is a schematic plan view of another embodiment of the present invention, Fig. 6A, in which 62a, 62a ', 62b and 62b' are electrodes and 67a and 67b are electrode terminals.
【第7A図】本発明に係る電極付基板製作を段階的に説
明のための断面略図であり、第7A図→第7B図→第7
C図と段階的に加工が進められる。図中71は基板、7
2は印刷・焼成によった抵抗膜、79はスルーホールで
ある。[Fig. 7A] Fig. 7A is a schematic cross-sectional view for explaining step by step the production of a substrate with electrodes according to the present invention.
Processing progresses step by step with Figure C. In the figure, 71 is a substrate, 7
Reference numeral 2 is a resistance film formed by printing and firing, and 79 is a through hole.
【第7B図】本発明に係る電極付基板製作を段階的に説
明のための断面略図であり、第7A図に続く段階であ
る。図中71は基板、72は印刷・焼成によった抵抗
膜、72a,72bは印刷・焼成によった導電膜であ
り、79はスルーホールである。[FIG. 7B] FIG. 7B is a schematic cross-sectional view for explaining stepwise the production of the substrate with electrodes according to the present invention, which is the step following FIG. 7A. In the figure, 71 is a substrate, 72 is a resistance film formed by printing and baking, 72a and 72b are conductive films formed by printing and baking, and 79 is a through hole.
【第7C図】本発明に係る電極付基板製作を段階的に説
明のための断面略図であり、第7B図に続く段階であ
る。図中71は基板、72は印刷・焼成によった抵抗
膜、72a,72bは印刷・焼成によった導電膜であ
り、73はマイクロギャップであり、72a’、72
b’はギャップにより分離された抵抗膜による一対の電
極である。また79はスルーホールである。[FIG. 7C] FIG. 7C is a schematic cross-sectional view for explaining stepwise the production of the substrate with electrodes according to the present invention, which is the step following FIG. 7B. In the figure, 71 is a substrate, 72 is a resistive film formed by printing / firing, 72a and 72b are conductive films formed by printing / firing, 73 is a microgap, and 72a ′, 72
Reference numeral b'denotes a pair of electrodes formed by a resistance film separated by a gap. 79 is a through hole.
【第8A図】本発明に係る他の電極付基板製作を段階的
に説明のための断面略図であり、第8A図→第8B図→
第8C図と加工が進む。81は基板、82は高抵抗薄
膜、89はスルーホールである。[Fig. 8A] Fig. 8A is a schematic sectional view for explaining step by step the production of another substrate with electrodes according to the present invention. Fig. 8A → Fig. 8B →
Processing proceeds with FIG. 8C. Reference numeral 81 is a substrate, 82 is a high resistance thin film, and 89 is a through hole.
【第8B図】本発明に係る他の電極付基板製作を段階的
に説明のための断面略図であり、第8A図に続く段階で
ある。81は基板、82a’と82b’は高抵抗薄膜か
らなる一対の電極であり、83はマイクロギャップ、8
9はスルーホールである。FIG. 8B is a schematic cross-sectional view for explaining step-wise the production of another substrate with electrodes according to the present invention, which is a step following FIG. 8A. 81 is a substrate, 82a 'and 82b' are a pair of electrodes made of a high resistance thin film, 83 is a microgap,
9 is a through hole.
【第8C図】本発明に係る他の電極付基板製作を段階的
に説明のための断面略図であり、第8B図に続く段階で
ある。81は基板、82a’と82b’は高抵抗薄膜か
らなる一対の電極でアり、83はマイクロギャップ、8
7aと87bはスルーホール89を貫通して基板の両面
にわたって形成された厚膜導電膜である。[Fig. 8C] Fig. 8C is a schematic cross-sectional view for explaining stepwise the production of another substrate with electrodes according to the present invention, which is the stage following Fig. 8B. 81 is a substrate, 82a 'and 82b' are a pair of electrodes made of a high resistance thin film, 83 is a microgap,
Reference numerals 7a and 87b denote thick-film conductive films formed on both surfaces of the substrate, penetrating the through holes 89.
【第9A図】本発明に係る他の実施例を示す平面略図で
あり、図において、92a、92a’、92b、92
b’は電極であり、93はマイクロギャップ、更に10
0は電極の除去部である。9A is a schematic plan view showing another embodiment according to the present invention, in which 92a, 92a ', 92b and 92 are shown.
b ′ is an electrode, 93 is a microgap, and 10
Reference numeral 0 is a removed portion of the electrode.
【第9B図】本発明に係る他の実施例を示す平面略図で
あり、第9A図とは電極の除去部の形状が異なってい
る。図において、92a、92a’、92b、92b’
は電極であり、93はマイクロギャップ、更に100’
は電極の除去部である。FIG. 9B is a schematic plan view showing another embodiment according to the present invention, in which the shape of the removed portion of the electrode is different from that in FIG. 9A. In the figure, 92a, 92a ', 92b, 92b'
Is an electrode, 93 is a microgap, and 100 '
Is a removal part of the electrode.
【第9C図】本発明に係る実施例を示し、実施例第9A
図のa−bに沿った断面略図であり、図において、91
は基板、92a、92a’、92b、92b’は電極で
あり、93はマイクロギャップ、更に100’は電極の
除去部である。FIG. 9C shows an embodiment according to the present invention, and embodiment 9A
FIG. 9 is a schematic cross-sectional view taken along the line a-b of FIG.
Is a substrate, 92a, 92a ', 92b and 92b' are electrodes, 93 is a microgap, and 100 'is an electrode removal part.
【第10図】本発明に係る他の実施例を示す断面略図で
あり、図において、101は基板、102a、102
a’、102b、102b’は電極であり、103はマ
イクロギャップである。FIG. 10 is a schematic cross-sectional view showing another embodiment according to the present invention, in which 101 is a substrate and 102a, 102.
Reference numerals a ′, 102b, and 102b ′ are electrodes, and 103 is a microgap.
Claims (1)
縁され、マイクロギャップ或いはギャップを形成するよ
うに配置され、且つマイクロギャップ或いはギャップ近
傍に於いて電気抵抗の高い電極部と、外部電極或いは端
子に通ずる比較的電気抵抗の低い電極部とより成る一対
の電極と、前記マイクロギャップ或いはギャップ及びギ
ャップ周辺の電気抵抗の高い電極部と、比較的電気抵抗
の低い電極部の一部含み、前記基板の前記平面を覆う気
密キャップ又は蓋と、前記基板の両端面近傍に設けられ
た一対の電極とを有することを特徴とするマイク ロギ
ャップ或いはギャップ式サージ吸収素子。1. An electrode portion, which is electrically insulated from each other on the same plane of a substrate, is arranged so as to form a microgap or a gap, and has a high electric resistance in the vicinity of the microgap or the gap. A pair of electrodes consisting of an electrode portion having a relatively low electric resistance communicating with the electrodes or terminals, an electrode portion having a high electric resistance around the microgap or the gap and the gap, and a part of the electrode portion having a relatively low electric resistance. A microgap or a gap type surge absorbing element, comprising: an airtight cap or a lid for covering the flat surface of the substrate; and a pair of electrodes provided near both end faces of the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6505896A JPH09223566A (en) | 1996-02-16 | 1996-02-16 | Surge absorption element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6505896A JPH09223566A (en) | 1996-02-16 | 1996-02-16 | Surge absorption element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH09223566A true JPH09223566A (en) | 1997-08-26 |
Family
ID=13275980
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6505896A Pending JPH09223566A (en) | 1996-02-16 | 1996-02-16 | Surge absorption element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH09223566A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6606230B2 (en) * | 2000-06-30 | 2003-08-12 | Mitsubishi Materials Corporation | Chip-type surge absorber and method for producing the same |
KR100413719B1 (en) * | 2000-04-18 | 2003-12-31 | 빙린 양 | Surface mounting surge absorber and surface mounting cap for surge absorber |
CN1319230C (en) * | 1999-11-30 | 2007-05-30 | 三菱综合材料株式会社 | Sheet-shape surging absorber and its mfg. method |
KR100788580B1 (en) * | 2000-08-28 | 2007-12-26 | 타카시 카토다 | Main element of a protector device |
JP2009016616A (en) * | 2007-07-05 | 2009-01-22 | Tdk Corp | Surge absorbing element, and light emitting device |
JP2011254106A (en) * | 2011-09-07 | 2011-12-15 | Stanley Electric Co Ltd | Semiconductor device module and heat conduction chip for use therein |
WO2013146189A1 (en) * | 2012-03-28 | 2013-10-03 | 株式会社村田製作所 | Esd protection device |
JP2017010850A (en) * | 2015-06-24 | 2017-01-12 | 株式会社村田製作所 | ESD protection device |
-
1996
- 1996-02-16 JP JP6505896A patent/JPH09223566A/en active Pending
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1319230C (en) * | 1999-11-30 | 2007-05-30 | 三菱综合材料株式会社 | Sheet-shape surging absorber and its mfg. method |
KR100723572B1 (en) * | 1999-11-30 | 2007-05-31 | 미츠비시 마테리알 가부시키가이샤 | Chip type surge absorber and method of manufacturing the same |
KR100413719B1 (en) * | 2000-04-18 | 2003-12-31 | 빙린 양 | Surface mounting surge absorber and surface mounting cap for surge absorber |
US6606230B2 (en) * | 2000-06-30 | 2003-08-12 | Mitsubishi Materials Corporation | Chip-type surge absorber and method for producing the same |
KR100788580B1 (en) * | 2000-08-28 | 2007-12-26 | 타카시 카토다 | Main element of a protector device |
JP2009016616A (en) * | 2007-07-05 | 2009-01-22 | Tdk Corp | Surge absorbing element, and light emitting device |
JP2011254106A (en) * | 2011-09-07 | 2011-12-15 | Stanley Electric Co Ltd | Semiconductor device module and heat conduction chip for use therein |
WO2013146189A1 (en) * | 2012-03-28 | 2013-10-03 | 株式会社村田製作所 | Esd protection device |
JP5796677B2 (en) * | 2012-03-28 | 2015-10-21 | 株式会社村田製作所 | ESD protection device |
JPWO2013146189A1 (en) * | 2012-03-28 | 2015-12-10 | 株式会社村田製作所 | ESD protection device |
US9516728B2 (en) | 2012-03-28 | 2016-12-06 | Murata Manufacturing Co., Ltd. | ESD protection device |
JP2017010850A (en) * | 2015-06-24 | 2017-01-12 | 株式会社村田製作所 | ESD protection device |
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