JPH0922321A - Backup device for information storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the service life of a backup battery itself from being unnecessarily shortened by preventing the backup battery from being degraded, by stopping the backup function when a first memory cell holds no information. SOLUTION: The positive pole of a backup battery 9 is connected to the collector of an NPN transistor TR1 and the emitter of the NPN transistor TR1 is connected to the anode of a Schottky diode D5 so that the voltage of the positive pole of the backup battery 9 can be applied to the anode of the Schottky diode D5 when the base of the NPN transistor TR1. Namely, when data are stored in a DRAM 2, the voltage is applied through the NPN transistor TR1 to the anode of the Schottky diode D5 and a current flows, but oppositely, when data are not stored, since no voltage is applied to the anode of the diode D5, no current flows from he backup battery 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a backup device for an information storage device, and more particularly to a backup device based on the information storage state of a storage element that retains information by receiving power from a power source. The present invention relates to a backup device for an information storage device that controls opening / closing of a circuit for supplying power to a storage element.

[0002]

2. Description of the Related Art As an information storage device, a personal computer, a printer, a facsimile device and the like have been put into practical use. In the present invention, an electrophotographic plain paper facsimile device for transmitting and receiving a B4 size document is taken as an example. And explain. In general, a plain paper facsimile apparatus using a conventional electrophotographic method divides a memory space of the same storage element into a page memory that stores print data for one page in a bit map and an image data of a transmission or reception document. And a code memory for storing code information. For example, when two 1M × 4bit DRAMs are used as the memory elements provided on the main control board, the memory space becomes 1M bytes, and the page memory has a fine print resolution of B4. Since it is necessary to store the print data of a document of a size, about 700 Kbytes are allocated for this purpose, and therefore, about 30 bytes are left as the code memory.
0K bytes will be allocated.

This code memory can store several tens of pages of code data of an A4 size original document having a normal resolution. Therefore, a function of backing up the code memory is added if necessary by the user. When the power is not supplied from the main power supply, the power is supplied from the backup power supply and the information is retained.

[0004]

In the backup device for the information storage device described above, power is not supplied from the main power source due to a power failure or the power switch is turned off, and at the same time, the function of backing up the code memory always works. Therefore, even if there is no data to be backed up in the code memory and there is no need to back it up, the backup function automatically operates and the current always flows from the backup power supply. This unnecessarily shortens the life of the battery itself when the backup power source is a non-rechargeable primary battery.

Even in the case of a rechargeable secondary battery, the capacity of the backup battery is restored by charging, but for example, it takes several hours to several hours from the completely discharged state to the fully charged state. Need ten hours,
If the main power is turned off again before the charging is completed, it becomes impossible to back up the code memory. Further, the secondary battery has a problem that the performance of the battery is deteriorated by repeating charging and discharging and the life of the battery itself is shortened.

The present invention has been made to solve the above problems, and when the code memory does not need to be backed up, the backup function is stopped so that the backup battery included in the backup power supply is An object of the present invention is to provide a backup device for an information storage device that prevents deterioration and does not unnecessarily shorten the life of the battery itself.

[0007]

In order to achieve the above object, a backup device for an information storage device according to the present invention is supplied from a backup power source when power is not supplied from the main power source. In a backup device for an information storage device, which comprises a first storage element that retains information by power consumption, a second storage element that stores information indicating whether or not information is stored in the first storage element; 2 analysis means for reading the information stored in the storage element and analyzing whether or not the information is stored in the first storage element; and the first storage from the backup power source based on the analysis result of the analysis means. Circuit opening / closing means for opening / closing a circuit for supplying electric power to the element, and when it is determined by the analyzing means that information is stored in the first storage element. The circuit opening / closing means closes the circuit for backing up the first storage element, and conversely, when it is determined that no information is stored in the first storage element, the circuit opening / closing means is A feature is that a circuit for backing up the first memory element is opened.

[0008]

In the backup device for the information storage device of the present invention, the second storage element stores information indicating whether or not information is stored in the first storage element, and the analyzing means is the second storage element. Read the information stored by the
The circuit opening / closing means analyzes whether or not information is stored in the storage element, and opens / closes a circuit for supplying power from the backup power supply to the first storage element based on the analysis result of the analyzing means. If it is determined by the analysis means that information is stored in the first storage element, the circuit opening / closing means closes a circuit for backing up the first storage element, and conversely, When it is determined that no information is stored in the first storage element, the circuit opening / closing means opens a circuit for backing up the first storage element.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A backup device for an information storage device according to the present invention will be described in detail below with reference to the drawings based on an embodiment in which it is applied to an electrophotographic facsimile machine.
FIG. 1 is a circuit diagram showing a memory configuration of a backup device for an information storage device according to the present invention.

The facsimile apparatus is controlled by a central control unit 10 (hereinafter referred to as "CPU 10") provided on a main control board 1, and the CPU 10 includes a ROM for storing a control program and a plurality of units required for control. And a RAM for temporarily storing data and the like, and controls the entire facsimile apparatus.

The main control board 1 has a DR including a DRAM 2 having a storage capacity of 1 Mbyte and a backup control circuit.
An AM control circuit 3 is provided. DRAM2 is 1M
It uses 2 x 4bit DRAM chips, and the page memory is about 700M in 1Mbyte of memory space.
K bytes are allocated, and the remaining about 300 K bytes are allocated to the code memory.

The DRAM control circuit 3 is a circuit for performing data read / write / refresh control for the DRAM chip and a circuit for continuously performing refresh control even when a reference power supply VCC, which will be described later, is not created due to a power failure or the like. It is configured. A memory bus 5 is connected to the DRAM 2 and the DRAM control circuit 3, and control signals such as addresses and data and strobe signals such as RAS, CAS, WE and OE come and go through the memory bus 5.

The main control board 1 is provided with a reference power supply VCC formed from a main power supply (not shown) for supplying electric power.
Also, the power supply ground GND is supplied through the power supply line, the anode of the Schottky diode D1 is connected to the reference power supply VCC, and the cathode of the Schottky diode D1 serves as the reference power supply VBU1. The cathode of the Schottky diode D2 is connected to the cathode of the Schottky diode D1, and the anode of the Schottky diode D2 is connected to the DC-DC converter 7.
Is connected to the OUT terminal.

The reference power source VBU1 is V of the DRAM chip.
DRAM connected to the DD terminal and the DRAM control circuit 3
Power is supplied to the chip and the DRAM control circuit 3, and the power supply ground GND is the GND terminal of the DRAM chip and the DR.
The DRAM control circuit 3 is connected to the AM control circuit 3,
The reference power supply VCC is connected. Further, the main control board 1
Includes a flip-flop circuit 11, an AND gate 12,
A reset IC 13, a work SRAM 14 and a backup battery 4 are provided.

The flip-flop circuit 11 is a circuit for outputting the signal input to the D input terminal from the Q output terminal at the rising edge of the pulse input to its input terminal. In this case, the D input terminal is inverted. Since the Q output terminal (indicated by Q bar in the figure) is connected, the flip-flop circuit 11 performs a toggle operation, and outputs a signal from the Q output terminal each time a pulse is input to the input terminal. Invert.

The AND gate 12 outputs H from its output terminal when the input signals of its two input terminals are both HIGH.
Outputs IGH. The reset IC 13 immediately outputs a LOW signal from its output terminal when the voltage of its input terminal becomes 4.2 V or less. The work SRAM 14 is
It is configured by an SRAM that does not require refresh control, and stores information such as a one-touch dial number and abbreviated dial number, call command information such as timer transmission, and file management information that manages transmitted and received images.

The backup battery 4 is a primary battery such as a lithium battery and backs up the flip-flop circuit 11 and the work SRAM 14. The reference power supply VCC and the anode of the Schottky diode D6 are connected to the input terminal of the reset IC 13, and the cathode of the Schottky diode D6 serves as the reference power supply VBU3 and outputs a predetermined voltage.

The cathode of the Schottky diode D7 is connected to the reference power source VBU3, the positive electrode of the backup battery 4 is connected to the anode of the Schottky diode D7, and the negative electrode of the backup battery 4 is
It is connected to the power supply ground GND. The reference power supply VBU3 has a VDD terminal of the work SRAM 14 and a power supply input terminal of the flip-flop circuit 11 (not shown).
Connected to the SRAM 14 and the flip-flop circuit 1
1 to power.

The output terminal of the reset IC 13 is the CPU 1
0 is connected to the NMI (non-massable interrupt) terminal and the input terminal of the AND gate 12. Further, the input terminal of the AND gate 12 is connected to the O of the CPU 10.
The PORT1 terminal is connected. DAT of CPU10
The work SRAM 1 is connected to the A terminal via the data bus 6.
4 DATA terminals are connected. Also, A of the CPU 10
The work SRA is connected to the DR terminal via the address bus 8.
The ADR terminal of M14 is connected.

The output terminal of the AND gate 12 is connected to the input terminal of the flip-flop circuit 11. Also,
The inverted Q output terminal of the flip-flop circuit 11 is connected to the D input terminal of the flip-flop circuit 11.
The base of the NPN transistor TR1 is connected to the output terminal. The collector of the NPN transistor TR1 is connected to the positive electrode of the backup battery 9, and the emitter of the NPN transistor TR1 is connected to the anode of the Schottky diode D5.

The reference power supply VCC is connected to the anode of the Schottky diode D3, and the cathode of the Schottky diode D3 is connected to the IN terminal of the DC-DC converter 7. The OUT terminal of the DC-DC converter 7 serves as the reference power supply VBU2 and outputs a predetermined voltage. The reference power source VBU2 is connected to the capacitor C1, and the other end of the capacitor C1 has a power source ground GN.
D is connected.

Further, the reference power supply VCC is connected to the resistor R1, and the other end of the resistor R1 has a Schottky diode D4.
Connected to the anode. Schottky diode D4
Is connected to the positive electrode of the backup battery 9,
The negative electrode of the backup battery 9 is connected to the power supply ground GND. Further, the positive electrode of the backup battery 9 is an NPN.
It is connected to the collector of the transistor TR1.

The backup battery 9 is a rechargeable secondary battery such as a lithium ion battery.
Is lower than the voltage of the reference power supply VCC, and is usually 3
It is charged to about V. However, although not shown in the embodiments, the backup battery 9 may be a non-chargeable primary battery. Next, the operation of the backup device for the information storage device according to the present invention configured as described above will be described.

When the main power supply is turned on, the main control board 1 receives the reference power supply VCC and the power supply ground GND.
Is supplied, the reference power supply VCC is connected to the anode of the Schottky diode D1. Therefore, the cathode of the Schottky diode D1 is connected to the reference power supply VBU1.
And a predetermined voltage is generated. This reference power supply VBU1
Is lower than the voltage of the reference power supply VCC by the voltage drop in the Schottky diode D1.

A reference power supply VCC is provided at the anode of the Schottky diode D6, and the Schottky diode D6.
Since the positive electrode of the backup battery 4 is connected to the anode of the Schottky diode 7, the cathodes of the Schottky diode D6 and the Schottky diode D7 serve as the reference power supply VBU3 and generate a predetermined voltage. Since the voltage of the reference power supply VCC is higher than the voltage of the positive electrode of the backup battery 4, the voltage of the reference power supply VBU3 is lower than the voltage of the reference power supply VCC by a voltage drop in the Schottky diode D6. To do.

The voltage of the reference power supply VCC is applied to the anode of the Schottky diode D3. Also, NPN
If the base of the transistor TR1 is HIGH, the voltage of the positive electrode of the backup battery 9 is applied to the anode of the Schottky diode D5, but the voltage of the reference power supply VCC is higher than the voltage of the positive electrode of the backup battery 9. Therefore, regardless of the state of the base of the NPN transistor TR1, the IN terminal of the DC-DC converter 7 has a Schottky diode D3 higher than the voltage of the reference power supply VCC.
A lower voltage is applied as much as the voltage drops at.

A current flows from the reference power source VCC to the backup battery 9 via the resistor R1 and the Schottky diode D4, and the backup battery 9 is charged. D
The OUT terminal of the C-DC converter 7 has a reference power source VBU.
2, the reference power supply VBU2 outputs a predetermined voltage slightly lower than the reference power supply VCC. Reference power supply VBU
2 is connected to the anode of the Schottky diode D2, but the voltage of the reference power supply VCC is the reference power supply VB.
Since it is higher than the voltage of U2, the voltage of the reference power supply VBU1 is lower than the voltage of the reference power supply VCC by the amount of voltage drop in the Schottky diode D1, and no current flows from the reference power supply VBU2 to the DRAM2.

Further, the DRAM 2 and the DRAM control circuit 3
Since the voltage of the reference power supply VBU1 is applied to
According to the instruction of U10, the normal operation for data storage is started, and the DRAM 2 stores the data. As a result, the CPU 10, DRAM 2, DC-D on the main board
Since a predetermined voltage is applied to all circuit elements such as the C converter and the DRAM control circuit 3, the facsimile machine can start a predetermined operation.

First, the CPU 10 performs an initial check of the facsimile machine, and if it is confirmed that the facsimile machine is normal, the CPU 10 analyzes the calling data stored in the work SRAM 14 and stores the image data in the DRAM 2. Know whether or not. For example, the work SRAM 14
If the timer transmission command exists in the CPU 2, the CPU 10 inevitably determines that the image data to be transmitted exists in the DRAM 2.

Normally, when the facsimile apparatus is used for the first time, since the image data does not exist in the DRAM 2,
The CPU 10 confirms the IPORT1 of the CPU 10,
If IPORT1 is HIGH, one pulse is output from OPORT1 to the input terminal of the AND gate 12.
The other input terminal of the AND gate 12 is the reset circuit 13
The output terminal of the reset circuit 13 is HIGH because the voltage of the reference power supply VCC is applied to the input terminal of the reset circuit 13 and the output terminal of the AND gate 12. 1 pulse is output from. As a result, the output of the Q output terminal of the flip-flop circuit 11 is inverted and becomes LOW. That is, CP
When the U10 determines that the image data is not stored in the DRAM 2, the output of the Q output terminal of the flip-flop circuit 11 is set to LOW.

Next, a case where the facsimile operator registers a timer transmission command together with image data to be transmitted will be described. When the timer transmission command is registered in the work SRAN 14, the CPU 10 determines that the image data to be transmitted exists in the DRAM 2, and the IPORT 1 is LOW.
After confirming that, one pulse is output from the OPORT 1 to the input terminal of the AND gate 12. As a result, similarly to the above, the Q of the flip-flop circuit 11 is
The output of the output terminal is inverted and becomes HIGH.

Next, a description will be given of a case where the main power supply stops supplying the reference power supply VCC and the power supply ground GND to the main control board 1 due to a power failure or the like in this state. When the reference power supply VCC and the power supply ground GND are not supplied, the reference power supply VCC is in an electrically open state, and the power supply ground GND is connected to the negative electrode of the backup battery 4 and the negative electrode of the backup battery 9 by the power supply line. Therefore, the potentials of the negative electrodes of the backup battery 9 and the backup battery 4 are the same.

The positive electrode of the backup battery 9 is connected to the collector of the NPN transistor TR1, and the emitter of the NPN transistor TR1 has a Schottky diode D5.
When the base of the NPN transistor TR1 is HIGH, the voltage of the positive electrode of the backup battery 9 is applied to the anode of the Schottky diode D5. That is, if the data is stored in the DRAM2, the data is stored in the DRAM2 via the NPN transistor TR1.
A voltage is applied to the anode of the Schottky diode D5 and a current flows, but conversely, if no data is stored, no voltage is applied to the anode of the Schottky diode D5, so if backup is not necessary, No current flows from the backup battery 9.

Next, a case where data is stored in the DRAM 2 will be described. The base of the NPN transistor TR1 is HIGH, and the Schottky diode D5
Since the cathode of is connected to the IN terminal of the DC-DC converter 7, from the moment the voltage of the reference power supply VCC becomes lower than the voltage of the backup battery 9, the DC-DC
To the IN terminal of the converter 7, a voltage lower than the voltage of the backup battery 9 by the amount of voltage drop in the Schottky diode D5 is applied.

The DC-DC converter 7 boosts the voltage applied to the IN terminal of the DC-DC converter 7 in its internal circuit, and the OUT terminal of the DC-DC converter 7 is the reference power source supplied from the main power source. The reference power supply VBU2 has a predetermined voltage slightly lower than VCC. Reference power supply V
BU2 is connected to the anode of the Schottky diode D2, and at the cathode of the Schottky diode D2, from the moment the voltage of the reference power supply VCC becomes lower than the voltage of the reference power supply VBU2, the voltage of the Schottky diode is higher than the voltage of the reference power supply VBU2. A voltage lower by the voltage drop in the diode D2 is generated, and the cathode of the Schottky diode D2 becomes the reference power supply VBU1.

The reference power source VBU1 is the DRA of the DRAM2.
It is connected to the VDD terminal of the M chip and the DRAM control circuit 3, and supplies power to the DRAM chip and the DRAM control circuit 3. The power ground GND is the GND of the DRAM chip
Since it is connected to the D terminal and the DRAM control circuit 3,
The DRAM control circuit 3 can perform control necessary for holding the data stored in the DRAM 2.

[0037]

As described above, according to the backup device of the information storage device of the present invention, if the first storage element does not hold information, the backup function is stopped, so that a current flows from the backup battery. As a result, deterioration of the backup battery can be prevented, and the life of the backup battery itself is not unnecessarily shortened.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a memory configuration of a backup device for an information storage device according to the present invention.

[Explanation of symbols]

 1 Main Control Board 2 DRAM 3 DRAM Control Circuit 4 Backup Battery 5 Memory Bus 7 DC-DC Converter 9 Backup Battery 10 CPU 11 Flip-Flop Circuit 12 AND Gate 13 Reset IC 14 Work SRAM

Claims (1)

[Claims] 1. A backup device for an information storage device, comprising: a first storage element that retains information by the power supplied from a backup power supply when no power is supplied from the main power supply; A second storage element that stores information indicating whether or not is stored, and an analysis that reads information stored in the second storage element and analyzes whether or not information is stored in the first storage element Means and circuit opening / closing means for opening / closing a circuit for supplying electric power from the backup power source to the first storage element based on the analysis result of the analyzing means. When it is determined that the information is stored in the storage element, the circuit opening / closing means
The circuit for backing up the first memory element is closed,
On the contrary, when it is determined that information is not stored in the first storage element, the circuit opening / closing means opens a circuit for backing up the first storage element. Device backup device.