JPH09223009A - Device and method for processing data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimize the number of processing cycles allowable for executing an instruction at a data processing system. SOLUTION: The data processing system utilizes a data processing instruction word having a 1st field 32 for designating one operation to be executed out of plural arithmetic and logic unit operations and a 2nd field 28 for designating one operation to be executed out of plural shift operations. Both the fields are independent of each other. While depending on the specified combination of both these fields in response to both the fields, an instruction decoder changes the number of processing cycles allowable for each data processing instruction word.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to the field of data processing. In particular, the present invention relates to controlling the number of processing cycles permitted to execute instructions within a data processing system.

[0002]

It is known in the field of data processing systems that different data processing instruction words require different numbers of processing cycles (clock cycles) to execute before the next instruction can begin. . Some instruction words require very little processing to be executed by the system (eg swap register data instructions), while others require very many processing cycles to complete (eg multiple load instructions).

In the case of single type instructions, it is also known that some specific instructions can execute faster than others. For example, a simple shift that moves a small number of bits directly specified by a constant in an instruction performs with less work than a complex arithmetic shift through a large number of bits specified by a value read from a register. be able to.

Another tendency regarding computers is that the number of bits included in program command words is increasing. 3 from 8-bit or 16-bit instruction word
Moved to 2-bit or 64-bit instruction words. In order to efficiently use the space of the instruction set for such a large instruction, Advanced RISC Machines L is used.
It has been proposed in a microprocessor such as ARM6 manufactured by Immited) to include a program instruction word having two or more fields, each field specifying a particular type of arithmetic logic unit operation, or a shift operation. In this way, the coding density can be improved. This technique is particularly well suited for short instruction set computers, where the alternative of using many instruction set bit spaces to provide a large number of more complex and specialized instructions is inadequate.

With respect to the program instruction word having two or more fields, each field specifying one instruction type, there is only one instruction of a different type, for example, a shifter or an adder in the processor. Another problem arises in the desire to use hardware resources.
As a result, the number of processing cycles that must be allowed to execute a program instruction word in order to satisfy all conflicting requirements for hardware resources increases. This runs counter to the constant aim of processing systems to make them run faster.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to speed up execution in a data processing system by controlling the number of processing cycles allowed to execute an instruction.

[0007]

SUMMARY OF THE INVENTION In one aspect, the present invention comprises a first field that specifies one of a plurality of arithmetic logic unit operations and is independent of the first field. An apparatus is provided for processing data in response to a data processing command having a second field that specifies one of a plurality of shift operations. The data processing device executes the arithmetic logic unit operation designated by the first field in a number of processing cycles determined by which of the plurality of arithmetic logic operations is designated by the first field. An arithmetic logic unit, a shifter for executing the shift operation designated by the second field in a number of processing cycles determined by which of the plurality of shift operations is designated by the second field, and An instruction decoder that changes the number of processing cycles allowed to execute the data processing instruction word before starting execution of the processing instruction word depending on both the first field and the second field. Including.

According to the present invention, in a data processing system in which a data processing instruction word has a plurality of fields for independently designating an arithmetic logic unit operation and a shift operation, even if these operations share common hardware resources. The number of processing cycles allowed can be selected depending on both fields. Thus, it is necessary to allow a large number of operations only in the worst case of a combination of arithmetic logic unit operation and shift operation, but in the case of a more general and simple combination, use a smaller number of operations. Is allowed.

The techniques described above could be used in an environment where arithmetic logic operations and shift operations are completely independent, but some combinations require longer operating times than others. However, the present invention provides an embodiment in which the arithmetic logic unit and the shifter sequentially execute the arithmetic logic operation and the shift operation for one or a plurality of combinations of the arithmetic logic operation and the shift operation. , Especially useful.

When deciding whether to increase the total number of processing cycles required by the data processing instruction word, the sequential execution of arithmetic logic operations and shift operations each takes the time required for the other to complete. Become more sensitive to

The difference between the fast and slow shift operations can be considered to be one of the following. Full shift operations where the shift amount is above a predetermined level and simple shift operations where the shift amount is below a predetermined level.

A shift operation with a shift amount smaller than a predetermined level can be processed by a shifter for exclusive use of the shifter which is not shared with other operations. In this way, a small shift amount can be processed at a higher speed. The shift operations selected to be processed by the dedicated shifter are relatively common among typical data processing operations, but are chosen to be relatively easy to read and perform.

There are many different forms of arithmetic logic unit operation. As one way to separate these operations, arithmetic logic unit operations are assumed to be one of the following: Logical operations with one or more operands and arithmetic operations with one or more operands. Typically, arithmetic operations are significantly more complex than logical operations, and therefore take longer to process (eg, when it is necessary to process carry along a series of bit values).

As an effective example of separating the arithmetic logic unit operation and the shift operation as described above, a full shift operation and a logical operation,
Alternatively, in response to a data processing instruction including a single sheet shift operation and an arithmetic operation, the instruction decoder allows X processing cycles before starting execution of the next processing instruction word, and a full shift operation and an arithmetic operation. In some cases, the instruction decoder may allow Y processing greater than X in response to the containing data processing instruction before beginning execution of the next processing instruction word. It will be appreciated that the values of X and Y can take on any number of values, provided that Y is greater than X. However, a typical highly optimized processor (eg RISC processor)
Then, Y = 2 and X = 1.

In another aspect, the present invention provides a first field that specifies one of a plurality of arithmetic logic unit operations and a plurality of shift operations that are independent of the first field. And a second field that specifies one of the following: a method of processing data in response to a data processing instruction word, the method including the following steps. Performing the arithmetic logic unit operation designated by the first field in a number of cycles determined by which of the plurality of arithmetic logic operations is designated by the first field; Performing a shift operation designated by the second field for a number of processing cycles determined by which of the shift operations is designated by the second field;
Changing the number of processing cycles allowed to execute the data processing instruction word before starting execution of the next processing instruction word depending on both the first field and the second field.

[0016]

Next, the present invention will be described with reference to the drawings. FIG. 1 shows a microprocessor circuit 2. The microprocessor circuit 2 includes an address register 4 for storing the address currently appearing on the address bus (not shown). The address incrementer circuit 6 serves to rapidly increment the address stored in the address register 4. This is desirable for high speed sequential access to memory locations and the like. The instruction pipeline and read data register unit 8 serves to store data processing instruction words read from memory for addition to the microprocessor circuit 2. The data processing instruction words at the top of the instruction pipeline 8 are applied to the instruction decoder and control logic unit 10 where they are at least partially decoded. This decoding causes the other elements in the microprocessor circuit 2 to unit 10 the instruction decoder and control logic unit in order to fully process the data processing instruction word.
Can be driven appropriately. Register bank 12 is provided for storing data words to be processed. In the microprocessor circuit 2, a multiplier 14, a barrel shifter 16 and an arithmetic logic unit 18 are included as special processing units that are optimized to perform a given function. These functional units handle most of the processing operations required in the microprocessor circuit 2. The debug circuit 20 is for supporting the debugging of the hardware of the system in which the microprocessor circuit is incorporated during development. The write data register bank 22 serves to buffer the data values output from the microprocessor circuit 2.

FIG. 2 illustrates a first field 32 that specifies one of a plurality of arithmetic logic unit operations.
And a second field 28 that specifies one of a plurality of shift operations. An example of this instruction is Advanced RISC Machines.
Limited) ARM6 processor instruction set. An example of the operation of the present invention will be described below by modifying the manner in which the data processing instruction word is decoded and applied.

From 31 bits to 2 in the data processing instruction word
The condition field 24 occupies up to 8 bits. The condition field 24 enables conditional execution of the entire data processing instruction word, whether the status flag in the microprocessor circuit 2 matches the condition specified in the condition field 24. It depends.

Bits 27 and 26 are always both zero for this particular data processing instruction word. Bit 25 is called the I bit and is the lowest 1 of the data processing instruction word.
Specifies how the two bits (ie bits 11 to 0) are decoded, that is, whether to use the immediate value or the value stored in the register.

The first field 32 (bits 24 to 2)
1) is an arithmetic logic unit 18 and a microprocessor circuit 2
Specifies an operation code (opcode) that selects one of the operations of the plurality of arithmetic logic units to be executed by a combination with other elements in the above. There are 16 possible arithmetic logic unit operations, the format of which is shown in FIG. Of the 16 arithmetic logic unit operations, 8 are arithmetic operations (SUB, RSB, AD
D, ADC, SBC, RSC, CMP, CMN), 8 logical operations (AND, EOR, TS
T, TEQ, ORR, MOV, BIC, MVN).

Bit 20, called the S bit 33, indicates whether the condition flag to which the condition field 24 responds can be changed by the current data processing instruction word. Next 4
Bit 34 (bits 19 through 16) specifies the number of registers in register bank 12 that provide the first operand of this data processing instruction word. Next 4 bits 3
6 (bits 15 to 12) specify the register in register bank 12 for writing the result of the data processing instruction word.

The last 12 bits 28 (bits 11 to 0)
Up to) specify the shift operation to be performed. As mentioned above, the method of decrypting the least significant 12 bits 28 depends on the I bit 30. If I = 0, the least significant 4 bits (bit 3 to 0) are in register bank 1
Specifies which register in 2 to take the value from and shift it to form the second operand. The most significant 8 bits 40 (bits 11 through 4) specify the nature and amount of shift to be performed. Field 4 for shift
Depending on the bits in 0, there is a left logical shift, a right logical shift, an arithmetic right shift or a right rotation shift. Field 40 also either specifies a register in register bank 12 that holds the value of the shift amount to be performed or directly specifies this shift amount as an immediate value. When I = 1, the least significant 8 bits (bit 7 to 0)
Up to) specifies the immediate value that represents the shift amount to be executed. This shift is specified by the remaining 4 bits (bits 11 through 8).

In this embodiment, the left logical shift that shifts the position by any one of 0, 1, 2, and 3 bits is treated as a simple shift that is promptly executed by a dedicated shifter. All remaining shifts are treated as full shifts, which take longer to execute.

FIG. 3 illustrates the instruction decoder and control logic unit 10.
Shows how to decode the first field 32, which specifies the arithmetic logic unit operation, and the second field 28, which specifies the shift operation. The relevant bits of these fields are provided to respective combinatorial logic blocks 42, 44, which output whether these blocks are designated as logical or arithmetic, and whether a simple shift or a full shift. Provides an output indicating if it is specified. These two outputs are AND gate 4
6 and gate 46 outputs a value of 1 if both full shift and arithmetic operations are specified. And gate 4 for all other combinations
The output of 6 is 0. The output of AND gate 46 controls the progress of the instruction along the instruction pipeline, ie, controls the time allowed to execute the current instruction before the next instruction is added to instruction decode and control logic 10. Used to do.

Table 1 shows various combinations of arithmetic and shift operations that produce respective cycle counts.

[0026]

[Table 1]

In a highly optimized microprocessor circuit 2 such as a simplified instruction set calculation circuit, almost all instructions can be executed within one cycle. Only in the worst case, where arithmetic operations and full shifts are specified at the same time, the microprocessor must allow two clock cycles to complete.

[Brief description of drawings]

FIG. 1 illustrates functional elements within a microprocessor.

FIG. 2 illustrates the format and contents of a data processing instruction word having independent fields for specifying arithmetic logic unit operations and shift operations.

FIG. 3 is a diagram showing decoding of the instruction of FIG. 2 to determine the number of processing cycles allowed to complete execution of a data processing instruction word.

[Explanation of symbols]

 2 Microprocessor 18 Arithmetic Logic Unit 28 Second Field 32 First Field

Claims (7)

[Claims] 1. A first field for specifying one of a plurality of arithmetic logic unit operations and a second field for specifying one of a plurality of shift operations independent of the first field. An apparatus for processing data in response to a data processing instruction word having a field of any one of the plurality of arithmetic logic operations,
An arithmetic logic unit that executes the arithmetic logic unit operation designated by the first field in a number of processing cycles determined by the number of processing cycles designated by the first field, and which of the plurality of shift operations is the second field A shifter that executes the shift operation specified by the second field in a number of processing cycles that is determined depending on whether the data processing instruction word is permitted to be executed before the execution of the next processing instruction word is started. An instruction decoder that changes the number of processing cycles performed depending on both the first field and the second field. 2. The apparatus according to claim 1, wherein the arithmetic logic unit and the shifter perform the arithmetic logic operation and the shift operation for one or a plurality of combinations of the arithmetic logic operation and the shift operation. A data processing device that executes sequentially. 3. The apparatus according to claim 1, wherein the shift operation is a full shift operation in which a shift amount is equal to or more than a predetermined level, and a simple shift operation in which the shift amount is less than a predetermined level. And a data processing device. 4. The device according to claim 1, 2, or 3,
A data processor wherein the arithmetic logic unit operation is one of a logical operation with one or more operands and an arithmetic operation with one or more operands. 5. The apparatus of claim 3 or 4 prior to initiating execution of a next processing instruction word in response to a data processing instruction including a full shift operation and a logical operation, or a simple shift operation and an arithmetic operation. , The instruction decoder is greater than X before beginning execution of the next processing instruction word in response to the data processing instruction including X processing cycles and full shift operations and arithmetic operations. Allowing Y processing, the data processing apparatus. 6. The data processing apparatus according to claim 5, wherein Y = 2 and X = 1. 7. A first field specifying one of a plurality of arithmetic logic unit operations, and a second field specifying one of a plurality of shift operations independent of the first field. A field for processing the data in response to a data processing instruction word, which of the plurality of arithmetic logic operations is the first logical operation.
A number of processing cycles determined by the number of processing fields specified by the first field, and a step of executing the arithmetic logic unit operation specified by the first field, and which of the plurality of shift operations is specified by the second field. A step of executing the shift operation specified by the second field in a number of processing cycles determined by whether or not to be executed, and processing permitted to execute the data processing instruction word before starting execution of the next processing instruction word. Changing the number of cycles depending on both the first field and the second field.