JPH0922275A - Liquid crystal display - Google Patents

Abstract

(57) [Summary] [Object] To provide a liquid crystal display device capable of suppressing noise of a voltage applied to a data electrode and capable of operating at a relatively low clock speed. [Configuration] A scan electrode driving circuit includes an orthogonal function generating circuit that generates m kinds of orthogonal functions, and a scan electrode of a liquid crystal panel of N rows and M columns, which is divided into upper and lower groups. m)
, And an output circuit for applying a selection voltage according to the above orthogonal function to the selected scan electrodes, and the data electrode drive circuit displays the display data corresponding to the selected scan electrodes. a shift register for storing m rows, and a latch circuit for fetching display data stored in the shift register and holding the same while the same scan electrode is selected,
An arithmetic unit for simultaneously performing M column operations on the display data held therein and the above orthogonal function, and an output circuit for applying a display voltage according to the operation result to the data electrodes are provided. In this configuration, scanning for m rows is sequentially performed at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a simple matrix type liquid crystal display device which simultaneously drives a plurality of scan electrodes.

[0002]

2. Description of the Related Art As a simple matrix type liquid crystal display device related to the present invention, for example, there is a device disclosed in Japanese Patent Laid-Open No. 6-67628. In this liquid crystal display device, the driving voltage level of the liquid crystal panel is reduced by simultaneously driving a plurality of continuous scan electrodes of the liquid crystal panel, and as a result, the power consumption of the liquid crystal display device is reduced. The liquid crystal display device will be described in detail below with reference to FIGS. 23 to 32.

FIG. 23 is a diagram showing the structure of a liquid crystal display device,
FIG. 24 shows a liquid crystal panel (N rows,
It is a figure for demonstrating the drive method of (M column). Here, the driving method will be described first, and then the configuration of the apparatus will be described.

As shown in FIG. 24, in this device, the voltage function applied to the scanning electrode of the liquid crystal panel is a Walsh function only for eight consecutive rows, and is "0" for the others. If one frame period is T and T / (2N) is regarded as one unit time,
The Walsh function value is generated every unit time, and
One series is generated in a unit time.
At this time, the voltage function f (i) applied to the scan electrodes
And the voltage function g (i) applied to the data electrode is expressed by equations (1) and (2), respectively.

[0005]

[Equation 2]

Here, Fp is a constant shown by the equation (3), and B (i, t) is a function shown in FIG.

[0007]

(Equation 3)

Further, P (i, j) represents display data in which the display dots in the i-th row and the j-th column are "-1" when the display is on and "1" when the display is off. Using equations (1) and (2), the effective voltage value Urms (i, j) of dot U (i, j) is calculated as follows.

[0009]

(Equation 4)

[0010]

(Equation 5)

[0011]

(Equation 6)

[0012]

(Equation 7)

From this, the effective voltage value of U (i, j) is given by equation (4). When U (i, j) is on, P
Since (i, j) is "-1", the above-mentioned voltage effective value is given by equation (5), and when the display is off, P (i, j) is "1", so the above-mentioned voltage effective value is Equation (6) is obtained.

[0014]

(Equation 8)

Further, if the ratio of equations (5) and (6) is obtained, equation (7) is obtained. This result is the same as the operation margin indicating the operation characteristics of the liquid crystal cell.

[0016]

[Equation 9]

From these results, it can be seen that even if a voltage function is applied to the scanning electrodes by the method as shown in FIG. 24, display can be performed on the liquid crystal panel.

Next, a case where the above example is generalized will be described. Here, let us consider a case where the R row of the N rows is the Walsh function and a series of Walsh function values is generated in K unit time. However, in this case, the relations of R <N and K ≧ R are established. F (i), g when generalized
(J) is shown in equations (8) and (9), respectively, and the constant Fp in this case is shown in equation (10).

[0019]

(Equation 10)

Voltage effective value Urm of U (i, j) at this time
Calculate s (i, j).

[0021]

[Equation 11]

[0022]

(Equation 12)

This result agrees with the equation (4). The driving method described above will be referred to as simultaneous driving of a plurality of rows.

Next, the structure and operation of the liquid crystal display device of FIG. 23 will be described.

In FIG. 23, the data electrode driving means 18
Is 1 for analog display data 16 per unit time of orthogonal function
Captures lines and outputs the captured data all at once. This output is supplied to the data electrodes of the first column, the second column, ..., The Mth column as data electrode signals 19 to 21, respectively. The scanning function generating means 22 generates R orthogonal function values for each unit time, and outputs the generation result as scanning function data 23. The scan electrode driving means 24 uses the scan function data 23.
Is taken in and the scanning voltage according to the value of the taken-in data is output. This output is supplied to the scan electrodes of the first row, the second row, ..., The Nth row as scan electrode signals 25 to 27, respectively. The data fetching by the scan electrode driving means 24 is carried out every one unit time in synchronization with the fetching of data by the data electrode driving means 18. The liquid crystal panel 28 displays N rows and M columns according to the scanning electrode signals 25 to 27 and the data electrode signals 19 to 21.

FIG. 25 shows a structural example of the column signal generating means for generating the analog display data 16 described above. In the figure,
The display data 1 is data indicating that the display is on by "1" and the display off by "0", and the writing means 2 displays the display data 1
Is output as A data 3 or B data 4 in units of R rows, and the output is alternately written in the line memories A5 and B6. The reading means 9 reads R pieces of data at a time from the line memory A5 and the line memory B6 whose data writing has been completed, and reads the R pieces of data at a time.
Output as 0. The calculating means 11 has the R row display data 10 and the R row function data 1 generated by the function generating means 12.
The product-sum operation of 3 is performed, and the operation result is the operation data 1
The voltage converting means 15 converts 4 into a voltage signal and outputs it as analog display data.

FIG. 26 shows the configuration of the calculating means 11 when the number of simultaneous selections R = 2. In the figure, inverting circuits 29, 30
Is for logically inverting the R row display data 10 in order to match the R row display data 10 with the expression P (i, j) in the equation (2). The EXOR circuits 31 and 32 each perform an exclusive OR of two inputs, and the decoding means 33
Decodes the input signal according to the relationship shown in FIG.

Next, the operation of the liquid crystal display device configured as described above will be described.

Here, in order to simplify the description, the liquid crystal panel 28 has N = 4 rows, M = 4 columns, and the number of simultaneous selections R = 2, 1
It is assumed that the number of unit time K in one scan is K = 4.

FIG. 28 is a diagram showing the dot information U (i, j) of the liquid crystal panel at this time, and FIG. 29 is R of the function generating means 12.
The figure which illustrated the value in each unit time t of the row function data 13, FIG. 30: R row read data 10 in FIG.
FIG. 6 is a diagram for explaining the relationship between the timings of R and the R row function data 13.

First, in the dot information shown in FIG. 28, the display data 1 is U (1,1), U (1,2) ... U.
(2,1), U (2,2) ... U (4,3), U
The writing means 2 is serially sent in the order of (4, 4).
According to (FIG. 15), the line memory A5 and the line memory B6
Are written alternately in two rows. That is, the first and second
The data of the row is written in the line memory A5, and the data of the third and fourth rows is written in the line memory B6.
Now, assuming that the writing of the data of the first and second rows to the line memory A5 is completed and the writing of the data of the third row to the line memory B6 is started, the reading means 9
As shown in FIG. 30, first, U (1,1) and U (2,2
1), then U (1,2) and U (2,2) ... Read from the line memory A5. In this way, two rows of data are read in one unit time, and the same data is read four times. On the other hand, the function generating means 12 determines the function h shown in FIG. 29 according to the unit time t.
(1) and h (2) are repeatedly generated, and the generation result is 2
Output as bit R row function data 13. Where R
Each bit of the row function data 13 has a function h (1), h
When the value of (2) is "-1", it indicates "0", and when it is "1""
1 ". When the reading means 9 reads the data of the first and second rows four times, this time starts reading the data from the line memory B6. Now, the R row read data 1
If U (1,1) and U (2,1) are output as 0, the arithmetic means 11 receives the input U (1,1), U.
(2, 1) is inverted by the inversion circuits 29 and 30, respectively, and the exclusive OR of the inversion result and h (1) and h (2) is EX.
The ORs 31 and 32 respectively take the results, and the decoding means 33 decodes the result according to the relationship shown in FIG. This means that the following formula is calculated, which is equivalent to calculating the sum of products of formula (2).

[0032]

(Equation 13)

For this reason, the voltage conversion means 15 uses the equations (8),
The operation data 14 is converted into the voltage value of the following equation obtained from (9) and (10), and the conversion result is output as the analog display data 16.

[0034]

[Equation 14]

Here, N = 4 and R = 2, and V
off is the display off voltage as shown in equation (6).
Since it is 1 ”, it is a coefficient for converting into an actual drive voltage.

As described above, the display data 1 is converted into the signal according to the equation (9) by the column signal generating means 17, and further converted into the voltage signal according to the equation (11). The conversion result is sequentially fetched into the data electrode driving means 18 as the analog display data 16 and is output to the data electrodes all at once when the fetching of one row is completed. On the other hand, the scanning function generating means 22 generates the function f shown in FIG. 31 according to the unit time t.
(1), f (2), f (3), f (4) are generated, and the generation result is serially output as the scanning function data 23. The scan electrode driving means 24 takes in the scan function data 23, receives all the data for four columns, and then outputs them as scan electrode signals 25 to 27. FIG. 32 shows the operation timings of the data electrode driving means 18 and the scan electrode driving means 24 at this time.

[0037]

By the way, a liquid crystal controller which outputs the display data for the upper screen and the display data for the lower screen separately corresponding to a liquid crystal panel composed of two upper and lower screens has become popular. The above-mentioned conventional liquid crystal display device cannot use this type of liquid crystal controller because of its configuration.

Also, in the conventional liquid crystal display device, the column signal generating means 17 generates the analog display data 16 applied to the data electrodes, and the generation result is the data electrode driving means 1.
Since the data is serially transmitted to the A.8, noise is likely to be added to the analog display data, which causes a problem that the display on the liquid crystal panel is likely to be uneven. Further, in the conventional liquid crystal display device, the writing means 2
The display data 1 for R rows are once written in the line memories 5 and 6, and the read-out display means 9 repeatedly reads the written display data 1 for R rows every unit time. Therefore, a circuit related to reading the display data 1 is required to operate at high speed. This is an obstacle to reduction of power consumption and price reduction in the display device.

Therefore, an object of the present invention is to provide a liquid crystal display device capable of simultaneously driving a plurality of rows by using a liquid crystal controller corresponding to a liquid crystal panel having a two-screen structure.

It is another object of the present invention to provide a liquid crystal display device capable of suppressing noise of the voltage applied to the data electrode and capable of operating at a relatively low clock speed.

[0041]

A liquid crystal display device according to the present invention has M data electrodes and N scan electrodes, and a difference between a display voltage applied to the data electrodes and a scan voltage applied to the scan electrodes. A liquid crystal panel for displaying N rows and M columns according to the effective value of, a liquid crystal controller for outputting a sync signal and two kinds of display data for a liquid crystal panel composed of two screens, and the scanning according to the sync signal. A liquid crystal display device including scan electrode driving means for outputting a selection voltage to a scan electrode to be scanned among the electrodes, and data electrode driving means for outputting a display voltage corresponding to the display data to a data electrode according to the synchronization signal. The scan electrode driving means includes an orthogonal function generating circuit for generating m kinds of orthogonal functions and two sets of scanning electrodes obtained as a result of dividing the liquid crystal panel into two in the row direction. A selection circuit that simultaneously selects m / 2 scan electrodes in each of the groups, and a selection according to the m orthogonal functions generated by the orthogonal function generation circuit for the m scan electrodes selected by the selection circuit. A scan voltage output circuit that applies a voltage and applies a voltage that invalidates the scan to the remaining (N−m) scan electrodes is provided, and the data electrode driving unit includes the scan selected by the selection circuit. While the display data stored in the m-line shift register and the m-line shift register for storing the display data input corresponding to the electrodes for m rows are fetched, and the same scanning electrode is selected in the selection circuit. A latch circuit that holds only the data, a computing unit that performs computation on the display data held in the latch circuit and the m orthogonal functions generated by the orthogonal function generation circuit, and a performance of the computing unit. A display voltage corresponding to the result, comprising the display voltage output circuit to be applied to the data electrodes.

Further, it has M number of data electrodes and N number of scan electrodes, and N is set in accordance with the effective value of the difference between the display voltage applied to the data electrodes and the scan voltage applied to the scan electrodes.
A liquid crystal panel for displaying rows and M columns, a liquid crystal controller for outputting a synchronizing signal and display data, and a scan electrode driving means for outputting a selection voltage to a scan electrode to be scanned among the scan electrodes according to the synchronizing signal. A liquid crystal display device including a data electrode driving unit that outputs a display voltage corresponding to the display data to a data electrode according to the synchronization signal, wherein the scan electrode driving unit is a quadrature that generates m kinds of orthogonal functions. A function generating circuit, a selection circuit that simultaneously selects m / 2 scan electrodes in each of two scan electrode groups obtained by dividing the liquid crystal panel into two in the row direction, and m selected by the selection circuit. A selection voltage according to m orthogonal functions generated by the orthogonal function generating circuit is applied to the scanning electrodes, and scanning is performed on the remaining (N−m) scanning electrodes. A scan voltage output circuit for applying a voltage to be applied, the data electrode driving means stores an m line shift register for storing display data corresponding to the scan electrode selected by the selection circuit for m rows; A latch circuit that fetches display data for m rows and M columns stored in a line shift register and holds the display data only while the same scan electrode is selected in the selection circuit, and the display data held in the latch circuit and the orthogonal An arithmetic unit that simultaneously performs arithmetic operations for each of M columns on the m orthogonal functions generated by the function generating circuit, and a display voltage for M columns corresponding to the arithmetic result of the arithmetic unit is applied to the data electrode. The display voltage output circuit is provided.

[0043]

In the above-mentioned liquid crystal display device, the scanning electrode driving means simultaneously selects m / 2 scanning electrodes in each of the two scanning electrode groups obtained as a result of dividing the liquid crystal panel into two in the row direction. Therefore, it can operate according to the display data and the synchronization signal generated by the liquid crystal controller corresponding to the liquid crystal panel having the two-screen configuration.

In the data electrode driving means of the liquid crystal display device, the display data is stored in the m line shift register as m.
When only the rows are stored, the stored display data and the orthogonal function supplied from the scan electrode driving means are simultaneously operated for M columns, and the display voltage according to the operation result for M columns is M.
It is simultaneously output to the individual data electrodes. That is, FIG.
Since the display voltage is not transmitted serially or is not shifted in the circuit like the conventional device described in 1., noise is not easily added to the display voltage. Further, since the display data for m rows stored in the m line shift register is held by the latch circuit while scanning is performed, it is not necessary to repeatedly read out the same display data as in the conventional device. It is possible to operate with a synchronization signal that is slower than the conventional device.

[0045]

【Example】

<First Embodiment> A liquid crystal display device according to a first embodiment of the present invention will be described below with reference to FIGS. In this embodiment, one simple matrix type liquid crystal panel is arranged in two rows.
Dividing and driving a plurality of scan electrodes simultaneously in each of the two scan electrode groups obtained thereby. Hereinafter, this driving method is referred to as a multiple-row simultaneous driving method.

[Driving Concept] First, the concept of the multi-row simultaneous driving method in this embodiment will be briefly described. FIG. 2 is a diagram showing a waveform example of a scan electrode drive voltage (hereinafter referred to as a scan voltage) applied to the scan electrodes of the liquid crystal panel of the present embodiment.
As shown in the figure, the scanning electrodes (here, 24
0 rows, Y1 to Y240) are divided into two, and the upper and lower two rows (four rows in total) are simultaneously driven. And
The driven scan electrodes are sequentially shifted in units of divided periods, and one screen of the liquid crystal panel is scanned by shifting (scanning) 60 times. Here, the divided period refers to a period in which the same scan electrode is driven, that is, a period required for one scan, and as shown in FIG. 2, in the first divided period 1, the scan electrodes Y1, Y2, Y121, Y122 are driven simultaneously, and in the divided period 2, scan electrodes Y3, Y4, Y12
3, Y124 are driven at the same time, ..., In the last divided period 60, scan electrodes Y119, Y120, Y239, Y
240 are driven simultaneously. A schematic representation of this driving state is shown in FIG.

In FIG. 2, + Vsel or -Vsel [V] is applied to the scan electrodes selected in each divided period, and 0 [V] is applied to the other non-selected scan electrodes. Here, Vsel is defined by the equation (12) obtained from the equation (10).

[0048]

(Equation 15)

Here, N is the number of scanning electrodes, m is the number of scanning electrodes selected simultaneously, and Vth is the threshold voltage of the liquid crystal. Here, the scanning voltage Fi (t) of the i-th row is expressed by the formula (1
3).

[0050]

(Equation 16)

However, wi is a function that becomes "+1" or "-1" in the selection period and "0" in the non-selection period, and an orthogonal function such as a Walsh function is used in the selection period. Therefore, the value of the equation (13) is equal to the value of the equation (12) by “+1”,
It is a value obtained by multiplying "0" and "-1". With respect to such a scanning voltage, the data electrode drive voltage Gj (t) of the jth column is given by the equation (14).

[0052]

[Equation 17]

Here, Iij is the display data of the display pixel at the i-th row and the j-th column, and takes a value of "-1" when the display is on and "+1" when the display is off. From this, equation (14)
Is transformed using Equations (12) and (13), Equation (1
5).

[0054]

(Equation 18)

Here, D is the number of matches, and the i-th row (i =
1 to N) and the display data Iij and the function wi match (Iij = −1 and wi = −1, or Iij = +)
1 and wi = + 1) are enumerated. The number of matches D defined in this way is an integer in the range of 0 to m.
By driving the liquid crystal panel according to the equations (13) and (15), the effective values Vrms (on) and Vrms (off) given to the display pixel in the i-th row and the j-th column are given by the equations (16) and (17), respectively. ). This result is no different from the conventionally known voltage averaging driving method.

[0056]

[Equation 19]

As described above, in the multi-row simultaneous driving method of this embodiment, the scanning voltage is determined according to equation (13) and the data voltage is determined according to equation (15). Furthermore, when the withstand voltage required for the drive circuit (LSI) for driving the liquid crystal panel is calculated from the equations (13) and (15), N = 24.
It can be seen that when 0, m = 4, and Vth = 2.5 V, the drive circuit on the scanning side requires 28.3 Vp-p and the drive circuit on the data side requires 7.3 Vp-p. On the other hand, in the conventional voltage averaging drive method, N = 240, Vth =
When driving a liquid crystal panel of 2.5 V, both the scanning side driving circuit and the data side driving circuit must have a withstand voltage of 30 V or higher. That is, in this embodiment, the breakdown voltage of the drive circuit on the scanning side is slightly reduced, and the breakdown voltage of the drive circuit on the data side is reduced to ¼ in comparison with the conventional voltage averaging drive method.

[Outline of Configuration] Next, the configuration of the liquid crystal display device which operates according to the multiple simultaneous selection method described above will be described.

FIG. 1 is a block diagram showing the structure of the liquid crystal display device according to this embodiment. In the figure, 50 is a liquid crystal panel, 100 is a liquid crystal controller, 106 and 107 are data electrode drive circuits, 108 is a scan electrode drive circuit, and 110.
Is a power supply circuit. In this embodiment, the liquid crystal panel 50 is assumed to be a simple matrix type liquid crystal panel having display dots of 320 dots in the row direction and 240 dots in the column direction.

The liquid crystal controller 100 is a general one corresponding to a liquid crystal panel having a two-screen structure, and at the timing shown in FIG. 4, the upper screen display data 1 for driving the liquid crystal panel is displayed.
01, lower screen display data 102, data latch signal 103, line signal 104, and head line signal 105.
And a half line signal 150 is generated. As shown in FIG. 4, the display data 101 and 102 are output for each dot in synchronization with the data latch signal 103, and the line signal 104 is output each time the display data for one row is output. The head line signal 105 is output every time a predetermined number of lines of display data are supplied, and the half line signal 150 is output in synchronization with the line signal 104 at twice the clock speed of the line signal 104. It

The scan electrode drive circuit 108 uses the line signal 1
04, head line signal 105, and half line signal 150
2 line signal 116 based on the input signal.
And the scanning function data 114 are generated to generate the electrode driving circuit 10.
6 and 107, and the scan electrode drive voltage 12
2 is generated and supplied to the liquid crystal panel 50.

The data electrode drive circuits 106 and 107 simultaneously input the upper screen display data 101 and the lower screen display data 102 in synchronization with the data latch signal 103, and simultaneously generate the 2-line signal 116 generated by the scan electrode drive circuit 108. And the scanning function data 114 are input, and the scanning function data 114 and the display data 10 obtained by capturing only the upper and lower two lines
1 and 102 are subjected to a predetermined calculation process, and a data electrode drive voltage (hereinafter referred to as a data voltage) according to the calculation result.
120 and 121 are output to the data electrodes of the liquid crystal panel 50.

The power supply circuit 110 inputs the 5V power supply voltage 111, and receives the five-level voltages Vx0, Vx1, Vx2, Vx.
Data electrode drive circuit power supply voltage 112 composed of 3 and Vx4
And scan electrode drive circuit power supply voltage 113 composed of three-level voltages Vy0, Vy1, and Vy2 are generated and supplied to data electrode drive circuits 106 and 107 and scan electrode drive circuit 108, respectively.

In the following, the scan electrode drive circuit 10 described above is used.
8, data electrode drive circuit 106, and power supply circuit 110
Each configuration and operation of will be described in more detail. In each drawing used in the following description, corresponding parts and signals are designated by the same reference numerals.

[Structure of Scan Electrode Driving Circuit 108] First,
The scan electrode drive circuit 108 will be described. 5 is a block diagram showing a configuration example of the scan electrode drive circuit 108. In the figure, 160 is a scan function generation circuit, 161 is a clock control circuit, 163 is a decoder, 165 is an output circuit, 166 is a level shifter, and 168 is It is a voltage selector. The structure of the scanning function generating circuit 160 is shown in FIG. 6, and the timing chart is shown in FIG. In FIG. 6, the frame counter 172 counts the head line signal 105 at the timing of the half line signal 150 and outputs it as a frame count value 174. The half-line counter 173 counts the half-line signal 150 using the head line signal 105 as a reset signal, outputs the result as a half-line count value 175, and outputs a two-line signal 176 every four times counting. (See FIG. 7). Here, the period in which the half line count value is "0" to "3" is the divided period 1 in FIG.
, The period of “4” to “7” corresponds to the divided period 2, and the period of “236” to “239” corresponds to the divided period 60.

The scanning function decoder 177 generates scanning function data 178 shown in FIG. 8 based on the frame count value 174 and the half line count value 175. As shown in FIG. 8, the scanning function data 178 has a value w that repeats at a cycle “4” for the half line count value 175.
Has 0, w1, w2, w3, and has a frame count value of 17
If 4 is an even number, half line count value 17
When 5 is "0", w0 to w3 are all "1", and when the count value 175 is "1", the scan function data 178 is w0.
= 1, w1 = 1, w2 = 0, w3 = 0, ...
When the frame count value 174 is an odd number, each value w0 to w3 is a logical inversion of the value when it is an even number. By selecting the scan function data 178 in this way, the polarity can be alternately inverted while the effective value of the voltage applied to the liquid crystal cell is made constant for each frame, and therefore, the deterioration of the liquid crystal material is caused. Can be prevented. The selector 179 selects an input signal according to the master mode signal 171, and when the mode signal 177 instructs master driving, the scan function data 178 generated by the scan function decoder 177.
Is output as the scanning function data 114 and the 2-line signal 17 generated by the half-line counter 173 is output.
6 is output as a 2-line signal 116. On the contrary, when the mode signal 177 indicates slave drive, the scan function input data 170 and the 2-line input signal 169 supplied from the outside of the scan electrode drive circuit are supplied to the scan function data 114 and the 2-line signal 116, respectively. Output as.
When slave driving is instructed by the master mode signal 171, the frame counter 172, the line counter 173, and the scanning function decoder 177 stop their operations.

The clock control circuit 161 shown in FIG. 5 generates and outputs the clock control output 162 based on the head line signal 105, the 2-line signal 116, and the mode signal 118 input from the outside. This clock control output 162 has 120 signals, which are usually logic "1" (162
-1 to 162-120). When the mode signal 118 is logic "0", the clock control circuit 161 first synchronizes the clock control outputs 162-1 and 162-61 with logic "0" in synchronization with the two-line signal 116, and then 62 -2 and 162-62 are set to logical "0", and finally 162-60 and 162-120
Is set to logic "0". On the contrary, when the mode signal 118 is logic "1", the clock control 161 controls the 2-line signal 11
Clock control outputs 162-1 and 162-
2, ..., 162-60, ..., 162-120 are set in the order of logic “0”. In this case, since the liquid crystal panel 50 having 240 display rows is driven by one scan electrode driving circuit, the mode signal 118 is set to logic "0".

FIG. 9 shows a configuration example of the decoder 163 in FIG. In the figure, the latch circuit 180 takes in the scanning function data 114 with the half line signal 150, and outputs the result (w0 to w3) taken in. Decoder 16
3-1 to 163-120 are configured as shown in FIG. 10, and decode the scan function data 114 according to the output 162 of the clock control circuit 161. Here, each decoder is in a selected state when the output 162 is a logic "0", and is in a non-selected state when the output 162 is a logic "1". The selected decoder outputs a decode output 164 corresponding to the scanning function data 114 latched by the latch circuit 180, and the remaining unselected decoders output a decode output 164 indicating non-selection.

FIG. 11 shows a configuration example of the output circuit 165 in FIG. In the figure, a level shifter 166 level-shifts and outputs each of the decoder outputs 164. The voltage selector 168 includes an output transistor provided corresponding to each scan electrode, selects one of the voltages Vy0, Vy1, and Vy2 according to the output of the level shifter 166, and outputs the selection result as the scan electrode voltage 122. Specifically, when the scan function data 114 of logic “1” is input to the decoder in the selected state, the corresponding output transistor selects the voltage Vy0 (+ Vsel shown in FIG. 12) and the decoder in the selected state selects it. When the scan function data 114 of logic "0" is input, the corresponding output transistor selects Vy2 (-Vsel shown in FIG. 12).
When the decoder is in the non-selected state, Vy1 (0V) is selected regardless of the logic of the scan function data 114.

FIG. 12 shows the operation timing of each part of the scan electrode drive circuit 108 described above.

[Configuration of Data Electrode Driving Circuit 106] Next, the data electrode driving circuits 106 and 107 of FIG. 1 will be described.

FIG. 13 shows the data electrode drive circuits 106 and 1.
It is a block diagram which shows the structural example of 07, and FIG. 14 is a timing chart for demonstrating operation | movement of the said circuit. FIG.
In FIG. 3, 132 is a timing adjustment circuit, and 134 is 2
The line shift register U and the two-line shift register L, 136 are data latches, 138 is an arithmetic unit, 140 is an output circuit, 141 is a level shifter, and 143 is a voltage selector.

The timing adjusting circuit 132 generates a shift clock 133 whose state is sequentially shifted according to the data latch signal 103. Here, the shift clock 13
Generation 3 starts from the time when the enable input signal 130 is input, and when the generation is completed, the enable output signal 131 is output. The enable output signal 131
Is supplied to the enable input of the data electrode drive circuit of the next stage.

The 2-line shift register 134 fetches the upper screen display data 101 and the lower screen display data 102 in the order shown in FIG. 14 in accordance with the shift clock 133, and outputs the fetched result as a shift register output 135. For example, immediately after the head line signal 105 is input, first, the 2 line shift registers 134-1 and 1
34-3 fetches the display data of the 1st row and the 121st row, respectively, and then the 2-line shift register 134-
The display data of the 2nd row and the 122nd row are respectively captured in 2,134-4.

The data latch 136 latches the shift register output 135 at the timing of the 2-line signal 116,
The result is output as the latch output 137, and the arithmetic unit 13
8 performs a predetermined operation on the latch output 137 and the scan function data 114.

The output circuit 140 is composed of a level shifter 141 and a voltage selector 143. The level shifter 141 level shifts the output 139 of the arithmetic unit 138, and the voltage selector 143 responds to the output 142 of the level shifter 141 by the data electrode drive circuit. One of five levels of the power supply voltage 112 is selected, and the selection result is output as the data electrode voltage 120.

The arithmetic unit 138 and the output circuit 140 will be described in more detail.

FIG. 15 is a block diagram showing a configuration example of the arithmetic unit 138, and in this figure, a configuration corresponding to one data electrode is shown. That is, in the present embodiment, the data electrode driving circuits 106 and 107 are each 160
Since each data electrode is driven, 160 calculators are provided in each data electrode driving circuit. Also, here, the arithmetic unit in the figure is 160
The description will be given assuming that the output corresponds to the output of the j-th column.

In the figure, exclusive OR circuits 151 to 1
Reference numeral 54 is the output of the j-th column of the data latch 136 of FIG.
7 and the scanning function data 114 are subjected to an exclusive OR operation, and the operation result is output as data E0, E1, E2, E3. The decoder 155 selects S0 and S which are selection signals 139 from the data E0 to E3 according to the relationship shown in FIG.
1, S2, S3, S4 are generated. That is, at this time, if the number of the input data E0 to E3 having the logic "1" is 0, the S0 is the logic "1", and if the data is one, the S1 is the logic "1", 2
If there are three, S2 is a logical "1", if three, S3 is a logical "1", and if four, S4 is a logical "1". The selection signal 139 thus generated is supplied to the output circuit 140 shown in FIG. The arithmetic processing of the arithmetic unit 138 is represented by the equation (18).

[0080]

(Equation 20)

Here, m is the number of scan electrodes to be simultaneously selected (here, m = 4), wi is a function which becomes “+1” or “−1” in the selection period and “0” in the non-selection period, Iij Is display data of the display pixel in the i-th row and the j-th column.

FIG. 17 shows the output circuit 140 shown in FIG.
FIG. 16 is a circuit diagram showing a configuration example of the level shifter 141 and the voltage selector 143, in which the configuration of the portion connected to the arithmetic unit shown in FIG. 15 is shown. That is, FIG.
15 circuits correspond to the output of the j-th column of the data electrode driving circuit and are provided in the same number as the arithmetic units in FIG.

In the figure, the selection signal 139 (S0 to S4) generated by the arithmetic unit is supplied to the level shifter 141 of the output circuit 140, and the level shifter 141 needs this selection signal 139 to control the voltage selector 143. Convert to voltage signal. The output transistors 143-1 to 143-5 of the voltage selector 143 are the level shifters 141.
In accordance with the output of the above, the voltage Vx0, Vx1, Vx2 of five levels included in the data electrode drive circuit power supply voltage 112 is
One of Vx3 and Vx4 is selected and output as the jth data voltage 120.

As described above, in the data drive circuit of this embodiment, the arithmetic unit and the output transistor 143 are provided corresponding to each data electrode of the liquid crystal panel, and the voltage selected by each output transistor 143 is kept as it is. Since data is output to the data electrode, noise is unlikely to be added to the data voltage.

Further, the display data for four rows fetched in the two-line shift register 134 is held in the data latch circuit 136 while the same scan electrode is selected, so that it is the same as in the conventional device. It is not necessary to repeatedly read the display data of 1), and therefore it is possible to operate with a clock signal that is slower than the conventional device.

[Power Supply Circuit 110] Next, the power supply circuit 110 in FIG. 1 will be described.

FIG. 18 is a diagram showing a configuration example of the power supply circuit 110. In the figure, a DC-DC converter 190
From the 5V power supply 111 to + 15V, -15V, + 5V,
Generate four levels of voltage of -5V. Among the generated voltages, the voltage of + 15V is divided by the resistors R1 and R2, then current-amplified by the OP amplifier 191, and output as the voltage Vy0. Similarly, a voltage of -15V is applied to the resistor R1,
After being divided by R2, the current is amplified by the OP amplifier 192 and output as the voltage Vy2. Further, the voltage Vy1 of the ground level (0V) is also output, and these voltages Vy
The scan electrode drive circuit power supply voltage 113 is composed of 0 to Vy2. On the other hand, the voltage of + 5V is applied to the resistors R3, R4, R
After being divided into two levels of voltage by 5, the OP amplifier 19
Current amplification is performed at 3 and 194, and the voltages Vx0 and Vx are obtained.
Output as 1. Similarly, a voltage of -5V is applied to the resistor R
After being divided by 3, R4 and R5, OP amplifier 195, 1
The current is amplified at 96 and output as voltages Vx3 and Vx4. Further, the ground level voltage Vx2 is also output, and these voltages Vx0 to Vx4 form the data electrode drive circuit power supply voltage 112.

Each set voltage of the scan electrode drive circuit power supply 113 is N = 240, m = 4, Vth in the equation (12).
= 2.5V, Vy0 = 14.2V, Vy1 = 0V, Vy2 = -14.
It becomes 2V. Further, the set voltage of the data electrode drive circuit power supply 112 is calculated from the equation (15) as follows: Vx0 = + 3.66V, Vx1 = + 1.83V, Vx2
= 0V, Vx3 = -1.83V, Vx4 = -3.66V. In this embodiment, the resistors R1 to R5 are selected so that such a set voltage can be obtained.

[Operation of Liquid Crystal Display Device] Next, the operation of the liquid crystal display device (FIG. 1) described above will be described.

When the line signal 104 is supplied, the scan electrode driving circuit 109 selects the scan electrodes in each of the upper and lower two rows at the timing of the two line signal 116 and responds to the internally generated scan function data 114. Scan voltage (Vy0, V
y2) is output to the selected scan electrode. On the other hand, the data electrode drive circuits 106 and 107 are connected to the scan electrode drive circuit 109.
The scan function data 11 supplied from the scan electrode driving circuit 109 is obtained by fetching the display data 101 and 102 for each of the upper and lower two rows in one cycle unit of the two-line signal 116 supplied from
4 and the read display data are calculated, and the data voltage (Vx0 to Vx4) corresponding to the calculation result is output to the data electrode. The scanning function data changes four times in one cycle of the two-line signal 116, and the scanning voltage and the data voltage also change accordingly. In this way, the liquid crystal panel 50 displays two lines each in the upper and lower rows according to the display data 101 and 102.

As described above, according to this embodiment, in each of the liquid crystal panels divided in the row direction,
Multiple rows can be driven simultaneously.

[Another Example of Scan Function] In this embodiment, the scan voltage (see FIG. 2) is changed in the same pattern for each divided period by the scan function data 178 generated by the scan function generation circuit 160. However, different combinations of scanning voltages may be given for each divided period. Further, the polarity of the scanning voltage may be inverted for each divided period. Furthermore, the combination of scanning voltages may be changed for each frame.

Here, the influence of the characteristics of the scanning function on the display state of the liquid crystal panel will be considered. It is known that the optical characteristics of liquid crystal change depending on the frequency of the applied voltage change. The difference in the number of times that the voltage polarity of the scanning voltage changes results in the display unevenness because the difference in the frequency causes the difference. In addition, if there is an imbalance in the voltage polarities of the scanning voltages of the selected plural rows in one divided period (that is,
If the selected + Vsel voltage and the number of + Vsel voltages are biased), a DC component is given to the liquid crystal cell during the one-divided period, which may cause optical flicker or flicker. In this embodiment, as shown in FIG.
There are a total of 4 scan voltages: one that does not change during the divided period, one that changes the voltage polarity once, one that changes the voltage polarity twice, and one that changes the voltage polarity three times.
There are different types, and the frequency of voltage change varies. Further, as shown in FIG. 8, when the frame count value 174 = even number and the line count value 175 = 0 to 3, ten + Vsel voltages indicated by “1” and −V indicated by “0” are shown.
There are 6 sel, while the frame count value is 174
= Odd number, line count value 175 = 0 to 3, "1"
There are 6 + Vsel voltages indicated by, and indicated by "0"-
The number of Vsel becomes 10, and four imbalances occur between + Vsel and −Vsel in each frame.

However, the frequency variation of the voltage change and the imbalance of the voltage polarity can be prevented by properly selecting the scanning function. FIG. 19 shows an example of the scanning function that eliminates the voltage polarity imbalance, and FIG. 20 shows the waveform of the scanning voltage when the scanning function is used. As can be seen from FIGS. 19 and 20, with this scanning voltage, not only the polarity of the voltage changes for each frame, but also the pattern of the voltage changes for every two frames. Further, in this scanning voltage, + Vsel is 8 and -Vsel is 8 in one divided period, and the voltage polarities are balanced. Therefore, if this scanning voltage is used, the display voltage is higher than that in FIG. Flicker can be suppressed.

<Second Embodiment> Next, a second embodiment of the present invention will be described.

FIG. 21 is a diagram showing the structure of a liquid crystal display device according to the second embodiment. The configuration shown in this figure is similar to that of the first embodiment (FIG. 1) except that the display size of the liquid crystal panel is 480 rows and that two scan electrode driving circuits are used. Therefore, the parts corresponding to those in FIG. 1 are denoted by the reference numerals in which the hundreds place of the reference numerals used in FIG. 1 is changed from “1” to “2”, and the detailed description thereof will be omitted.

In FIG. 21, the liquid crystal controller 200
Is set so that the number of display lines is 480 and the liquid crystal panel is configured to have two upper and lower screens, and the data line signal 204 is generated for 240 clocks in one cycle of the head line signal 205. Further, the liquid crystal controller 200 uses the display data of the first to 240th lines as the upper screen display data 201 and the 241st to 480th as the lower screen display data 202.
The display data of the rows are sequentially output in synchronization with the data line signal 204.

The scan electrode drive circuit 208 drives the scan electrodes in the first to 240th rows according to the upper screen display data 201, and the scan electrode drive circuit 209 drives the lower screen display data 202.
The scan electrodes of the 241-480th rows are driven in accordance with the above.
The basic operation of these scan electrode drive circuits is the same as that of the first embodiment, but there is a slight difference here in that master / slave drive is performed and the mode signal 218 is set to logic "1". First, master / slave driving will be described. In this embodiment, the scan electrode drive circuit 208 is set to the master drive mode and the scan electrode drive circuit 209 is set to the slave drive mode by the above-mentioned master mode signal. As a result, the scan electrode driving circuit 208 generates the scan functions 214 and 2 generated inside itself.
It operates according to the line signal 216 and gives the generated signal to the scan electrode driving circuit 209. The scan electrode drive circuit 209 operates according to the scan function 214 and the two-line signal 216 provided by the scan electrode drive circuit 208. On the other hand, since the mode signal 218 is set to logic "1", the clock control circuit in each scan electrode drive circuit first outputs the clock control output 262-1 to logic "0" in synchronization with the two-line signal. After that, the clock control outputs 262-2, 262-3, ..., 262-60, 2
62-61, ..., 262-120 in the order of logic “0”
To

FIG. 22 shows the timing relationship of the signals of the respective parts of the liquid crystal display device described above, and the operation of the device will be described. In FIG. 21, in the scan electrode drive circuit 208 set to the master drive mode, the scan function generation circuit 26
0 generates and outputs the 2-line signal 216 and the scan function data 214. According to the output, the scan electrode drive circuit 20
Each of the clock control circuits 261 and the decoder circuits 263 in the Nos. 8 and 209 operates to output the decoder outputs 26 of two rows.
4 is generated. Each output circuit 265 selects one of the three levels of the scan electrode drive circuit power supply voltage 213 and outputs it as the scan voltages 222 and 223. Thus, each scan electrode drive circuit drives the scan electrodes of two rows at the same time in synchronization with the two-line signal 216, and the liquid crystal panel 6 is driven.
When viewed as 0, a total of 4 rows are simultaneously selected, and 4 rows are simultaneously selected and driven as in the first embodiment.

Although the set voltage of the power supply circuit 210 is determined by the equations (12) and (15) and is different from that in the first embodiment, the set voltage of the DC-DC converter in the power supply circuit 110 (FIG. 18) is changed. This setting voltage can be obtained by slightly changing the rating and the resistance value.

As described above, according to the present embodiment, by providing a plurality of scan electrode driving circuits, 480
The liquid crystal panel of a row can be driven, and the same liquid crystal panel as described in the first embodiment can be simultaneously driven in a plurality of rows.

Although the half line signal is indispensable in the above-described two embodiments, some liquid crystal controllers do not output the half line signal, so that the half line signal is generated from the line signal and the data latch signal. The circuit may be provided in the scan electrode driving circuit.

Further, as described above, the display quality of the liquid crystal panel is largely influenced by the setting of the scan function, so that the scan function generating circuit is arranged outside the scan electrode driving circuit and the liquid crystal driven by the scan function generating circuit is arranged. You may make it set the scanning function suitable for the display characteristic of the panel. in this case,
All the scan electrode drive circuits are set in the slave mode for use.

In the embodiment, the scanning function generating circuit is composed of the frame counter, the half line counter and the decoder circuit, but a data ROM may be used instead of the decoder circuit. By doing so, it becomes possible to easily set or change the scanning function.

Further, in the embodiment, only the case where four lines are selected at the same time has been described. However, the present invention is not limited to this, and the cost of the data electrode drive circuit or the scan electrode drive circuit can be reduced, mass production can be performed, etc. The number of lines selected simultaneously may be increased or decreased. However, when changing the number of simultaneously selected rows, it is necessary to make the number of stages of shift registers in the data electrode drive circuit, the number of stages of arithmetic circuits, the scan function generation circuit in the scan electrode drive circuit, etc. correspond to the number of simultaneously selected rows.

By the way, a general liquid crystal controller employs a frame gradation display method (see "Liquid Crystal Device Handbook" edited by the 142nd Committee of the Japan Society for the Promotion of Science) as a method for displaying gradation on a liquid crystal panel. Therefore, in this gradation display method, the display data corresponding to each display pixel is limited to display on or display off in each frame. Since the liquid crystal display device of the embodiment completes the display in one frame, a desired gradation display can be performed using the liquid crystal controller adopting the above gradation display method. Further, the display data and various clock signals used in the embodiments are the same as those generated by a general liquid crystal panel interface. That is, the liquid crystal display device of the embodiment is compatible with a ready-made display controller, and various embodiments can be realized.

Further, in the display device of the embodiment, as the liquid crystal panel, not only the liquid crystal panel adopting the medium speed response liquid crystal but also the liquid crystal panel adopting the high speed response liquid crystal can be used. The medium-speed response liquid crystal panel can be driven at a frame frequency of about 70 Hz, which is the same as CRT driving, but when the high-speed response liquid crystal panel is driven at a frame frequency of about 70 Hz, a luminance reduction phenomenon called a frame response occurs and display deterioration is caused. . As a countermeasure against this, it is considered to increase the driving frequency, and it is particularly desirable to set the driving frequency to 150 Hz or higher. In the embodiment, the drive frequency can be easily switched by controlling the display data and the timing of various clock signals by the liquid crystal controller, and the other circuits can be used as they are without any change.

Further, in the simple matrix type liquid crystal display device, the change in the voltage applied to the data electrode appears as crosstalk on the scan electrode, and particularly in the non-selection period, the scan voltage which should be constant at 0 V is spiked. Noise appears as crosstalk, and the effective value of the voltage applied to the liquid crystal fluctuates, causing display unevenness. The spiked noise is generated without being absorbed by the output impedance of the scan driver and the impedance of the power supply circuit connected thereto. On the other hand, in this embodiment, the scanning voltage during the non-selected period is set to the ground level (0
By setting V), the impedance of the power supply circuit is made sufficiently small, so spike noise can be absorbed and display unevenness due to crosstalk can be reduced. In addition, parts such as an OP amplifier for generating the voltage in the non-selected period are unnecessary, so that the power supply circuit can be downsized and the cost can be reduced. Furthermore, in the power supply circuits 110 and 210 of the embodiment, 5
Since a DC-DC converter that is driven by a V power supply is used, the liquid crystal display device is driven by a logic drive circuit.
It is sufficient to provide a V power supply, and it is not necessary to provide a power supply dedicated to liquid crystal driving as in a conventional liquid crystal display device.

[0109]

As described above, according to the present invention, it is possible to provide a liquid crystal display device capable of simultaneously driving a plurality of rows by using a liquid crystal controller corresponding to a liquid crystal panel having a two-screen structure. it can.

Further, it is possible to provide a liquid crystal display device which can suppress the noise of the voltage applied to the data electrode and can operate at a relatively low clock speed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a liquid crystal display device according to a first embodiment of the present invention.

2 is a waveform example of a scanning voltage applied to the scanning electrodes of the liquid crystal panel of FIG.

FIG. 3 is a schematic description of the waveform of FIG.

FIG. 4 is a diagram showing timings of control signals and display data output from the liquid crystal controller 100.

5 is a detailed block diagram of a scan electrode driving circuit 108. FIG.

FIG. 6 is a detailed block diagram of a scan function generating circuit 160.

FIG. 7 is a timing diagram illustrating the operation of the scan function generating circuit 160.

FIG. 8 is an example of scan function data generated by a scan function generating circuit 160.

9 is a detailed block diagram of a decoder 163. FIG.

FIG. 10 is a detailed configuration diagram of decoders 163-1 and 163-61.

FIG. 11 is a detailed configuration diagram of an output circuit 165.

FIG. 12 is a timing diagram illustrating an operation of the scan electrode driving circuit 108.

FIG. 13 is a detailed block diagram of the data electrode driving circuit 106.

FIG. 14 is a timing diagram illustrating an operation of the data electrode driving circuit 106.

FIG. 15 is a detailed configuration diagram of a computing unit 138.

16 is a diagram showing the logic of a decoder 155 in the arithmetic unit 138. FIG.

FIG. 17 is a detailed configuration diagram of an output circuit 140, a level shifter 141, and a voltage selector 143 which configure the output circuit 140.

FIG. 18 is a detailed configuration diagram of the power supply circuit 110.

FIG. 19 is an example of scan function data generated by the scan function generating circuit 160.

20 is an example of a scanning signal waveform based on the scanning function data of FIG.

FIG. 21 is a configuration diagram of a liquid crystal display device according to a second embodiment of the present invention.

22 is a timing chart for explaining the operation of scan electrode drive circuit 208 in FIG. 1. FIG.

FIG. 23 is a diagram showing a configuration example of a conventional liquid crystal display device.

FIG. 24 is a diagram for explaining a driving method in the device of FIG. 23.

FIG. 25 is a block diagram showing a specific example of column signal generating means.

FIG. 26 is a block diagram showing a specific example of the calculating means 11.

FIG. 27 is a diagram showing the logic of the decoding circuit 33.

28 is a diagram showing dot information when the liquid crystal panel 28 in FIG. 1 has four rows and four columns.

FIG. 29 is a diagram showing an example of the function data 23 output by the row function generating means 12.

FIG. 30 is a diagram for explaining a timing relationship between R row read data 10 and R row function data 13.

FIG. 31 is a diagram showing function data 23 generated by the row function generating means 12.

FIG. 32 shows column electrode driving means 18 and row driving means 24.
FIG. 6 is a timing chart for explaining the operation of FIG.

[Explanation of symbols]

1 ... Display data, 2 ... Writing means, 3 ... A data, 4
B data, 5 line memory A, 6 line memory B, 7 read data A, 8 read data B, 9
... reading means, 10 ... R row display data, 11 ... computing means, 12 ... function generating means, 13 ... R row function data, 14
... operation data, 15 ... voltage conversion means, 16 ... analog display data, 17 ... column signal generating means, 18 ... data electrode driving means, 19-21 ... data electrode signals, 22 ... scanning function generating means, 23 ... scanning function data , 24 ... Scan electrode driving means, 25-27 ... Scan electrode signals, 28 ... Liquid crystal panel,
29, 30 ... Inversion circuit, 31, 32 ... EXOR circuit, 3
3 ... Decoding means, 50, 60 ... Liquid crystal panel, 100,
200 ... Liquid crystal controller, 101, 201 ... Upper screen display data, 102, 202 ... Lower screen display data, 10
3, 203 ... Data latch signal, 104, 204 ... Line signal, 105, 205 ... Leading line signal, 106, 1
07, 206, 207 ... Data electrode driving circuit, 108,
208, 209 ... Scan electrode driving circuit, 110, 210 ...
Power supply circuit, 111, 211 ... 5V power supply, 112, 212
Data electrode drive circuit power supply voltage 113, 213 Scan electrode drive circuit power supply voltage 114, 214 Scan function data 116, 216 Two line signals 118, 218
Mode signal, 119, 219 ... Data electrode drive circuit enable signal, 120, 121, 220, 221 ... Data electrode voltage, 122, 222, 223 ... Scan electrode voltage, 1
30 ... Enable input signal, 131 ... Enable output signal, 132 ... Timing adjusting circuit, 133 ... Shift clock, 134 ... Two-line shift register UL, 135 ...
Shift register output, 136 ... Data latch, 137 ...
Latch output, 138 ... Operator, 139 ... Operator output, 1
40 ... Output circuit, 141 ... Level shifter, 142 ... Level shifter output, 143 ... Voltage selector, 150, 250
... Half line signals, 151-154 ... Exclusive OR circuit, 155 ... Decoder, 160, 260 ... Scan function generating circuit, 161, 261 ... Clock control circuit, 162, 2
62 ... Clock control output, 163, 263 ... Decoder,
164, 264 ... Decoder output, 165, 265 ... Output circuit, 166, 266 ... Level shifter, 167, 267
... Level shifter output, 168, 268 ... Voltage selector,
169 ... 2 line input signal, 170 ... Scan function input data, 171 ... Master mode signal, 172 ... Frame counter, 173 ... Half line counter, 174 ... Frame count value, 175 ... Half line count value, 1
76 ... 2 line signal, 177 ... Scan function decoder, 17
8 ... Scan function data, 179 ... Selector, 180 ... Latch circuit, 190 ... DC-DC converter, 191-19
6 ... OP amplifier

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor ▲ Hiroyuki Nono 1099, Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Prefecture, Ltd. System Development Laboratory, Hitachi, Ltd. (72) Inventor, Yasuyuki Kudo 1099, Ozen-ji, Aso-ku, Kawasaki, Kanagawa Prefecture Address Incorporated company Hitachi Ltd. System Development Laboratory (72) Inventor Toshio Futami 3300 Hayano, Mobara-shi, Chiba Hitachi Electronic Works, Ltd. Electronic Device Division (72) Inventor Satoru Tsunekawa 5-chome, Kamimizumotocho, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Business Division No. 1

Claims (9)

[Claims] 1. M rows of data electrodes and N scan electrodes are provided, and N rows and M are provided according to an effective value of a difference between a display voltage applied to the data electrodes and a scan voltage applied to the scan electrodes.
A liquid crystal panel for displaying columns, a liquid crystal controller for outputting a synchronizing signal and two kinds of display data for the liquid crystal panel configured by two screens, and a scanning electrode to be scanned among the scanning electrodes according to the synchronizing signal. A liquid crystal display device comprising scan electrode driving means for outputting a selection voltage and data electrode driving means for outputting a display voltage corresponding to the display data to a data electrode according to the synchronization signal, wherein the scan electrode driving means is , An orthogonal function generating circuit for generating m kinds of orthogonal functions, and a selection circuit for simultaneously selecting m / 2 scanning electrodes in each of two scanning electrode groups obtained as a result of dividing the liquid crystal panel into two in the row direction. And applying a selection voltage according to the m orthogonal functions generated by the orthogonal function generation circuit to the m scanning electrodes selected by the selection circuit, and (N-m) scan electrodes are provided with a scan voltage output circuit for applying a voltage for invalidating the scan, and the data electrode driving means inputs corresponding to the scan electrodes selected by the selection circuit. An m line shift register for storing the display data for m rows, and a latch circuit for fetching the display data stored in the m line shift register and holding the display data only while the same scan electrode is selected in the selection circuit, An arithmetic unit for performing an arithmetic operation on the display data held in the latch circuit and the m orthogonal functions generated by the orthogonal function generating circuit, and a display voltage according to the arithmetic result of the arithmetic unit is applied to the data electrode. A liquid crystal display device comprising a display voltage output circuit. 2. M rows of data electrodes and N scan electrodes, N rows, M depending on an effective value of a difference between a display voltage applied to the data electrodes and a scan voltage applied to the scan electrodes.
A liquid crystal panel for displaying columns, a liquid crystal controller for outputting a synchronizing signal and display data, a scan electrode driving means for outputting a selection voltage to a scan electrode to be scanned among the scan electrodes according to the synchronizing signal, and the synchronization A liquid crystal display device comprising: a data electrode driving unit that outputs a display voltage corresponding to the display data to a data electrode according to a signal, wherein the scanning electrode driving unit generates an m-type orthogonal function. A selection circuit for simultaneously selecting m / 2 scan electrodes in each of two scan electrode groups obtained by dividing the liquid crystal panel into two in the row direction; and m scans selected by the selection circuit. A selection voltage according to m orthogonal functions generated by the orthogonal function generating circuit is applied to the electrodes, and scanning is disabled for the remaining (N−m) scanning electrodes. And a scanning voltage output circuit for applying a voltage for driving the data electrode driving means, wherein the data electrode driving means stores m rows of display data corresponding to the scanning electrodes selected by the selection circuit.
A line shift register, a latch circuit that fetches display data of m rows and M columns stored in the m line shift register, and holds the same only while the same scan electrode is selected in the selection circuit, and a latch circuit that holds the latch circuit An arithmetic unit that simultaneously performs an operation on each of the M columns of the displayed display data and the m orthogonal functions generated by the orthogonal function generation circuit, and a display of M columns corresponding to the arithmetic result of the arithmetic unit. A liquid crystal display device comprising a display voltage output circuit for applying a voltage to the data electrodes. 3. The liquid crystal display device according to claim 2, wherein the liquid crystal controller outputs display data corresponding to each of the two sets of scan electrode groups individually and simultaneously. Liquid crystal display device. 4. The liquid crystal display device according to claim 2, wherein a value of “−1” when the display is turned on and “+1” when the display is turned off is i-th column and j-th column (1 ≦ i ≦ N, 1 ≤ j ≤ M), the orthogonal function value corresponding to the i-th row having a value of Iij, "+1" or "-1" is Wi, and the calculation result corresponding to the j-th column is Sj, The computing unit is A liquid crystal display device characterized by performing the following calculation. 5. The liquid crystal display device according to claim 1, wherein the orthogonal function generating circuit is arranged outside a scan electrode driving circuit, and an arbitrary orthogonal function can be set in the orthogonal function generating circuit. A liquid crystal display device characterized by the following. 6. The liquid crystal display device according to claim 1, wherein each of the data electrode driving means and the scan electrode driving means is a one-chip integrated circuit. 7. The liquid crystal display device according to claim 1, wherein the scan electrode driving means is a total of two integrated circuits connected to each set of the two sets of scan electrodes. Characteristic liquid crystal display device. 8. The liquid crystal display device according to claim 1 or 2, wherein m = 4. 9. The liquid crystal display device according to claim 1, wherein a DC voltage converter for converting the level of the input DC voltage and three types of scan electrodes including the ground level from the converted DC voltage. Including voltage and ground level (m
+1) a power supply circuit having a voltage divider that generates data electrode voltages, and the scan voltage output circuit outputs, for each scan electrode, one of the scan electrode voltages except the ground level. The scan voltage is selected as the scan voltage, and the scan electrode voltage at the ground level is selected as the voltage for invalidating the scan, and the display voltage output circuit selects one of the data electrode voltages for each data electrode. Is selected as the display voltage.