JPH09219500A - High density memory structure and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a cell structure which is easily manufactured at a low cost, excellent in reliability, and high in density by a method wherein a field effect transistor is formed adjacent to a recessed region of a semiconductor substrate, and a capacitor is formed covering an insulating layer in the recessed region. SOLUTION: A semiconductor substrate is equipped with a recessed region with a side wall 36 which extends from a base 32, and a field effect transistor 18 equipped with source/drain regions 38 and 46 adjacent to the recessed region is provided to the semiconductor substrate. A lower capacitor plate 26 is provided so as to be connected to the source/drain regions 38 and 46 and located above a part of the field effect transistor 18 covering an insulating layer 24 deposited on the recessed region. Furthermore, a capacitor dielectric piece 30 is provided to cover the lower capacitor plate 26, and an upper capacitor plate 28 is provided to coat the dielectric piece 30. For instance, the upper capacitor plate 28 and/or the lower capacitor plate 26 are formed of a polycrystalline silicon layer which is doped in a forming process.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to the manufacture of semiconductor integrated circuits. Although the present invention has been described with the memory cell structure of a dynamic RAM device as an example, the present invention has a wider range of applicability. For example, the present invention is applied to semiconductor devices such as special application integrated circuits (ASICs), microprocessors (MICROs) and other memory devices.

[0002]

2. Description of the Related Art In manufacturing a dynamic RAM device, there has been a problem to be solved in the storage capacity of a memory cell of each dynamic RAM device. In this dynamic RAM (DRAM) memory cell, the storage capacity refers to the maximum amount of charge that can be stored in the dielectric between the electrode of the lower capacitor and the electrode of the upper capacitor. Since this storage capacity is proportional to the surface area of the capacitor dielectric between these electrodes, the larger the surface area of the capacitor, the larger the storage capacity.

Low density DRAM of 256 kbit DRAM
Is designed as a planar capacitor structure set in a plane of horizontal space substantially the same as the transistor gate. These capacitor structures have a transistor / drain in a finite space region between the transistor gate and the field oxide film. Is configured to cover. Although these planar capacitor structures can provide sufficient storage capacity for these low density DRAM memory cells, as the size of DRAM memory cells shrinks for high density devices, they have sufficient storage capacity within relatively small memory cell sizes. Designing a capacitor structure becomes increasingly difficult.
A multilayer capacitor is used as a technique for increasing the storage capacity of such a high-density DRAM memory cell, but it does not form the capacitor structure on the same plane as the gate of the field effect transistor (FET). By forming above the gate of the field effect transistor,
It increases the surface area of the capacitor. However, this type of capacitor is problematic in the process. In fact, the multilayer capacitor structure causes the DRAM memory cell to have an extremely complicated uneven topography, which requires a high level of technology during manufacturing. Moreover, the processing time is long, the yield is low, and the production cost is high.

Trench capacitors have been proposed as another technique for increasing the storage capacity of high density DRAM memory cells. This is formed by providing a well region of a DRAM memory cell with a recessed region or "trench", and is formed with a width and depth appropriately selected. The trench has a sidewall, which forms a lower capacitor electrode. The conductive filler covering the capacitor dielectric layer forms the upper capacitor electrode. By doing so, the surface area of the capacitor increases, and the storage capacity increases accordingly.

Increasing the surface area of a capacitor is
This leads to making the trench deeper or wider, but the width of the trench cannot be basically increased because the substrate surface area of each memory cell is limited. Therefore, it has been considered to increase the depth of the trench to increase the surface of the capacitor. However, when the trench is deepened, the aspect ratio becomes large, so that the fabrication is often difficult. In addition, when this trench structure is used, a junction area becomes large, which may cause a problem of "soft error". In addition, the sidewalls used as the lower capacitor electrodes may be doped, affecting the quality of the capacitor dielectric layer.

[0006]

As described above, in this field, there is a demand for a high-density cell structure which can be easily manufactured, is low in cost, and has high reliability. It is an object of the present invention to improve a capacitor of a DRAM integrated circuit device satisfying these requirements and to provide a manufacturing method and a structure thereof.

[0007]

A dynamic RAM (DRAM) integrated circuit according to the present invention which achieves the above object comprises a semiconductor substrate having a recessed region having a side wall extending from a bottom surface, and a source adjacent to the recessed region. / Drain region, an insulating layer covering the recessed region, an insulating layer covering the insulating layer, located above a part of the field effect transistor and connected to the source / drain region. A lower capacitor plate, a capacitor dielectric covering the lower capacitor plate, and an upper capacitor plate covering the dielectric.

Further, the DRA of the present invention which achieves the above object
A method of forming a capacitor structure in an M integrated circuit is
A step of preparing a semiconductor substrate; a step of forming a recessed region having a sidewall extending from a bottom surface; a step of providing an insulating layer formed so as to cover the recessed region; Forming a drain region, forming a lower capacitor plate covering the insulating layer and overlying a portion of the field effect transistor and connected to the source / drain regions, and the lower capacitor plate. And a step of forming an upper capacitor plate that covers the dielectric.

The DRA of the present invention which achieves the above object
A bitline structure in an M integrated circuit covers a semiconductor substrate having a recessed region having sidewalls extending from a bottom surface, a field effect transistor having source / drain regions adjacent to the recessed region, and the recessed region. An insulating layer and a conductor formed in the recessed region and connected to the source / drain regions are provided.

Further, a method of forming a bit line in a DRAM integrated circuit which achieves the above-mentioned object includes a step of preparing a semiconductor substrate and a step of forming a recessed region having a side wall extending from a bottom surface in the semiconductor substrate. A step of providing an insulating layer in a range covering the recessed region, a step of forming a field effect transistor having a source / drain region adjacent to the recessed region, and a conductor connected to the source / drain region. Forming in the recessed region.

[0011]

According to the device of the present invention, the upper and lower capacitor plates are both polycrystalline silicon layers doped with an N-type dopant during the formation process, and are striped or rough-polished polycrystalline silicon layers. Since it is produced as
Unlike the smooth polycrystalline silicon layer, small protrusions are formed, which increases the effective area of the capacitor.
Further, according to the present device, the structure of the trench capacitor is configured to extend from the bottom of the trench along the sidewall to reach above the field effect transistor, so that a trench capacitor structure that is substantially longer than the conventional capacitor structure is obtained. be able to. As described above, the trench capacitor designed according to the technical concept of the present invention can increase the number of capacitors and can eliminate the drawback that the conventional trench capacitor structure cannot be manufactured to a certain depth or more.

According to the process of claim 10 of the present application, an improved capacitor having a shallow trench and a laminated capacitor plate is provided, each capacitor plate being above the gate electrode of the field effect transistor in the trench. Since it is formed, the surface area of the capacitor is increased, and the storage capacity is increased accordingly. Further, according to this method, a bit line structure formed in the trench is provided, and the bit line can be connected to each source / drain region with a simpler structure without using a conventional structure.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

I. Dynamic RAM (DRAM) device
Structure FIG. 1 of a simplified cross-sectional view of the DRAM integrated circuit device 10 of the present invention. Generally, the DRAM device 10 includes a plurality of memory cell regions 12, a covering dielectric layer 14, a top metallization layer 16, a protective film 17 and other elements. These memory cell regions are manufactured by a conventional CMOS processing technique or the like.

Each memory region 12 is formed in a P-type well region 22, and the field effect transistor 18 is also formed in this P-type well 22. The field effect transistor 18 is an N-channel MOS (NMOS), and has a gate electrode 54 (also referred to as a word line) that covers the thin film gate dielectric layer 52. The sidewall 56 is formed adjacent to the gate electrode 54, and the cap oxide layer 58 is coated on the gate electrode 54. The interlayer dielectric 60 is formed to cover the cap oxide layer and a portion of the source / drain regions 38,46. An N-type LDD region 4 is formed in each source / drain region.
2, 48 and N + type source / drain regions 40, 50 are formed. The N + type source / drain region 40 is connected to the trench capacitor 20 and is formed in the P type well region.

The trench capacitor 20 is used as a memory device by accumulating charges in a capacitor dielectric 30 located between a lower capacitor plate 26 and an upper capacitor plate 28. The capacitor dielectric is formed of a suitable insulating material such as silicon dioxide, silicon nitride, or the like.
Also, a silicon dioxide-silicon nitride-silicon dioxide sandwich layer is preferably used for the capacitor dielectric. This is an ONO that has been used conventionally
Although it is an (oxide-nitride-oxide) layer, it is of course possible to use other combinations of dielectric materials.

The lower capacitor plate 26 is formed above the field effect transistor 18 and covers the insulating layer 24, the trench bottom 32 and the side wall 34. The thickness of this insulating layer is sufficient to insulate the P-type well region from the lower capacitor plate 26. Also,
If a high quality silicon dioxide material is used for this insulating layer, a suitable insulating effect can be obtained. In order to improve the electrical contact between the lower capacitor plate 26 and the N + type source / drain regions 40, the insulating layer is formed on the trench side wall 3.
It has been removed in the upper part 36 of 4.

The lower capacitor plate may be an appropriate conductor layer, and preferably a polycrystalline silicon layer doped with an N-type dopant (such as phosphorus) during the formation process is used. Further, the lower capacitor plate may be formed as a multi-metal layer, a silicide layer, and a layer having a sandwich structure in which these layers are combined. Also, in other embodiments, the lower capacitor plate is fabricated as a striped or rough-cut polycrystalline silicon layer. Unlike the smooth polycrystalline silicon layer, the striped polycrystalline silicon layer has small protrusions, which increases the effective area of the capacitor. The lower capacitor plate 26 extends upwardly from the insulating layer at the bottom 32 of the trench to cover the sidewalls 34 of the trench while at the same time contacting the source / drain regions 40, as shown in the figure, and further to the intermediate dielectric 60. Of the field effect transistor to cover the field effect transistor.

The upper capacitor plate 28 is formed to cover the capacitor dielectric 30 and extends from the bottom 32 of the trench insulating layer to cover the capacitor dielectric layer 30 of the lower capacitor 26. The upper capacitor plate 28 is also preferably a polycrystalline silicon layer doped with an N-type dopant during the formation process. The upper capacitor plate 28 may be formed as a multi-metal layer, a silicide layer, or a layer having a sandwich structure in which these layers are combined. In another embodiment, the upper capacitor plate 2
8 is produced as a striped or rough-cut polycrystalline silicon layer. Unlike the smooth polycrystalline silicon layer, the striped polycrystalline silicon layer has small protrusions formed,
Therefore, the effective area of the capacitor is increasing.

As shown in the figure, the lower capacitor 2
6, the capacitor dielectric 30 and the upper capacitor plate 28 extend along the sidewall 34 from the trench bottom and the field effect transistor 1
Since it is formed so as to reach the upper side of 8, it is possible to obtain a trench capacitor structure which is substantially longer than the conventional capacitor structure.

As described above, the trench capacitor designed according to the technical concept of the present invention can increase the number of capacitors and eliminate the problem that the conventional trench capacitor structure cannot be manufactured to a certain depth or more. You can For example, using the 0.25 μm design rule, the trench depth can range from about 8,000 Å to about 12,000 Å, preferably about 10,000 Å. The width of the trench is about 2,500 Å for the bit line and insulation area and about 4,000 Å for the capacitor.
The degree is preferred. Although this trench structure is provided with the lower capacitor plate as described above, the thickness of this capacitor plate can range from about 1,000Å to about 1,400Å, preferably about 1,200Å. As described above, a part of the lower capacitor is formed so as to cover the field effect transistor and the trench sidewall.

FIG. 2 is a simplified diagram of the bit line structure of the DRAM in the first embodiment. The cut-out portion 200 includes the P-type well region 22 and the gate electrode 54 (or word line). Bit line 204 is formed in trench 201 having sidewalls and a bottom. The periphery of the trench is covered with an insulating layer including a bottom insulating layer portion 203 and a sidewall insulating layer portion 202. This insulating layer serves to isolate the P-type well region 22 from the bit line formed perpendicular to the word line 54. The bit line serves as a connection to the source / drain region of each transistor adjacent thereto.

The bit line 204 is a sidewall insulating layer 2
02 through the contact opening 207 of the field effect transistor 1
8 source / drain regions 46. A portion of the sidewall insulating layer 202 is removed before the bit line 204 is formed, and the source / drain region 46 and the bit line 20 are removed.
A contact opening for contacting with 4 is formed. According to the 0.25 μm design rule, the width of this contact opening is about 2,000 Å to about 2,
The range is 800 Å, preferably about 2,200 Å.
The depth of this contact opening is about 2,200 Å to about 2,800.
The range is Å, preferably about 2,500 Å.

The bit line 204 is made of a conductive material, and the bit line is preferably a polycrystalline silicon layer doped with an N-type dopant during the formation process. The bit line 204 may be manufactured by depositing a polycrystalline silicon layer and doping it by diffusion of POCl ₃ , or by implanting ions by annealing. In addition to the bit line thickness, the trench depth is approximately 1,000 Å top insulation and approximately 500 Å
It is the one with the bottom insulation part added. The bit lines may also be made of other materials of different sizes, such as polycide or a combination of various materials.

A top insulating layer 205 is formed on the bit line 204. This top insulating layer portion 20
Reference numeral 5 insulates the bit line from the gate electrode and other device elements thereon. This top insulating layer portion 20
5, the insulating layer including the side insulating layer portion 202 and the bottom insulating layer portion 203 is formed so as to surround the bit line 204, and isolates the bit line from the surrounding P-type well region and other elements. As shown, the top insulating portion 205 is connected to the side wall insulating portion 202, and the side wall insulating layer portion 202 is connected to the bottom insulating layer portion 203.

FIG. 3 is a sectional view of the bit line structure in FIG. The cut-out portion 300 shows that the bit line 204 is connected to the source / drain region 46 through the contact opening 207. In FIG. 3, by forming this contact opening 207, the bit line 204 can be connected to the N + type source / drain region 50. Since the resistance of the N + type source / drain region 50 is lower than that of the adjacent N− type LDD region, the charge representing a signal can be easily transferred from the source / drain region 46 of the memory cell to the bit line 204. . The connection between the bit line 204 and the source / drain region 46 is made through the N + type source / drain region 50.

The top insulating layer portion 205 and the side wall insulating layer portion 202A adjacent to the contact opening 207 are respectively connected to the side wall insulating layer portion 202 and the bottom insulating layer portion 203.
It is connected to the. The combination of these insulating layer portions isolates the bit line 204 from the adjacent device element and connects the bit line 204 to the source / drain region 46. Each DRAM memory cell is formed using this type of bit line connection system.

FIG. 4 is a simplified plan view of the DRAM integrated circuit structure of the present invention. In the matrix in the X and Y directions of this plan view 400, the gate electrode 54 extends in the X direction and P
It is formed so as to cover the mold well region 22. Y
Each lower capacitor electrode 26 formed in the direction is formed above the gate electrode 54. Multiple bit lines 20
Reference numeral 4 extends along the electrode below the gate electrode 54 in the Y direction and is orthogonal to the gate electrode 54. Each bit line 204 has a contact opening 207 for connecting the bit line to the source / drain region 46 of each field effect transistor.

II. Production of dynamic RAM (DRAM)
Manufacturing Technology All steps of the manufacturing method of the present invention are listed below.

(1) Preparing a semiconductor substrate; (2) Photomask 1: forming a P-type well in the semiconductor substrate; (3) photomask 2: forming an N-type well in the semiconductor substrate; (4) forming a protective layer including a pad oxide layer and a silicon nitride layer; (5) photomask 3: forming an active region to form a trench region; (6) forming a trench region; (7) ) Form trench sidewalls and bottom oxide layer; (8) Photomask 4: form bitline contact,
Removing the photoresist; (9) depositing doped polycrystalline silicon during the forming process to fill the trench region; (10) etching back the doped polycrystalline silicon during the forming process into the trench. (11) Photomask 5: forming a non-bitline trench region and removing polycrystalline silicon doped in the formation process in the non-bitline trench region; (12) during formation process in the bitline trench region (13) photomask 6: mask the P-type channel region and implant the channel stop region to the bottom of the trench; (14) deposit borophosphosilicate (BPSG). Filling the trench region in the non-bitline trench region; (16) Complete critical implant is performed; (17) Photomask 7: N-type well region is masked,
The critical voltage (threshold voltage) is adjusted by using P-type dopant as an implant in the memory cell region (or P-type well region).

(18) Form Gate Oxide Layer; (19) Form Doped Gate Polysilicon or Polycide (or poly-1); (20) Photomask 8: Form Gate Polysilicon Layer Forming a gate electrode; (21) photomask 9: forming an N-type lightly doped drain (LDD) region and implanting an N-type dopant; (22) photomask 10: forming a P-type LDD region,
(23) Form sidewall spacers on the sides of the polycrystalline silicon gate; (24) Photomask 11: form N + type source / drain regions and implant N + type dopants; 25) Photomask 12: P + type source / drain regions are formed and P + type dopant is implanted; (26) Photomask 13: Bit line region and word line region are covered with photoresist to form capacitor regions; (27) The BPSG in the trench capacitor region is removed and the photoresist is removed.

(28) depositing an intermediate polycrystalline silicon oxide layer; (29) photomask 14: forming and etching the contact region of the capacitor unit; (30) depositing and doping a poly-2 layer; (31) Photomask 15: forming a capacitor electrode (lower capacitor plate) having a poly-2 layer formed thereon; (32) forming a memory cell capacitor dielectric; (33) depositing poly-3 Doping (or depositing doped poly-3 during the formation process).

(34) Photomask 16: poly-3
Forming a layer to form an upper capacitor electrode (upper capacitor plate); (35) depositing and plasticizing BPSG / NSG (undoped silicate glass); (36) photomask 17: contacts in the BPSG / NSG layer Forming a pattern; (37) sputtering a first metal layer; (38) photomask 18: forming a first metal layer; (39) depositing an intermediate metal oxide; (40) photomask 19: Forming a via pattern; (41) sputtering a second metal layer; (42) photomask 20: forming a second metal layer; (43) depositing a protective film and a polyimide coating; 44) Photomask 21: forming a pad region and a fuse region; (45) curing pariimide; (46) coating a protective film And quenching to form a pad region; (47) sintered.

These steps provide an improved capacitor with a shallow trench and a laminated capacitor plate, each capacitor plate being formed in the trench above the gate electrode of the field effect transistor. Therefore, the surface area of the capacitor can be increased,
Along with this, the storage capacity increases. The present invention also provides a bit line structure formed in the trench, which bit line structure connects each source / drain region with a simpler structure without using the complicated structure of the prior art. I am trying to do it. The method of the present invention will be described below with reference to the accompanying drawings.

5 to 14 show a DRAM according to the present invention.
FIG. 9 is a simplified diagram illustrating the method of manufacturing the integrated circuit device. FIG.
The method of the present invention begins with providing a semiconductor substrate 11, as shown in FIG. As the substrate 11, various wafers suitable for manufacturing the integrated circuit device according to the present invention can be used. As an example, this wafer uses CMOS fabrication technology for DRAM storage. However, it is also possible to appropriately use other manufacturing methods depending on the object.

The photoresist mask is formed so as to cover the upper surface of the semiconductor substrate 11 and form the P-type well region 22. The P-type well region 22 is formed by implanting a dopant (such as phosphorus) containing a P-type material into the substrate 11. The photoresist mask is removed using conventional techniques. Then, an N-type channel device is formed in the P-type well region.

The N-type well may be formed in the semiconductor substrate 11. In this case, the photoresist mask is formed so as to cover the P-type region of the semiconductor substrate 11. An N-type well region is formed in the semiconductor substrate 11 by the implant step. The P-channel device is then formed in the N-well region after the photoresist mask has been removed using conventional techniques.

As shown in FIG. 5, a dielectric layer 501 is formed to cover the substrate 11 to form a protective layer. That is, this protective layer is used as a photomask layer.

This protective layer 501 is a pad oxide layer 503.
And a silicon nitride layer 505 covering the same.
The pad oxide layer 503 has a thickness of 200Å to 300Å, and the silicon nitride layer 505 has a thickness of 1200Å to 1800.
Has a thickness of Å. The silicon nitride layer 505 may optionally include a silicon dioxide layer (not shown) overlying it. These layers are formed in a plurality of trench regions, such as capacitor trench 20 and bit line trench 201, as shown in FIG.

The capacitor trench 20 and the bit line trench 201 are formed by reactive ion etching,
It is performed by plasma etching or the like. Compared to conventional capacitor trenches, the trenches of this method are shallower and thus easier to fabricate. Using the 0.25 μm design rule, the depth of the capacitor trench is about 0.8 μm.
To about 1.2 μm, and preferably about 1.0 μm. The trenches simultaneously have a width of 0.4 μm. If the same design rule is used, the depth of the bit line trench corresponds to the depth of the capacitor trench and is about 0.8 μm to about 1.2 μm, preferably about 1.0 μm. The trenches simultaneously have a width of about 0.25 μm. Of course, the depth and width of each trench are determined according to its purpose.

As shown in FIG. 7, the dielectric isolator layer comprises a capacitor trench 20 and a bit line trench 2.
01 trench. Capacitor trench 2
0 comprises a dielectric layer 24 covering the trench bottom 32 and trench sidewalls 34. On the other hand, the bit line trenches 201 each have a dielectric layer 203 that covers the sidewalls and bottom of the trenches. Although these trenches are more advantageously coated with an oxide layer, preferably by thermal oxidation of silicon, the oxide layer should be thick enough to isolate the coating structure from the substrate 11 and other device elements. is required. This thickness is about 400Å to about 600Å, preferably about 500Å. The trench is CV
The oxide layer or multiple dielectric layers may be deposited and formed by D or other suitable technique. Of course, the dielectric layer material and its thickness are determined according to its purpose.

The bit line contacts in the dielectric layer of these bit line trenches 201 are formed by photomasking and etching, and are formed as contact openings 207 in the dielectric layer that cover the sidewalls of the trenches. The contact opening 207 is formed by coating the upper surface of the substrate including the trench with photoresist. After coating, patterning the photoresist,
An exposed area is formed covering the contact opening and the exposed area is wet etched to form a bit line contact opening. Each contact opening has a width of 0.25 μm and a depth of about 3000Å.

Then, the photoresist is removed by a conventional technique. During later steps, this contact opening 207
Provides a via structure for connecting the bit line to the source / drain region of each field effect transistor.

Next, the trench is filled with a polycrystalline silicon filling layer 801 which is doped during the formation process (see FIG. 8). And heavily doping the doped polycrystalline silicon layer during this formation process,
It should have a constant conductivity. This doping may include, for example, a concentration of about 2 × 10 ^{20 to} about 6 × 10 ²⁰ atoms /
A cm ³ and preferably about 4 × 10 ²⁰ atoms / cm ³ phosphorus N-type dopant is used. This bit line trench 2
In 01, doped polycrystalline silicon layer 80
1 fills the contact openings and covers the substrate surface forming the source / drain regions of the field effect transistor.

Then, the upper portion of the polycrystalline silicon layer doped during the forming process is removed by etching, and a part of the polycrystalline silicon layer in the trench doped during the forming process is also removed. The top surface of this polycrystalline silicon is preferably about 1000Å away from the top surface of the silicon substrate. The etching referred to here includes plasma etching, reactive ion etching and the like.

The doped polycrystalline silicon is removed from the non-bitline trench regions during the formation process. That is, the doped polycrystalline silicon during the formation process is removed from the capacitor trench instead of the bit line trench. The doped polycrystalline silicon is coated with photoresist on the top surface of the substrate to expose and remove the areas covered by the capacitor trenches. Then, the doped polycrystalline silicon is removed from the inside of the capacitor trench by etching.

When the doped polycrystalline silicon is removed during the formation process, each capacitor trench is empty except for the insulating layer. The capacitor trench is filled with a filling material. The filler should have good masking properties and be capable of being selectively removed in later treatment steps. In this embodiment, BPSG 901 is used to fill the trenches, as shown in FIG. Of course, other applicable materials can be used.

During the process of forming the bit line trench, the upper portion 205 of the doped polycrystalline silicon is exposed to an oxidizing agent such as oxygen or water at a high temperature to be oxidized. Then, the heat treatment of the doped layer converts the polycrystalline silicon into a silicon oxide layer having an insulating property. The silicon dioxide should be thick enough to isolate the bit line from the device above it,
Its thickness is about 400Å to about 600Å, preferably about 50
0 °. Of course, it is also possible to form the silicon dioxide layer using other techniques (for example CVD).

Then, a channel stop region is formed in the substrate. In one embodiment, it can be formed by masking the P-type channel region and implanting the channel stop region. Desirably, the implant in the channel stop region is made of N, such as phosphorus.
Implant to the depth of the bottom of the trench using a type dopant.

Next, the protective layer made of silicon oxide, silicon nitride or the like is removed from the active region. The silicon nitride layer is removed by dry or wet etching (eg phosphoric acid etc.) and the silicon oxide coating on the substrate must be selectively removed so as not to damage the substrate. In the present embodiment, a hydrofluoric acid solution is used to selectively remove silicon dioxide. Of course,
Other applicable techniques can also be used.

N-type channel M typifying the CMOS process
OS (NMOS) device and P-type channel MOS (P
MOS) devices are formed in the P-type well region and the N-type well region, respectively. The DRAM memory cell is formed in the P-type well region. These devices are formed by the following steps.

For all surfaces of the substrate 11,
hold) Implant. That is, the N-type dopant containing phosphorus, As, etc. is entirely and simultaneously coated on the P-type and N-type well regions.

A photoresist mask is overlaid on the N-type well region and a P-type dopant of, for example, boron is implanted. The P-type dopant is implanted to set the threshold voltage of the N-type channel device in each memory cell, which implant is determined by the thickness of the gate oxide layer. In addition, P before the N-type dopant
The type dopant may be implanted first.

As seen in FIG. 10, a gate oxide layer 52 is formed so as to cover the top surface of the P-type well region 22. The gate oxide layer 52 is a high quality oxide and its thickness is sufficiently thin to improve the switching characteristics of the device. The thickness of this type of gate oxide layer is typically about 90Å to about 110Å,
It is preferably about 100Å. A deposition step forms a polycrystalline silicon layer overlying the oxide layer. This polycrystalline silicon layer or polycide (W on polycrystalline silicon
Si _x ) is about 2500Å to about 3500Å, preferably about 300Å. The polycrystalline silicon layer usually has a concentration of about 4 × 10 ^{20 to} about 6 × 10 ²⁰ atoms / cm 3.
Doped with ³ (preferably about 5 × 10 ²⁰ atoms / cm ³ ) N-type dopant. An implant and anneal step is performed to add an N-type dopant into the polycrystalline silicon and simultaneously diffuse or form the N-type dopant when the polycrystalline silicon layer is formed to reduce processing steps. Be seen. In the polycide gate embodiment, the comparatively thin polycrystalline silicon of about 1500 Å is doped, and the WSi of about 1000 Å is further added.
deposit _x .

The polycrystalline silicon layer or polycide is
Patterning is performed to form a polycrystalline silicon gate 54 as shown in FIG. These gate electrodes called word lines are usually formed by a series of photolithography (photomask, developing, etching) steps.
Each gate electrode has a substantially vertical side, but may exhibit a non-vertical side. The exact geometry of each gate electrode is determined by its applicability.

In the entire implant step, N-type dopant is introduced into a part of the well by using each gate electrode as a photomask, and the N-type LDD in the P-type well region 22 is formed.
42 and 48 are formed. The content range of this N-type dopant is about 1 × 10 ¹³ atoms / cm ² to about 5 × 10 ¹³ atoms / c.
It is between m ² and about 3 × 10 ¹³ atoms / cm ² is preferable. The angle range for implanting is an angle greater than 0 degrees (preferably about 30 degrees) from a line orthogonal to the channel direction.
Degree) to about 45 degrees. Also, the N-type well region may be masked and N-type dopant may be implanted into the P-type well region to form the N-type LDD region. These steps form the N-type LDD region of the memory cell.

Next, the P-type well region is masked and a P-type dopant is introduced into the N-type well region to form a P-type LDD region in the N-type well region. This P-type LD
About 1 × 10 ^{13 to} about 5 × 10 ¹³ atoms / cm ^{2 in the} D region
And the content of about 2 × 10 ¹³ atoms / cm ² is preferable. The implant in the P-type LDD region is also performed at an appropriate angle.

Sidewall spacers 56 are formed on the sides of each polycrystalline silicon gate 54. These side wall spacers 5
6 is usually formed by depositing a layer of dielectric material to densify the layer and removing the horizontal surface of the layer. This layer is made of a material such as silicon dioxide, silicon nitride or a combination thereof. The purpose of densifying the dielectric material layer is to seal the polycrystalline silicon gate and isolate it from the layers above it (eg, dielectric material such as silicon dioxide, silicon nitride, combinations thereof). By anisotropic etching performed on this densified dielectric layer,
The horizontal surface of this layer that formed the sidewall spacers is removed. This anisotropic etching includes, for example, reactive ion etching and plasma etching. In this way, the horizontal surface of the dielectric material is removed, leaving the sidewall spacers.

The source / drain regions of each MOS device are formed by masking and implanting.
Specifically, a photoresist mask is used to protect the regions of the P-type channel device and expose the source / drain regions to form the N-type channel device. Then, N + type dopant is implanted into this exposed region to form N + type dopants 40 and 50. The content range of the N + type dopant is between 3 × 10 ¹⁵ atoms / cm ^{2 and} about 5 × 10 ¹⁵ atoms / cm ^2, of which about 4 × 10 ¹⁵ atoms / cm ^2.
cm ² is preferred. The angle range for implanting is between about 0 degrees and about 7 degrees from a line orthogonal to the channel direction, with about 0 degrees being preferred. This photoresist mask is removed by conventional techniques.

Next, another photoresist mask is used to protect the N-type channel device and expose these source / drain regions to form a P-type channel device. Then, a P-type dopant is introduced into the source / drain regions of the P-type channel device. This P + type dopant content range is between about 3 × 10 ^{15 and} about 5 × 10 ¹⁵ atoms / cm ² , with about 4 × 10 ¹⁵ atoms / cm ² being preferred. The photoresist mask is then removed using conventional techniques.

Then, a photomask is placed on the top surface of the substrate to form an opening above the trench capacitor region. That is, the photoresist mask covers the bit lines and the word lines. Then, the BPSG 901 is removed from the trench capacitor region. In this embodiment, BP is selectively etched from the trench by wet etching with hydrofluoric acid.
SG is removed, leaving an insulating region. Alternatively, the BPSG layer may be selectively removed from the trench by dry etching. The photoresist mask is then removed using conventional techniques.

Further, as shown in FIG. 11, first, C
Interlayer dielectric 60 covering gate electrode by VD method
To form The interlayer dielectric 60 may include a compatible material such as TEOS. The intermediate dielectric, such as silicon dioxide, can be deposited using techniques such as APCVD, PECVD, LPCVD, but its adaptability determines the technique used.

Next, a photoresist mask is put on the substrate top surface region where the trench capacitor is formed to form an exposed region covering the memory cell contact region. Then, as shown in FIG. 11, a memory cell contact region or opening in these isolation regions is formed by an etching technique such as plasma etching or reactive ion etching. Note that, for example, a wet etching technique using hydrofluoric acid as a selective etching material can be used. In the figure, each opening serves to connect the lower capacitor electrode to the source / drain region of the field effect transistor. This opening is approximately 2000 Å from the surface of the substrate.
It is provided on the lower side. The top of this exposed source / drain region is essentially free of oxidation until the next step. Then, the source / drain regions are cleaned by dilute acid dip or dry etching.

Next, a lower capacitor electrode layer 26 covering the exposed portions of the isolation region and the source / drain regions is deposited. The lower capacitor electrode layer 26 is further provided on the top 1201 of the intermediate dielectric 60 to further increase the surface area of the capacitor storage cell. The lower capacitor layer is preferably formed of polycrystalline silicon that is heavily doped with a dopant to reduce resistance. The introduction of this dopant is accomplished by selecting a multi-angle implant depending on its applicability or by doping during the formation process. In this embodiment, these dopants are N-type dopants such as phosphorus.

A lower capacitor layer is formed on the lower capacitor electrode plate 26 through masking and etching steps (see FIG. 12). The lower capacitor electrode plate 26 is connected to the source / drain regions 38 of the field effect transistor via the contact openings 36. The photoresist is then removed using conventional techniques. The lower capacitor layer is cleaned by dry etching before the coating dielectric is manufactured.

Next, a capacitor dielectric layer 30 for storing charges is formed between the lower capacitor plate and the upper capacitor plate to cover the lower capacitor plate 26. In this embodiment, a high quality nitride / oxide composite layer is used as the capacitor dielectric layer. And in a preferred embodiment, the capacitor dielectric layer comprises a silicon dioxide layer overlying the lower capacitor plate, a silicon nitride layer overlying the silicon dioxide layer, and a silicon dioxide layer overlying the nitride layer. . This composite layer provides high storage capacity and is easy to manufacture.

After completion of this capacitor structure, an upper capacitor layer is deposited to cover the capacitor dielectric layer. The upper capacitor layer is a polycrystalline silicon layer heavily doped to reduce the resistance. This polycrystalline silicon layer is formed by selecting a multi-angle implant according to its applicability or by doping during formation. The capacitor layer is formed on the upper capacitor plate by a masking and etching step (see FIG. 13). As shown in FIG. 13, the lower capacitor plate 26, the capacitor dielectric layer 30, and the upper capacitor plate 28 form a capacitor structure. Some capacitors are located on the field effect transistor 18 and the trench to increase the capacitor surface area, thereby providing a relatively large capacitance.

A BPSG / NSG composite layer 14 is then deposited by typical CVD techniques to cover the entire substrate 14. As a result, the BPSG / NSG composite layer 14
Isolates the lower device structure from the upper metallization. Then, by the annealing step, the BPSG / N
The SG layers are plasticized and the surfaces of these layers are masked to define the contact openings. Then, after forming a contact opening by an etching method, the photomask is removed by a conventional technique.

Next, a first metal layer is formed so as to cover these layers 14 and is formed in the contact openings so that they can be electrically connected. Then, the masking and etching steps pattern the first metal layer 16 as shown in FIG. Then, an intermediate metal layer 17 is deposited by a typical CVD technique to cover the patterned first metal layer 16. Next, using a conventional masking and etching technique, a via pattern having an opening for electrically connecting the first metal layer 16 and the second metal layer is formed into the intermediate metal oxide. It is defined in the object 17. The second metal layer is then metallized to cover the intermediate metal oxide and metallize these passages. The patterning step now defines the second metal layer.

As a remaining manufacturing step, an inactive layer consisting of a silicon nitride-containing layer and a silicon dioxide layer is deposited. The inactive layer is patterned to form bond pad area openings and fuse openings. After etching and treating these openings, the entire surface is coated with polyimide. Finally, the coated surface is patterned again by a masking and etching step. After patterning, the wafer is arranged, assembled and tested.

The above description is of the specific embodiment, but within the scope of the technical idea of the present invention,
It goes without saying that various changes are possible. For example, the present invention can be realized by using SRAM.

[Brief description of drawings]

FIG. 1 is a sectional view of a DRAM integrated circuit device according to the present invention.

2 is a perspective view of the DRAM bit line structure in FIG. 1. FIG.

FIG. 3 is another cross-sectional view of the bit line structure in FIG.

FIG. 4 is a plan view of the DRAM shown in FIG.

FIG. 5 is a drawing for explaining the manufacturing method of the DRAM integrated circuit device according to the present invention.

FIG. 6 is a diagram illustrating a method for manufacturing a DRAM integrated circuit device according to the present invention.

FIG. 7 is a drawing for explaining the manufacturing method of the DRAM integrated circuit device according to the present invention.

FIG. 8 is a drawing for explaining the manufacturing method of the DRAM integrated circuit device according to the present invention.

FIG. 9 is a drawing for explaining the manufacturing method of the DRAM integrated circuit device according to the present invention.

FIG. 10 is a drawing for explaining the manufacturing method of the DRAM integrated circuit device according to the present invention.

FIG. 11 is a drawing for explaining the manufacturing method of the DRAM integrated circuit device according to the present invention.

FIG. 12 is a drawing for explaining the manufacturing method of the DRAM integrated circuit device according to the present invention.

FIG. 13 is a drawing for explaining the manufacturing method of the DRAM integrated circuit device according to the present invention.

FIG. 14 is a drawing for explaining the manufacturing method of the DRAM integrated circuit device according to the present invention.

[Explanation of symbols]

 10 DRAM Integrated Circuit Device 12 Memory Cell Region 14 Covering Dielectric Layer 18 Field Effect Transistor 20 Trench Capacitor 22 P-type Well Region 26 Lower Capacitor Plate 28 Upper Capacitor Plate 54 Gate Electrode

Claims (9)

[Claims] 1. A semiconductor substrate having a recessed region having sidewalls extending from a bottom surface, a field effect transistor having source / drain regions adjacent to the recessed region, and an insulating layer covering the recessed region. A lower capacitor plate which covers the insulating layer and is located above a part of the field effect transistor and which is connected to the source / drain regions; a capacitor dielectric which covers the lower capacitor plate; A memory device comprising: an upper capacitor plate that covers the. 2. The recessed area is from 8000Å to 120.
The storage device according to claim 1, wherein the storage device has a depth of 00Å. 3. The lower capacitor plate is 1000 liters to 1
The storage device according to claim 1, wherein the storage device has a thickness of 400Å. 4. The memory device according to claim 1, wherein the upper capacitor plate and / or the lower capacitor plate is a polycrystalline silicon layer doped during a forming process. 5. The capacitor dielectric comprises an oxide layer or an oxide layer and a nitride layer.
A storage device as described. 6. The memory device according to claim 1, wherein the field effect transistor is a MOS transistor. 7. A step of preparing a semiconductor substrate, a step of forming a recessed region having a sidewall extending from a bottom surface, a step of providing an insulating layer formed so as to cover the recessed region, and the recessed region. Forming a source / drain region adjacent to the source / drain region, and forming a lower capacitor plate that covers the insulating layer and is located above a portion of the field effect transistor and is connected to the source / drain region. A method of forming a capacitor structure for a memory device, comprising: forming a capacitor dielectric covering the lower capacitor plate; and forming an upper capacitor plate covering the dielectric. 8. A semiconductor substrate having a recessed region having a side wall extending from a bottom surface, a field effect transistor having a source / drain region adjacent to the recessed region, and an insulating layer covering the recessed region. Dynamic R comprising a conductor formed in the recessed region and connected to the source / drain region
Bit line structure in an AM integrated circuit. 9. A step of preparing a semiconductor substrate, a step of forming an indented region in the semiconductor substrate having a sidewall extending from a bottom surface, and a step of providing an insulating layer in a range covering the indented region, Dynamic R comprising forming a field effect transistor having a source / drain region adjacent to the recessed region, and forming a conductor connected to the source / drain region in the recessed region.
Method of forming a bit line in an AM integrated circuit device.