JPH09214300A - Programmable set reset flip-flop - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the programmable set reset flip-flop with a small occupied area, low power consumption and operated at a high speed. SOLUTION: Inverters 21, 22 form a flip-flop 20. Signals A, B (Cx, Dx) are reset (set) signals of the flip-flop 20. The signals A, B (Cx, Dx) in pairs are switched by a switching signal (d) and when the signal (d) is logical 0, the former signal pair and when logical 1, the latter signal pair is valid. When the signal A(B) is logical 1, transistor (TR) 31(28) is conductive to reset the flip-flop 20 and an output signal (q) goes to 0. On the other hand, when the signal Cx (Dx) is logical 1, transistor (TR) 25 (27) is conductive to set the flip- flop 20 and an output signal (q) goes to 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable set / reset flip-flop capable of externally controlling a set / reset operation of a flip-flop.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram of a programmable set / reset flip-flop 10 according to the prior art. In the figure, reference numerals 11 to 12 are 3-input NANs.
D gate, 13 to 16 are 2-input NAND gates, 17
Is an inverter. Of these, NAND gate 1
Reference numerals 1 and 12 form a set / reset type flip-flop 18. Further, d is a switching signal for the programmable set / reset flip-flop 10, q is an output signal of the programmable set / reset flip-flop 10, and signals A to D are flip-flops 1.
8 is a signal for controlling the set / reset operation of No. 8.

On the other hand, FIG. 3 is a truth table showing the circuit operation of FIG. As can be seen from FIG. 3, in the programmable set / reset flip-flop 10, either the signal A and the signal C or the signal B and the signal D is selected according to the value of the switching signal d, and the selection is performed. The generated signal pair controls the flip-flop 18. That is, if the switching signal d is "0", the signals A and C are selected, and if the switching signal d is "1", the signals B and D are selected.

The signal A and the signal B, or the signal C and the signal D have the same meaning. That is, the signal A (B) is a reset signal for resetting the flip-flop 18, and when this signal becomes "1", the output signal q becomes "0". On the other hand, the signal C (D) is a set signal for setting the flip-flop 18,
When this signal becomes "1", the output signal q becomes "1".
If both the signal A (B) and the signal C (D) are "0", the content of the flip-flop 18 is not changed, and the value of the output signal q retains the previous value. As is well known, a combination in which both the signal A (B) and the signal C (D) are set to "1" is not normally used because the operation of the flip-flop 18 thereafter may be undefined.

[0005]

By the way, the circuit shown in FIG. 2 is replaced with a CMOS (Complementary Metal Oxide Semic).
On the other hand, if it is attempted to realize it with an on-ductor gate, 30 transistors are required according to the conventional general technology. That is, since a 2-input NAND gate is converted into 4 transistors, a 3-input NAND gate is converted into 6 transistors, and an inverter is converted into 2 transistors, 6 × 2 + 4 × 4 + 2 =
Calculated as 30 transistors.

As described above, according to the conventional general implementation, since the number of transistors required is large,
There is a drawback in that the occupied area on the chip increases and the power consumption increases. In addition, the switching signal d or the signals A to D
There is also a problem in terms of speed, since a delay time of 2 to 4 gates is generated from the output stage to the output stage. The present invention has been made in view of the above points, and an object thereof is a small occupied area and low power consumption,
It is to realize a programmable set-reset flip-flop capable of high-speed operation.

[0007]

In order to solve the above-mentioned problems, the invention according to claim 1 is one of the first to nth set / reset signal pairs based on the switching signal. And a programmable set-reset flip-flop for controlling the set-reset operation of the flip-flop according to the selected set / reset signal pair, the first inverter and an open drain type second
Of the first to n-th selection signals based on the switching signal, and a flip-flop configured by connecting the inverters in a loop shape so as to take out an output terminal from the output of the second inverter. Selection signal generating means for generating n selection signals in which only one of them is effective; a first channel type transistor element which is turned on / off by the first to nth selection signals; 1st to nth setting means formed by cascading a first channel type transistor element that is turned on and off by an n set signal between a power supply terminal and the output terminal, and the first to nth setting means. A second channel type transistor element that is turned on / off by a selection signal and a second channel type transistor element that is turned on / off by the first to nth reset signals; Those constructed from the first to n reset means comprising cascaded between the ground terminal of the output terminal.

According to a second aspect of the invention, in the first aspect of the invention, the first channel type transistor element is a p-channel MOSFFET, and the second channel type transistor element is an n-channel M-type.
It is characterized by being an OSFET.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a transistor-level circuit diagram of a programmable set-reset flip-flop according to the same embodiment. Here, signal names having the same meanings as in FIG. 2 described above are given the same names, and description thereof will be omitted here.

In the figure, reference numerals 21 to 23 are inverters, and 24 to 27 are p-channel transistors (MOSFs).
ET; MOS field effect transistor), 28 to 31 are n
It is a channel transistor (MOSFET). Here, the inverters 21 and 22 form a flip-flop 20. The inverter 22 is an open drain type logic gate. Furthermore, the signal Cx and the signal Dx are the inversion signals of the above-mentioned signal C and the signal D, respectively. As can be easily calculated from FIG. 1, the programmable set / reset flip-flop according to the present embodiment is composed of 2 × 3 + 1 × 8 = 14 transistors, which is higher than that of the conventional circuit described above. The number is about half.

Next, the operation of the programmable set / reset flip-flop having the above configuration will be described. First, it is assumed that the switching signal d is "0". in this case,
The switching signal d turns on the transistors 24 and 30 and turns off the transistors 26 and 29, so that the operation of this circuit does not depend on the levels of the signals B and Dx. First, to reset the flip-flop 20,
The signal A is set to "1" and the signal C is set to "0". Then, the transistor 31 turns on and the transistor 25 turns off, and the input of the flip-flop 20 is connected to the ground potential. As a result, the output signal q becomes "0" and the flip-flop 20 is reset.

Next, to set the flip-flop 20, the signal A is set to "0" and the signal C is set to "1".
Then, the transistor 31 turns off and the transistor 25
Is turned on, and the input of the flip-flop 20 is connected to the power supply potential. As a result, the output signal q becomes "1" and the flip-flop 20 is set.

Next, when the signals A and C are both set to "0", both the transistors 31 and 25 are turned off,
The level held by the flip-flop 20 is directly obtained as the output signal q. At that time, the contents of the flip-flop 20 are unchanged. When both the signal A and the signal C are set to "1", both the transistors 31 and 25 are turned on, so that the power supply and the ground (although the on resistance of the transistor exists) are short-circuited. As in the art, this combination is not used in this embodiment either.

Next, assume that the switching signal d is "1". In this case, the switching signal d causes the transistor 24,
30 is off, transistors 26 and 29 are on,
The operation of this circuit does not depend on the levels of the signal A and the signal Cx. The circuit operation when the switching signal d is "1" is the same as the circuit operation when the switching signal d is "0": signal A → signal B, signal C (Cx) → signal D (Dx), transistor 25 → transistor 27, Transistor 31 →
It suffices if the transistor 28 is replaced. Therefore, the operation can be easily understood, and the detailed operation will be omitted.

In the above embodiment, the signals C,
Instead of D, signals Cx and Dx which are inverted signals are used. In general, such an inverted signal is often used in a peripheral circuit other than the programmable set / reset flip-flop, and such a signal is generally used also in the case of the present embodiment.

In the above embodiment, only two sets of set / reset signal pairs are switched.
It is also possible to make it possible to switch n (n is a natural number of 3, 4, ...) Set / reset signal pairs. For that purpose, a) the switching signals for bits corresponding to the number of set / reset signal pairs are input, and b) n sets of reset circuits composed of transistors 24, 25, 30, 31 are provided, and c) By decoding the switching signal of a) above,
A decoder for selecting any one of the n sets of reset circuits is provided, and d) each set is set such that only one of the n sets of reset circuits is activated by the selection signal output of the decoder. Reset circuit transistors 24 and 3
It may be configured to control 0.

[0017]

As described above, according to the present invention,
Since the flip-flop is composed of two inverters and each of the setting means and each of the reset means is composed of two transistor elements, the number of required transistor elements is small and therefore the occupied area is small. An effect that a low power consumption type programmable set-reset flip-flop can be configured is obtained.

Further, according to the present invention, since each set means and each reset means are directly connected to the output terminal, the delay time until the change of the set / reset signal or the switching signal is propagated to the output terminal. There is also an effect that it is small and can operate at high speed.

[Brief description of drawings]

FIG. 1 is a programmable circuit diagram according to an embodiment of the present invention.
It is a transistor level circuit diagram of a set reset flip-flop.

FIG. 2 is a gate-level circuit diagram of a programmable set-reset flip-flop according to the related art.

FIG. 3 is a truth table showing the circuit operation of a programmable set / reset flip-flop according to the same technology.

[Explanation of symbols]

20 ... Flip-flop, 21-23 ... Inverter, 2
4-27 ... p-channel transistors, 28-31 ... n
Channel transistor

Claims (2)

[Claims] 1. A set / reset operation of a flip-flop is controlled by selecting one of the first to n-th set / reset signal pairs based on a switching signal and by the selected set / reset signal pair. A programmable set-reset flip-flop, comprising a first inverter and an open-drain type second inverter connected in a loop form, wherein an output terminal is taken out from the output of the second inverter. And a selection signal creating unit that creates n selection signals based on the switching signal, in which only one of the first to nth selection signals is valid, and the first to first selection signals. First turned on / off by an n selection signal
No. 1 to No. 1 in which the channel type transistor element and the first channel type transistor element that is turned on / off by the first to nth set signals are connected in series between the power supply terminal and the output terminal. n setting means, and a second ON / OFF switch according to the first to nth selection signals
No. 1 to No. 1, which are formed by cascading the channel type transistor element and the second channel type transistor element turned on / off by the first to nth reset signals between the ground terminal and the output terminal. n reset means and a programmable set reset flip-flop. 2. A transistor element of the first channel type is a p-channel MOSFET, and a transistor element of the second channel type is an n-channel MOSF.
The programmable set-reset flip-flop according to claim 1, which is an ET.