JPH09213595A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: A semiconductor chip warps due to a difference in coefficient of thermal expansion between a surface coating covering an element formation surface of the semiconductor chip and the semiconductor substrate, and the warp becomes apparent as the semiconductor chip becomes thinner. For example, there is a problem that a defective connection of bonding occurs due to a difference in height of the protruding electrodes of the semiconductor chip. SOLUTION: A back surface coating film having thermal characteristics similar to those of the surface coating film formed on the element formation surface is provided on the surface of the semiconductor chip on which the element is not formed. For example, when the coefficient of thermal expansion of the surface coating is larger than that of the semiconductor substrate, a back coating having a coefficient of thermal expansion larger than that of the semiconductor substrate is formed, and in the opposite case, the coefficient of thermal expansion is higher than that of the semiconductor substrate. To form a backside coating having a small [Effect] The volume change due to the heat of the back surface coating cancels the bending moment caused by the volume change due to the heat of the front surface coating, thereby preventing the semiconductor chip from warping.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a technique effectively applied to a thin semiconductor device.

[0002]

2. Description of the Related Art In the manufacture of semiconductor devices, various elements forming a circuit, wiring layers connecting the formed elements, and interlayer insulating films for insulatingly separating the wiring layers are formed in a plurality of regions on a wafer made of single crystal silicon or the like. A wafer process for forming a protective insulating film and the like is performed, and the wafer for which the wafer process has been completed is cut into individual regions and separated into individual semiconductor chips.

However, in such a semiconductor chip, the function of the circuit is only a few μm on the substrate surface, but there is a problem of strength or rigidity in the wafer process. Therefore, the thickness of the wafer is from 550 μm to 725 μm. Is manufactured using.

On the other hand, in thin semiconductor devices such as IC cards, there is a demand for thinner semiconductor chips to be mounted for further thinning.

Therefore, the surface of the wafer on which the elements have been formed, on which the elements are not formed, is mechanically or chemically polished so that the thickness of the wafer is 200 μm to 5 μm.
The semiconductor chip is made thinner by backside grinding to 00 μm.

[0006]

However, the present inventors have found that the following problems become apparent as the semiconductor device becomes thinner. In a semiconductor chip, due to the difference in the coefficient of thermal expansion between the surface coating made of the interlayer insulating film, the wiring layer, the protective insulating film, etc. and the semiconductor substrate, the volume change caused by heat is different, so that thermal stress occurs and the semiconductor chip is bent. A moment may act and the semiconductor chip may be warped.

For example, a silicon nitride film formed by the plasma CVD method, which is used as an insulating film, has a coefficient of thermal expansion slightly smaller than that of single crystal silicon which is a semiconductor substrate, and therefore is small as viewed from the element forming surface and the wafer central portion is small. A protruding warp (hereinafter referred to as a convex warp) is generated, and since the polyimide film has a coefficient of thermal expansion that is considerably larger than that of single crystal silicon, which is a semiconductor substrate, the center of the wafer is greatly depressed when viewed from the element formation surface. A warp (hereinafter referred to as a concave warp) is caused.

The warp of the semiconductor chip increases as the semiconductor chip becomes thinner, and the thickness of the semiconductor chip is 2
It becomes conspicuous in the case of less than 00 μm. When such a warp of the semiconductor chip occurs, for example, the flatness of the protruding electrode that serves as an external terminal of the semiconductor chip becomes different, which causes a problem such as defective bonding connection, or the like. When the warp of the chip is large, there arises a problem that the chip cannot be sucked by the vacuum suction collet at the time of handling the chip.

An object of the present invention is to solve the above problems and provide a technique capable of eliminating the warp of a semiconductor chip due to heat.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

Means for Solving the Problems Among the inventions disclosed in the present application, the outline of typical inventions will be briefly described.
It is as follows.

According to the present invention, the back surface coating having thermal characteristics similar to those of the front surface coating formed on the element forming surface is provided on the surface of the semiconductor chip on which the elements are not formed, whereby the volume change of the back surface coating due to heat is changed. This offsets the bending moment caused by the volume change of the surface coating due to heat, and prevents the semiconductor chip from warping.

For example, when the coefficient of thermal expansion of the surface coating is larger than that of the semiconductor substrate, a back coating having a coefficient of thermal expansion larger than that of the semiconductor substrate is formed, and the coefficient of thermal expansion of the surface coating is higher than that of the semiconductor substrate. When the coefficient of thermal expansion is smaller than that of the semiconductor substrate, a back surface coating film having a coefficient of thermal expansion smaller than that of the semiconductor substrate is formed. The back surface film is selected in consideration of the coefficient of thermal expansion of the surface film, extension due to volume change, elasticity, film thickness, etc., and should form a film that produces a force approximately equal to the force generated by the volume change of the surface film due to heat. Offsets the bending moment of the surface coating.

Embodiments of the present invention will be described below.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals and their repeated description will be omitted.

[0016]

FIG. 1 is a vertical sectional view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is an enlarged vertical sectional view showing a portion A in FIG. Is.

In the figure, 1 is a semiconductor chip in which an element is formed on the main surface of a semiconductor substrate such as single crystal silicon, 2 is a surface coating such as an insulating film formed on the element forming surface of the semiconductor chip 1, and 3 is an element. This is a backside coating formed on the surface not formed, that is, the surface opposite to the element formation surface.

According to the present invention, the back surface coating 3 having a thermal expansion characteristic similar to that of the surface coating 2 formed on the element forming surface is provided on the surface of the semiconductor chip 1 on which the elements are not formed. By the volume change due to the heat of
The bending moment due to the thermal stress of the surface coating 2 is offset to prevent the warpage of the semiconductor chip 1.

For example, when the force generated by the heat-induced volume change of the surface coating 2 is larger than the force caused by the heat-induced volume change of the semiconductor substrate, the back surface coating 3 having a larger force generated by the heat-induced volume change than the semiconductor substrate. And the force generated by the heat-induced volume change of the surface coating 2 is smaller than the force caused by the heat-induced volume change of the semiconductor substrate, the back surface coating 3 smaller than the force caused by the heat-induced volume change of the semiconductor substrate. To form.

The backside coating 3 is selected in consideration of the coefficient of thermal expansion of the frontside coating 2, elongation due to volume change, elasticity and film thickness.
A coating film is formed to generate a force substantially equal to the force generated by the volume change of the surface coating 2 due to heat, and the bending moment of the surface coating 2 is offset.

Further, since the warp of the semiconductor chip 1 is greater in the problem caused by the concave warp than in the problem caused by the convex warp, the semiconductor chip 1 has no warp or a slightly convex warp. It is desirable to do so. Therefore, the force generated by the heat-induced volume change of the back surface coating is equal to the force generated by the heat-induced volume change of the surface coating, or slightly smaller than the thermal stress of the surface coating.

As the material of the back surface coating 3, for example, an ultraviolet curable polymer, a thermosetting polymer, a thermosetting photosensitive polymer, a thermoplastic polymer or the like is used.

In addition, the above-mentioned semiconductor chip 1 is provided with the protruding electrode 6 serving as an external terminal on the element forming surface via the pad 4 and the barrier metal, and the wiring 8 of the circuit board 5 and the protruding electrode 6 are electrically connected. The semiconductor chip 1
And the circuit board 5 are electrically connected. The circuit board 5 is a film 7 of epoxy type, polyimide type, PET, or the like.
The wiring 8 is formed of copper foil or Ag paste. In the case of copper foil, Ni is formed after the wiring pattern is formed.
+ Au plating treatment is performed.

In the present embodiment, this electrical connection is collectively performed by the thermosetting anisotropic conductive sheet 9.
The anisotropic conductive sheet 9 has a configuration in which conductive particles 9b are mixed in a binder 9a which is an insulating thermosetting polymer film. For example, the wiring 8 and the protruding electrode 6 are connected to each other by the anisotropic conductive sheet 9. When they are faced to each other and pressed against each other, the binder 9a is deformed and the conductive particles 9b come into direct contact with the wiring 8 and the protruding electrode 6, and the wiring 8 and the protruding electrode 6 are electrically connected via the conductive particle 9b. By heating in this state, the binder 9a is hardened, the semiconductor chip 1 can be fixed to the circuit board 5, and the electrical connection between the wiring 8 and the protruding electrode 6 can be maintained.

As the conductive particles 9b, spherical particles of resin or nickel or the like, plated with gold or the like, amorphous particles of nickel or the like are used.

In the connection using the anisotropic conductive sheet 9 as described above, it is important that the interval between the protruding electrode 6 and the wiring 8 is constant, and when the semiconductor chip 1 is warped, Even in the pressure contact state, the conductive particles 9b are not able to partially contact the wiring 8 or the protruding electrode 6, and a connection failure is likely to occur.

After connecting the semiconductor chip 1 to the circuit board 5 as described above, potting for coating the protective resin 10 made of epoxy resin or the like around the semiconductor chip 1 is performed for the purpose of improving the moisture resistance of the semiconductor device. Done.

(Manufacturing Method 1) Next, a method of manufacturing the above-described semiconductor device will be described step by step with reference to FIGS.

First, the thickness 50 after the wafer process is completed.
As a preparatory step for backgrinding the wafer 11 of 0 μm to 800 μm single crystal silicon, a protective tape 12 made of resin or the like is used to protect the element forming surface of the wafer 11 from being damaged or contaminated by the backgrinding process. 1
1 is attached to the element formation surface to protect the element formation surface. This state is shown in FIG.

Next, the wafer 11 is sucked and fixed on the vacuum suction type holding substrate 13 with the protective tape side down. This state is shown in FIG.

Next, mechanical grinding is performed while applying cutting water by the grindstone 14 that rotates at a high speed. The wafer 11 is thinned by polishing it to about 50 μm. This state is shown in FIG. Note that other methods such as chemical polishing such as etching or lapping using free abrasive grains can be used for the back surface grinding.

Next, an ultraviolet curable polyimide resin is applied to the back surface of the ground wafer 11 and is irradiated with ultraviolet rays to be cured to form a back surface coating 3 of about 5 μm. This state is shown in FIG.

Next, the wafer 11 is attached onto the dicing tape 16 fixed to the frame 15 with the back surface coating 3 facing. An adhesive is applied to the dicing tape 16, and a type of adhesive whose adhesive strength is lowered by heating is used. This state is shown in FIG.

Next, the protective tape 12 is peeled and removed using a peeling tape (not shown) or the like. This state is shown in FIG.

Next, the wafer 11 together with the back surface coating 3 is separated by the diamond blade saw into the individual semiconductor chips 1.
Disconnect. This cutting is performed by full dicing in which the diamond blade saw reaches the dicing tape 16 slightly. This state is shown in FIG.

Next, tension is applied to the dicing tape 7 to extend the dicing tape 7 in the horizontal direction to widen the intervals between the individual semiconductor chips 1 to facilitate the individual taking out of the semiconductor chips 1. This state is shown in FIG.

Next, a thermosetting anisotropic conductive sheet 9 is attached to a region of the separately prepared circuit board 5 where the wiring 8 connected to the semiconductor chip 1 is formed, and heated by the heat collet 17. This fixing may be light enough to prevent the sheet from slipping. This state is shown in FIG.

Next, after the recognition mark of the semiconductor chip 1 and the wiring pattern of the circuit board 5 are confirmed by an optical recognition device (not shown), the semiconductor chip 1 is accurately aligned, and then the circuit board 5 is changed. The conductive sheet 9 and the element forming surface of the semiconductor chip 1 to be attached are made to face each other, and in this state,
The heat collet 18 at about 120 ° C is the dicing tape 1
The semiconductor chip 1 on 6 is pushed up and pressed against the anisotropic conductive sheet 9 of the circuit board 5 via the dicing tape 16,
The semiconductor chip 1 is temporarily fixed to the circuit board 5 by the heat of the heat collet 18. After that, the circuit board 5 is lowered to press the semiconductor chip 1 against the heat collet 17, and the heat of the heat collet 17 heats the binder of the anisotropic conductive sheet 9 by heating at about 180 ° C. for about 30 seconds. Then, the semiconductor chip 1 is fixed to the circuit board 5 in a pressed state. As a result, the conductive particles of the anisotropic conductive sheet electrically connect the protruding electrodes of the semiconductor chip to the wiring of the circuit board, and the semiconductor chip 1 and the circuit board 5 are also electrically connected. This state is shown in FIG.

(Manufacturing Method 2) Next, another manufacturing method of the above-described semiconductor device will be described step by step with reference to FIGS.

First, a single crystal silicon wafer 1 having a thickness of 500 μm to 800 μm, which has been subjected to the wafer process, is placed with the element formation surface facing down on the vacuum suction type holding substrate 13.
1 is adsorbed and fixed. This state is shown in FIG.

Next, mechanical grinding is performed while applying cutting water by the grindstone 14 rotating at a high speed. The wafer 11 is thinned by polishing it to about 10 μm. This state is shown in FIG. Note that other methods such as chemical polishing such as etching or lapping using free abrasive grains can be used for the back surface grinding.

Next, a UV curable polyimide resin is applied to the back surface of the ground wafer 11 to form a back surface coating 3 of about 2 μm. This state is shown in FIG.

Next, the wafer 11 is removed from the holding substrate 13, the dicing area of the backside coating 3 is covered with a mask (not shown), and ultraviolet rays are irradiated to cure the backside coating 3 excluding the dicing area. The back surface coating 3 in the diced region which has not been cured by being irradiated with ultraviolet rays is removed. The mask covering the dicing area can be formed by using the position information of the element formation surface of the wafer 11. This state is shown in FIG.

Next, the wafer 11 is attached onto the dicing tape 16 fixed to the frame body 15 with the element formation surface facing. An adhesive is applied to the dicing tape 16, and a type of adhesive whose adhesive strength is lowered by heating is used. Then, the wafer 11 is cut into individual semiconductor chips 1 with a diamond blade saw. This cutting is performed by full dicing in which the diamond blade saw reaches the dicing tape 16 slightly. This state is shown in FIG.

In this manufacturing method, since the back surface coating film 3 in the dicing area is removed prior to dicing, deterioration of the dicing blade due to cutting of the organic coating film does not occur. Further, since the formation region of each semiconductor chip 1 can be visually observed from the back surface, dicing from the back surface is easy. By performing the dicing from the back surface, adhesion of cutting chips generated by dicing to the element formation surface of the semiconductor chip 1 is possible. There are advantages such as not occurring.

Next, the anisotropic conductive sheet 9 is attached to the area of the separately prepared circuit board 5 where the wiring 8 connected to the semiconductor chip 1 is formed, and heated by the heat collet 17. This fixing may be light enough to prevent the sheet from slipping. This state is shown in FIG.

About 120 from below the dicing tape 16
The vacuum suction collet 1 which pushes up the semiconductor chip 1 to be attached via the dicing tape 16 by the heat collet 18 at ℃ and stands by above the semiconductor chip 1.
The back surface coating 3 of the semiconductor chip 1 is pressed against 9 to adsorb and fix the semiconductor chip 1. FIG. 20 shows this state.

Next, the anisotropic conductive sheet 9 attached to the circuit board 5 and the element forming surface of the semiconductor chip 1 to be attached are made to face each other, and the recognition mark of the semiconductor chip 1 and the circuit board are made by an optical recognition device (not shown). After confirming the wiring pattern of 5 and accurately aligning the semiconductor chip 1, the vacuum suction collet 19 is lowered to press the semiconductor chip 1 against the circuit board 5 so that the semiconductor chip 1 is pressed against the circuit board 5. I will fix it. As a result, the conductive particles of the anisotropic conductive sheet electrically connect the protruding electrodes of the semiconductor chip to the wiring of the circuit board, and the semiconductor chip 1 and the circuit board 5 are also electrically connected. This state is shown in FIG.

The inventions made by the present inventors are as follows.
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

[0050]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, there is an effect that the semiconductor chip does not warp due to the difference in the coefficient of thermal expansion between the surface coating of the semiconductor chip and the semiconductor substrate.

(2) According to the present invention, due to the above effect (1), it is possible to improve the flatness of the protruding electrode which becomes an external terminal of the semiconductor chip.

(3) According to the present invention, due to the above effect (2), there is an effect that a defective connection of bonding does not occur.

(4) According to the present invention, the semiconductor chip can be made thinner due to the effect (1).

[Brief description of drawings]

FIG. 1 is a vertical sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a vertical cross-sectional view showing an enlarged main part of the semiconductor device of FIG.

FIG. 3 is a vertical cross-sectional view showing, step by step, a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a vertical cross-sectional view showing, step by step, a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a vertical cross-sectional view showing, step by step, a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a vertical cross-sectional view showing, step by step, a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a vertical cross-sectional view showing each step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a vertical cross-sectional view showing, step by step, a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 9 is a vertical cross-sectional view showing, step by step, the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 10 is a vertical cross-sectional view showing, step by step, the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 11 is a vertical cross-sectional view showing, step by step, the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 12 is a vertical cross-sectional view showing, step by step, the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 13 is a vertical cross-sectional view showing, step by step, the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 14 is a vertical cross-sectional view showing, step by step, another method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 15 is a vertical cross-sectional view showing, step by step, another method of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 16 is a vertical cross-sectional view showing, step by step, another method of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 17 is a vertical cross-sectional view showing, step by step, another method of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 18 is a vertical cross-sectional view showing, step by step, another method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 19 is a vertical cross-sectional view showing, step by step, another method of manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 20 is a vertical cross-sectional view showing, step by step, another method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 21 is a vertical cross-sectional view showing, step by step, another method of manufacturing the semiconductor device according to the embodiment of the present invention.

[Explanation of symbols]

1 ... Semiconductor chip, 2 ... Front surface coating, 3 ... Back surface coating, 4 ...
Pads, 5 ... Circuit board, 6 ... Projection electrodes, 7 ... Film,
8 ... Wiring, 9 ... Anisotropic conductive sheet, 9a ... Binder, 9b
... conductive particles, 10 ... protective resin, 11 ... wafer, 12 ... protective tape, 13 ... holding substrate, 14 ... grinding stone, 15 ... frame body,
16 ... Dicing tape, 17, 18 ... Heat collet, 19 ... Vacuum adsorption collet.

Claims (10)

[Claims] 1. A semiconductor device in which an element is formed on a main surface of a semiconductor substrate and a surface coating is formed on the semiconductor substrate of the element forming surface, and a thermal property is different from that of the surface coating on a surface opposite to the element forming surface. A semiconductor device having a similar backside coating. 2. The semiconductor device according to claim 1, wherein the force generated by the heat-induced volume change of the back surface coating is substantially equal to the force generated by the heat-induced volume change of the front surface coating. 3. The semiconductor device according to claim 1, wherein the surface coating is made of an interlayer insulating film, a wiring layer, a protective insulating film, or the like. 4. The semiconductor device according to claim 1, wherein the surface of the semiconductor substrate opposite to the element formation surface is ground. 5. The back coating is an ultraviolet curable polymer,
The semiconductor device according to any one of claims 1 to 4, which is a thermosetting polymer, a thermosetting photosensitive polymer, or a thermoplastic polymer. 6. A method of manufacturing a semiconductor device, wherein an element is formed on a main surface of a semiconductor substrate, and a surface coating is formed on the semiconductor substrate on the element forming surface, wherein the surface coating is provided on a surface opposite to the element forming surface. A method of manufacturing a semiconductor device, comprising the step of forming a back surface coating having similar thermal characteristics. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the force generated by the heat-induced volume change of the back surface coating is substantially equal to the force generated by the heat-induced volume change of the front surface coating. . 8. The method of manufacturing a semiconductor device according to claim 6, wherein the surface film is made of an interlayer insulating film, a wiring layer, a protective insulating film, or the like. 9. The semiconductor according to claim 6, further comprising a step of grinding the surface of the semiconductor substrate opposite to the element formation surface to thin the semiconductor substrate. Device manufacturing method. 10. The back surface coating is an ultraviolet curable polymer, a thermosetting polymer, a thermosetting photosensitive polymer, or a thermoplastic polymer, according to any one of claims 6 to 9. A method for manufacturing a semiconductor device as described above.