JPH09205164A - Semiconductor chip package and method of manufacturing the same - Google Patents

Abstract

(57) An object of the present invention is to improve reliability and productivity of a semiconductor chip package device using a circuit board by strengthening a bonding force between the circuit board and a package body. In a semiconductor chip package having a circuit board (10), a solder resist (20) is applied to the upper surface and the lower surface of the circuit board (10), and this is selectively etched to form a circular or hexagonal opening (38) in the solder resist (20). The molding resin forming the package body 36 is brought into direct contact with the circuit board 10 through the open portion 38, and the bonding force between the circuit board 10 and the package body 36 is strengthened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip package, and more specifically, it applies a solder resist to the upper and lower surfaces of a circuit board and then selectively etches the solder resist to form an opening in the package. The present invention relates to a semiconductor chip package in which a molding resin that forms a body is filled in the open portion to enhance the bonding force between the circuit board and the package body through the open portion.

[0002]

2. Description of the Related Art A technique for directly mounting a semiconductor chip on a circuit board does not require a primary assembly step of packaging individual chips separated from a wafer, which enables reduction of manufacturing cost and miniaturization of package elements. To do. In such a direct chip mounting technique, TAB (Tape Automated Bonding) or wire bonding is used for electrical connection of chips. The latter has the advantage of being low cost. PGA (Pin Grid Array) package and BGA (B
All Grid Array) packages, but these packages are pins (PGA packages) for mounting the chip on a printed circuit board provided with a predetermined conductive pattern and for electrical connection with an external system. Alternatively, a solder ball (BGA package) is used. The conductive wiring pattern, that is, the copper pattern and the semiconductor chip are protected from the external environment by mounting the chip on a circuit board and then sealing with a molding resin. A solder resist or a solder mask is applied to the circuit board before sealing with the molding resin.

The solder resist or solder mask is a protective coating film made of an organic material having resistance to heat and chemical substances. The solder resist has a role of preventing an electrical short circuit and a weight reduction of a circuit board when soldering is performed on a specific portion, for example, a solder ball pad. Further, since the solder resist is a thermal and electrical insulating layer, it contributes to the reduction of the mounting area of the surface mount semiconductor element. Further, the solder resist also has a role of protecting the conductive wiring pattern from physical impact, dust, moisture and the like.

The solder resist is made of a reactive organic material as a basic material, and a typical example thereof is a thermally cured epoxy or an ultraviolet ray curable acrylic. Such solder resist is widely used as a surface coating film on a circuit board provided with a circuit pattern.

FIG. 6 is a cross-sectional view of a prior art BGA package in which a solder resist is applied to the substrate. A copper pattern layer for electrically connecting the semiconductor chip 130 and the solder balls 128 is formed on the substrate 110. A via hole 124 is formed to connect the copper pattern layers provided on the upper surface and the lower surface of the substrate, and a copper film is applied to the inner wall of the via hole 124. A chip mounting region 132 on which a semiconductor chip is mounted is formed on the upper surface of the substrate 110. The bonding pad of the semiconductor chip 130 is electrically connected to the upper pattern layer by the wire 134. Substrate 110
A solder ball pad 126 to which a solder ball 128 is attached is provided on the lower surface of the. Reference numeral 127
Is a heat-dissipating via hole for dissipating heat generated from the semiconductor chip to the outside during operation of the semiconductor element.

Before performing electrical connection of semiconductor chips by wire bonding, a solder resist 120 is applied to the upper and lower surfaces of the substrate 110. At this time, the chip mounting region 132, the pattern layer portion for wire bonding, and the solder ball pad 126 region are excluded. After the chip connection is completed, a thermosetting resin or a thermoplastic resin is molded on the upper surface of the substrate 110 to protect the semiconductor chip and the conductive pattern to form a package body 136. However, the solder resist 120
Includes a curing step of curing the adhesive used to bond the semiconductor chip 130 and the chip mounting area 132,
At the wire bonding stage where a high temperature is applied to the bonding stage and the package body 13 under high temperature and high pressure conditions.
During the molding step forming 6 several thermal stresses will be experienced. As a result, a thin oil film may be formed on the solder resist 120, but such an oil film reduces the bonding force between the solder resist 120 and the package body 136. The decrease in the coupling force between the circuit board and the package body lowers the reliability of the BGA package and increases the defective rate of the product. As a result, the productivity of the semiconductor chip package device using the circuit board decreases. I will let you.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to enhance the bonding force between a circuit board and a package body to improve the reliability and productivity of a semiconductor chip package device using the circuit board. It is in.

[0008]

In order to achieve the above object, according to the present invention, a semiconductor chip and a circuit board provided with a chip mounting area for mounting the semiconductor chip and a predetermined conductive wiring pattern are provided. In a semiconductor chip package that includes a package body that protects the semiconductor chip and the wiring pattern and forms the appearance of the package,
Solder resist is applied to the upper and lower surfaces of the circuit board, and the solder resist is provided with a plurality of openings having a predetermined shape, and a part of the package body is connected to the circuit through the openings. It was designed to be in direct contact with the substrate.

A semiconductor chip, a circuit board on which a chip mounting area for mounting the semiconductor chip and a predetermined conductive wiring pattern are provided, the semiconductor chip and the wiring pattern are protected, and a package having an appearance of the package is formed. A method of manufacturing a semiconductor chip package including a body, a step of applying a solder resist on the upper surface and the lower surface of a circuit board, a step of preparing a mask having a pattern of open portions formed in the solder resist, and a photosensitive film on the solder resist. A step of exposing the photosensitive film through a mask to develop it, a step of selectively etching the solder resist through the developed photosensitive film to form an opening in the solder resist, and The package body is further molded on the upper surface, and the package body is connected to the circuit through the opening. It was composed of a step to make direct contact with the plate.

According to the present invention as described above, the molding resin forming the package body comes into direct contact with the circuit board through the opening, and the bonding force between the circuit board and the package body is strengthened.

The plurality of open portions formed in the solder resist can be formed as a plurality of circular or hexagonal open portions.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to the drawings.

FIG. 1A is a sectional view of a BGA package according to the present invention, and FIG. 1B is a detailed view thereof. BG
The A package is surface-mounted on the mother board of the system by a plurality of solder balls 28 attached to the lower surface of the board 10, and is suitable for packaging a semiconductor chip having a large number of input / output terminals. Substrate 10
Has a structure in which a BT (bismaleinimide triazine) resin or prepreg layer and a copper pattern layer are pressure-bonded. The copper pattern layer is a conductive pattern layer for electrically connecting the semiconductor chip 30 and the solder ball 28, and includes two layers on the upper surface and the lower surface of the substrate, two layers inside the substrate, and a total of four layers. It is composed of layers. The upper pattern layer 23 and the solder ball pad 26 on the lower surface are connected to each other by a signal via hole 24. The heat generated from the semiconductor chip 30 is radiated to the outside through the heat radiation via hole 27.

As described above, the solder resist 20 is applied to the upper and lower surfaces of the substrate 10 before wire bonding the semiconductor chip and the conductive pattern layer. On this occasion,
Solder resist 2 is provided on the chip mounting area 32 on the upper surface, the area of the upper surface of the pattern layer 23 where the wire is wedge-bonded, and the solder ball pad 26 on the lower surface.
0 is not formed. As shown in FIGS. 1A and 1B, and FIGS. 3A and 3B, the solder resist 20 has a plurality of openings 38, or 50 and 60, so that the solder resist 20 may be formed during the molding process for forming the protective package body 36. Filling resin is filled in the open portions 38, 50 and 60. Therefore, a part of the molding resin comes into direct contact with the circuit board. The other molding resin comes into contact with the solder resist 20. Further, even if the oil film 21 is formed on the solder resist 20, a part of the upper surface of the substrate 10 comes into direct contact with the molding resin, so that the bonding force of the package body 36 does not decrease.

FIG. 2 is a plan view of a circuit board coated with the solder resist according to the present invention.

The copper pattern layer 2 is formed on the upper surface of the circuit board 10.
A bonding region 25, which is electrically connected to the semiconductor chip 30, is formed at one end of the semiconductor chip 3, and a separation bar 40 is formed to distinguish the bonding region 25 from other chip package regions. A conductive pattern layer is also provided on the lower surface of the circuit board 10, and is connected to the upper pattern layer or the internal pattern layer by the via hole 24. 3A or 3B is formed on the entire upper surface of the circuit board 10 excluding the chip mounting area 32 having the heat dissipation via hole and the bonding area 25.
A solder resist having an opening having a circular shape or a hexagonal shape as shown in FIG.

As shown in FIG. 3A, the circular opening 5 is formed.
In the case of a solder resist having 0, it is preferable that the open portion 50 has a diameter C of 0.2 mm or more, and the distance Pa between the centers of the open portions 50 is 0.5 mm or more. As shown in FIG. 3B, in the hexagonal open portions 60, the interval T between the open portions 60 is 0.2 mm or more, and the distance Pb between the centers of the open portions 60 is 0.5 mm or more. It is preferable. The open portions 50 and 60 are not applied to the entire surface of the solder resist to be applied, but may be applied only to a predetermined area where the protective package body is formed.

FIGS. 4A, 4B and 4C and 5A and 5B are flow charts showing a series of steps for applying the solder resist to the upper and lower surfaces of the circuit board to form the opening according to the present invention. . The inner copper pattern layer is not shown for simplicity of the drawing.

Referring to FIG. 4A, the copper pattern layer 23
The circuit board 10 having the die pad region 32, the via hole 27, and the solder ball pad 26 is prepared.
Next, as shown in FIG. 4B, a solder resist 20a is applied to the entire lower surface of the substrate. Further, the solder resist 20b is applied to the entire upper surface of the substrate (FIG. 4C). After applying the solder resists 20a and 20b, two masks 70 and 7
Prepare 2 One is a mask 70 for exposing the chip mounting area 32 and the wire bonding area of the conductive pattern layer, and another is for forming the opening according to the present invention. The other is exposing the solder ball pad 26. Of the mask 72. Solder resist 20a, 20
b after coating the photosensitive film 80 on b
The photosensitive film 80 is exposed to UV light through 0 and 72, and developed so that only the unexposed photosensitive film is dissolved (FIG. 5).
A). By selectively etching the solder resist in the portion where the photosensitive film is dissolved by using the etching liquid Na ₂ CO ₃ , the solder resist 20a having a desired pattern,
20b is obtained (FIG. 5B).

The light-shielding portions of the masks 70 and 72 are coated with chromium in order to block UV light and selectively expose the photosensitive film. Whether the chip mounting area, the wire bonding area, the solder ball pad forming area, and the opening forming area should be the portions that receive UV light or the portions that do not receive UV light,
It is determined by the morphology (positive or negative) of the photosensitive film.

[0021]

As described above, in the semiconductor chip package according to the present invention, an opening is provided in a part of the solder resist, and the opening is filled with the molding resin forming the package body. Through this, the coupling force between the circuit board and the package body can be improved.

[Brief description of drawings]

1A is a cross-sectional view of a ball grid array package according to the present invention, and FIG. 1B is a partial detailed view thereof.

FIG. 2 is a plan view of a circuit board coated with a solder resist according to the present invention.

FIG. 3 is a detailed plan view of a solder resist having circular (FIG. 3A) and hexagonal (FIG. 3B) openings according to the present invention.

4A and 4B are diagrams showing a process of applying a solder resist and forming an open portion together with FIG. 5, in which A is a circuit board before application of the solder resist, B is a circuit board having a solder resist applied on its lower surface, and C is further. It is sectional drawing of the circuit board which applied the solder resist on the upper surface.

5A and 5B are diagrams showing a process of applying a solder resist and forming an open portion together with FIG. 4, in which A is a circuit board in a step of forming the open portion using ultraviolet light, and B is a circuit in which the open portion is formed. It is sectional drawing of a board | substrate.

FIG. 6 is a cross-sectional view of a ball grid array package according to the related art.

[Explanation of symbols]

 10 Circuit Boards 20, 20a, 20b Solder Resist 21 Oil Film 22 Wiring Pattern 23 Upper Pattern Layer 24 Signal Via Hole 25 Bonding Area 26 Solder Ball Pad 27 Heat Dissipation Via Hole 28 Solder Ball 30 Semiconductor Chip 32 Chip Mounting Area 34 Bonding Wire 36 Package body 38, 50, 60 Open part 40 Separation bar 70, 72 Mask 80 Photosensitive film

Claims (9)

[Claims] 1. A semiconductor chip, a circuit board on which a chip mounting region for mounting the semiconductor chip and a predetermined conductive wiring pattern are provided, and the semiconductor chip and the wiring pattern are protected, and a package appearance is provided. In a semiconductor chip package having a package body forming a solder body, a solder resist is applied to the upper and lower surfaces of the circuit board, and the solder resist is provided with a plurality of open portions having a predetermined shape. A semiconductor chip package, wherein a part of the package body is in direct contact with the circuit board through the opening. 2. The wiring pattern is formed on the upper surface of the circuit board, is connected to the semiconductor chip by a bonding wire, an upper pattern layer, an internal pattern layer formed inside the circuit board, and the circuit. The lower pattern layer formed on the lower surface of the substrate, wherein the upper pattern layer and the lower pattern layer are electrically connected by a via hole penetrating the circuit board. Semiconductor chip package. 3. The semiconductor chip package according to claim 1, wherein each of the plurality of openings has a circular shape. 4. The semiconductor chip package according to claim 3, wherein the circular opening has a diameter of 0.2 mm or more. 5. The semiconductor chip package according to claim 1, wherein each of the plurality of openings has a hexagonal shape. 6. The semiconductor chip package according to claim 5, wherein the interval between the adjacent hexagonal openings is 0.2 mm or more. 7. The lower pattern layer includes a plurality of solder ball pads, and the semiconductor chip is electrically connected to an external circuit element through the plurality of solder balls attached to the solder ball pads. The semiconductor chip package according to claim 2. 8. A semiconductor chip, a circuit board on which a chip mounting area for mounting the semiconductor chip and a predetermined conductive wiring pattern are provided, and the semiconductor chip and the wiring pattern are protected, and a package appearance is provided. A method of manufacturing a semiconductor chip package, comprising: a package body that forms a package body; and a step of applying a solder resist on an upper surface and a lower surface of the circuit board, and a step of preparing a mask having a pattern of opening portions formed in the solder resist. A step of coating a photosensitive film on the solder resist, a step of exposing and developing the photosensitive film through the mask, and a step of selectively etching the solder resist through the developed photosensitive film to form the solder resist. Forming the opening, and further forming a package body on the upper surface of the circuit board. To, a method of manufacturing a semiconductor package including the steps of package body through the opening is in direct contact with the circuit board. 9. The mask further has a pattern for the chip mounting region, a wire bonding region of the conductive wiring pattern, and a solder ball pad forming region provided on a lower surface of the circuit board. The method for manufacturing a semiconductor chip package according to claim 8.