JPH09198869A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To conserve current consumed. SOLUTION: For example, eight pairs of data signals I/O1, I/O1, I/O2 and I/O2... read out of a memory cell MC are selected sequentially by eight pairs of transmission gates 16 and 17 to be transmitted serially to a single sense amplifier 4. The data signals amplified by the sense amplifier 4 are held individually by eight buffer circuits 7. The operation of the transmission gates 16 and 17 and a latch circuit 6 is controlled by a pulse propagated through signal lines A and A1-A7 with a delay circuit 3 inserted thereinto. This can reduce the number of the sense amplifiers 4 to one from eight in the convention type thereby substantially conserving the consumption of current of the apparatus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a sense amplifier and simultaneously outputting a plurality of bits of signals in parallel, and more particularly to an improvement for reducing the current consumption and downsizing the device.

[0002]

2. Description of the Related Art FIG. 8 is a circuit diagram showing a structure of a main part of a conventional semiconductor memory device which is a background of the present invention. The conventional device 150 is configured as an SRAM capable of simultaneously inputting and outputting an 8-bit data signal in parallel.

In FIG. 8, MC is a memory cell, 1, 2
Is a bit line for transmitting a data signal connected to the memory cell MC, B1 to B8 are regions in the memory cell for individually storing 8-bit data signals input / output simultaneously in parallel for each bit, and R1 to RK are a pair. Regions B1 to B8 each having N memory cells MC connected to the bit lines 1 and 2 of
, A high potential power supply line, 11 and 12 a transmission gate for supplying a reference potential to the bit lines 1 and 2, and a transmission gate 13 for temporarily short-circuiting the bit lines 1 and 2. 14 and 15 are small areas R1
~ Transmission gate 4 for selectively passing a pair of data signals on K pairs of bit lines 1 and 2 belonging to RK, 4 is data signals I / O1, I / O1 ^* passing through transmission gates 14 and 15 ~ I / O8, I / O
8 ^* (in this specification, symbol " ^* " represents an inverted signal), a sense amplifier that amplifies and outputs a high-level or low-level signal, and W1 to WN are small regions R1 to RK
Word lines for transmitting a selection signal for selecting one of the N memory cells MC belonging to, YDEC1 to YDECK are decode signal lines for transmitting control signals to the transmission gates 14 and 15, BEQB is a signal to the transmission gate 13. Is a buffer circuit for temporarily storing the data signals D1 to D8 amplified by the sense amplifier 4.

The conventional device 150 operates as follows when reading a data signal from the memory cell MC.
Word lines W1 to WN and decode signal lines YDEC1 to YDE based on address signals input from the outside.
One memory cell MC is selected for each one of the regions B1 to B8 by CK. Then, eight pairs of data signals I / O1 and I / held by the selected eight memory cells MC
O1 ^{* to} I / O8 and I / O8 ^* are amplified by the sense amplifier 4. Data signals D1 to D8 obtained by amplification
Are temporarily stored in the buffer circuit 7. While being accumulated in the buffer circuit 7, these data signals D1
D8 are read out to the outside in parallel at the same time.

[0005]

By the way, since the sense amplifier 4 is a circuit element which occupies a relatively large area in the semiconductor chip, the conventional device 150 having as many as eight sense amplifiers 4 has a semiconductor chip Large area,
Along with that, there is a problem that the size of the device cannot be avoided. This is also one of the factors that increase the manufacturing cost of the device.

Further, since a large amount of current flows when the sense amplifier 4 operates, the conventional device 150 has a problem that the current consumption is large, and in particular, the peak current is large. This large peak current has been a factor that impairs operation stability and device reliability by causing electrical noise inside the device.

The present invention has been made in order to solve the above-mentioned problems in the conventional device, and provides a semiconductor memory device capable of reducing the current consumption, improving the reliability of the device, and achieving miniaturization. The purpose is to do.

[0008]

In the device of the first invention, M (M ≧ 2) -bit data signals read from a memory cell and amplified by a sense amplifier can be simultaneously output in parallel. In another semiconductor memory device, M switch circuits that receive M data signals read from the memory cells and transmit the M data signals to the sense amplifiers in response to a control signal include the memory cells and the sense amplifiers. And the M switch circuits are L (2 ≦ L ≦
Nominally divided into J (= M / L) groups to which each M) belongs, and one sense amplifier is provided for each one of the J groups. For each 1 of each group, the L switch circuits belonging to the group are connected in common to the input side of the corresponding one sense amplifier, and the output side of the sense amplifier is connected to the output side of the sense amplifier. L latch circuits for holding in response to a clock signal are commonly connected to each one of the sense amplifiers, and are connected in series to the control signal generation circuit that generates a pulse signal. At least L
−1 delay circuits cause the control signals of the L switch circuits belonging to each 1 of the J groups and the clock signals of the L latch circuits connected to each 1 of the sense amplifier to be L It is characterized in that it is supplied in such a manner that one of the pieces is sequentially delayed.

According to a second aspect of the present invention, in the semiconductor memory device of the first aspect, the pulse width of the signal generated by the control signal generating circuit is substantially equal to the delay time in the delay circuit. To do.

The device of the third invention is the semiconductor memory device of the first or second invention, wherein L = M.

According to a fourth aspect of the invention, in the semiconductor memory device according to any one of the first to third aspects of the invention, the delay circuit is a cascade connection of two stages of inverter circuits and a signal connecting them. A capacitive element interposed between the line and the constant potential line, and the first stage of the two-stage inverter circuit has a plurality of PMOS transistors and a plurality of NMOS transistors connected complementarily to each other. And the plurality of PMOS transistors are connected in series with each other, and the plurality of NMOS transistors are also connected in series with each other.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

<1. First Preferred Embodiment> First, a semiconductor memory device according to a first preferred embodiment will be described.

<1-1. Structure> FIG. 1 is a circuit diagram showing a structure of a main part of the semiconductor memory device according to the first embodiment. The device 101 is configured as an SRAM capable of simultaneously inputting and outputting 8-bit signals in parallel. And, preferably, all the circuit elements constituting the device 101 are built in a single semiconductor chip.

As shown in FIG. 1, the memory cell area is conceptually divided into eight areas B1 to B8 corresponding to the number of bits input / output simultaneously in parallel. And the areas B1 to B
Each 1 of 8 further includes K small areas R1 (K is a natural number).
It is divided into ~ RK conceptually. A pair of bit lines 1 and 2 is arranged in each one of the small regions R1 to RK, and N (N is a natural number) memory cells MC are connected to the pair of bit lines 1 and 2. ing.

Each memory cell MC stores a 1-bit signal. That is, the device 101 has a storage capacity of N × K × 8 bits. N word lines W1 to W are provided in N memory cells MC belonging to each one of the small regions R1 to RK.
N are connected to each other. These word lines W1
A signal sent to WN selects one of the N memory cells MC belonging to each of the small regions R1 to RK.

A pair of a data signal to be stored and its inverted signal is stored in the memory cell MC. Therefore, when reading the data signal stored in the memory cell MC, the data signal stored in the memory cell MC and its inverted signal are read out to the paired bit lines 1 and 2, respectively. Also, when writing a data signal to the memory cell MC, a pair of data signals are similarly sent to the bit lines 1 and 2.

The bit lines 1 and 2 are connected to the high potential power source line 9 via the transmission gates 11 and 12. Therefore, the high potential power supply line 9 is connected to the bit lines 1 and 2.
From the potential Vcc of the transmission gates 11 and 1
A reference potential dropped by a voltage corresponding to the gate threshold voltage Vth of the N-channel type transmission gate, which is one of the two components, is supplied. As a result, the pair of data signals stored in the memory cell MC is transmitted to the bit lines 1 and 2.
It is possible to transmit via.

Further transmission gates 14 and 15 are inserted in the bit lines 1 and 2. Area B
K decode signal lines YDEC1 to YDECK are connected to the gate electrodes of the K pairs of transmission gates 14 and 15 belonging to 1 to 1 to B8, respectively. When an active level signal, that is, a low level signal is transmitted to one of the decode signal lines YDEC1 to YDECK,
The corresponding transmission gates 14 and 15 are turned on (conducted).

In the areas B1 to B8, a pair of transmission gates (switch circuits) 16 and 17 are further provided, and in each 1 of the areas B1 to B8, the K pairs of bit lines 1 and 2 are Transmission gate 14,1
On the side opposite to the memory cell MC of No. 5, it is commonly connected to the pair of transmission gates 16 and 17. Therefore, the word lines W1 to WN and the decode signal lines YDEC1 to YDEC that make up a total of N + K signal lines are included.
One of the N × K memory cells MC belonging to each 1 of the regions B1 to B8 is selected by K and connected to the transmission gates 16 and 17.

The signals on the word lines W1 to WN and the decode signal lines YDEC1 to YDECK are transmitted to the device 10
It is obtained by decoding an address signal input to one address signal pin (not shown). As a result, the eight pairs of transmission gates 16 and 17 output the eight pairs of data signals I / O1 and I / O1 ^* output from the eight pairs of memory cells MC designated by the address signal ^.
~ I / O8, I / O8 ^* are input respectively.

A transmission gate 13 is connected between each pair of bit lines 1 and 2. The signal line BEQB is connected to the gate electrode of the transmission gate 13. Immediately before a signal is read from one of the memory cells MC, an active level pulse signal (generally referred to as a “bit line equalize signal”) is sent to the signal line BEQB. As a result, the bit lines 1 and 2 are short-circuited for a short time, and the potentials of the bit lines are made equal to each other.
The signal stored in is correctly read to the bit lines 1 and 2.

A circuit portion for writing a data signal to the memory cell MC is further connected to each bit line 1, 2. However, since the circuit portion for writing is configured similarly to the corresponding portion in the conventional device 150, in FIG. 1, the circuit portion only relating to writing is omitted and only the portion relating to the read operation of the data signal is shown. ing.

Eight pairs of transmission gates 16 and 1
The output side of 7 is commonly connected to a single sense amplifier 4. And the transmission gates 16 and 1
7 is selectively turned on when reading a data signal from the memory cell MC. That is, the eight pairs of transmission gates 16 and 17 have eight pairs of data signals I / O1 and I / O.
It plays a role of selecting one of O1 ^{* to} I / O8 and I / O8 ^* and inputting it to the sense amplifier 4.

Eight pairs of transmission gates 16 and 1
The gate electrode 7 includes a signal line A, and signal lines A1 to A7 on the output side of the seven delay circuits 3 connected in series to the signal line A.
A7 are respectively connected. As shown in the block diagram of FIG. 2, the control signal sent to the signal line A is ATD.
It is generated by the signal generation circuit 28 and the control signal generation circuit 29 connected thereto. ATD signal generation circuit 28
Generates an ATD signal in the form of a pulse signal by detecting a change point of an address signal input from the outside. Further, the control signal generation circuit 29 generates a pulsed control signal to be sent to the signal line A based on this ATD signal.

The ATD signal generation circuit 28 is the conventional device 15
It is a conventionally well-known circuit block that is also provided with 0. Further, the control signal generation circuit 29 outputs a pulse having a rising time to the active level delayed by a certain time from the ATD signal based on the ATD signal, and further having a required pulse width of the certain time. This control signal generation circuit 29
Is the same as a conventionally known circuit block that generates an enable signal for making the sense amplifier 4 operable based on the ATD signal.
It can be configured by setting it to be suitable for 01. Although not shown in FIG. 1, the enable signal is input to the sense amplifier 4 in the device 101 as well.

Returning to FIG. 1, the control signal sent to the signal line A is delayed with a constant delay time each time it passes through one of the delay circuits. Therefore, the eight pairs of transmission gates 16 and 17 are sequentially turned on in a time division manner based on the control signal transmitted to the signal line A. As a result, eight pairs of data signals I / O1, I / O1 ^{* to} I / O
8, I / O8 ^* are sequentially selected in a time division manner and transmitted to the sense amplifier 4.

FIG. 3 is a circuit diagram showing a preferred internal structure of the delay circuit 3. All of the plurality of delay circuits 3 included in the device 101 have the same configuration. In FIG. 3, the delay circuit 3 inserted between the signal line A and the signal line A1 is illustrated as a representative. The delay circuit 3 includes inverter circuits 36, 3 which are interposed between the high potential power line 9 and the low potential power line 20.
7 and a capacitive element 30 having one end connected to a signal line connecting them and the other end connected to a constant potential line such as the low-potential power supply line 20.

The signal delay is mainly caused by the ON resistance of the first-stage inverter circuit 36 and the capacitance of the capacitive element 30. In order to obtain the required delay time, in the first stage inverter circuit 36, a plurality of PMOS transistors 31 and a plurality of NMOS transistors 32 are connected in series.

As described above, in the circuit shown in FIG. 3, the delay time required for the device 101 can be obtained by the cooperation of the high on-resistance of the inverter circuit 36 and the capacitance of the capacitive element 30. The number of inverter stages that require wiring is two. Therefore, the size of the delay circuit 3, that is, the area occupied in the semiconductor chip forming the device 101 can be reduced.

Returning to FIG. 1, the sense amplifier 4 is a kind of differential amplifier and amplifies and outputs a potential difference between a pair of input signals. That is, the minute voltage signal transmitted from one of the memory cells MC is enlarged, and thereby,
The binary signal represented by the memory cell MC is converted into a high level signal and a low level signal having a large level difference. In the device 101, unlike the conventional device 150 shown in FIG. 8, only one sense amplifier 4 is provided.

Eight latch circuits 6 are connected to the output side of the sense amplifier 4. The latch circuit 6 includes a signal line A and signal lines A1 to A1 on the output side of the seven delay circuits 3 which are connected in series to the signal line A.
7 are connected to each other. The signals on these signal lines A and A1 to A7 function as clock pulses for the eight latch circuits 6.

That is, the eight latch circuits 6 hold the output of the sense amplifier 4 in synchronization with the clock pulse supplied by the signal lines A and A1 to A7. Therefore, these latch circuits 6 individually hold the eight signals that are time-divisionally selected by the eight pairs of transmission gates 16 and 17 and that are sequentially amplified by the sense amplifier 4.

Eight buffer circuits 7 are individually connected to the output sides of the eight latch circuits 6. And 8
The data signals D1 to D8 held by the individual latch circuits 6 are
It is input to the buffer circuit 7 and temporarily stored in the buffer circuit 7. Then, the data signals D1 to D8 accumulated in the buffer circuit 7 are simultaneously read out to the outside in parallel. That is, the device 101, like the conventional device 150, is configured to be able to read 8-bit data signals simultaneously in parallel.

FIG. 4 is a circuit diagram showing an example of the internal configuration of the latch circuit 6. The eight latch circuits 6 have the same configuration, and in FIG. 4, the latch circuit 6 using the signal on the signal line A as a clock pulse is shown as a representative. The latch circuit 6 is configured as a standard D latch. That is, the transmission gate 5 functioning as a switch is connected to the input sides of the two inverter circuits 61 and 62 forming the positive feedback loop, and the inverter circuit 63 for matching the level with the input signal is provided on the output side. Are connected.

The signal line A is connected to the gate electrode of the transmission gate 5. Therefore, when the control signal sent to the signal line A becomes the active level, that is, the high level, the transmission gate 5 is turned on, and the output signal of the sense amplifier 4 becomes the inverter circuit 6.
It is transmitted to 1,62. As a result, the inverter circuit 6
The signal levels held by 1 and 62 are updated. Signal line A
After the control signal of is returned to the normal level, that is, the low level, the transmission gate 5 is turned off (interrupted), so that the inverter circuits 61 and 62 are connected to the signal line regardless of the level of the output signal of the sense amplifier 4. The signal level immediately before the control signal of A returns to the normal level is maintained.

Although FIG. 1 shows an example in which the latch circuit 6 and the transmission gates 16 and 17 are connected to the respective separate delay circuits 3, they may be connected to the common delay circuit 3. . By doing so, the number of delay circuits 3 can be reduced to half.

<1-2. Operation> FIG. 5 is a timing chart showing changes in signals on the respective signal lines during the read operation of the device 101. As shown in FIG. 5, by the action of the control signal generation circuit 29 (FIG. 2), a pulsed control signal in response to the ATD signal is sent to the signal line A. Before the control signal on the signal line A becomes active, the word line W1
To WN and decode signal lines YDEC1 to YDECK, the decode signals are sent to the eight pairs of transmission gates 16 and 17, and the data signals of the memory cells MC selected one by one in each of the regions B1 to B8 are transmitted. Eight pairs of data signals I / O1, I / O1 ^{* to} I / O8, I / O8 ^*
, Respectively.

Eight pairs of transmission gates 16 and 1
7 data signals I / O1, I / O1 ^{* to} I / O
8, I / O8 ^* is input, the control signal is sequentially propagated from the signal line A to the signal lines A1 to A7 with a delay time Td defined by the delay circuit 3. Then, for example, while the active level control signal is being sent to the signal line A1, the pair of data signals I / O2,
I / O2 ^* is selectively sent to the sense amplifier 4.
As a result, the data signal D2 is delayed by the buffer circuit 7 with some delay from the rising timing of the control signal on the signal line A1.
Accumulated in. The same applies to the other signal lines A and A2 to A7. This delay mainly occurs in the latch circuit 6 and the buffer circuit 7.

The pulsed control signals delivered to the signal lines A, A1 to A7 are preferably non-overlapping with each other,
Moreover, the pulse width is set so that one of them is always active. In other words, the pulse width of the control signal generated by the control signal generation circuit 29 and transmitted to the signal line A is preferably set so as to substantially match the delay time Td. At this time, the time required to fetch the eight data signals D1 to D8 into the eight buffer circuits 7 is the shortest. That is, the data signals D1 to D8
The time taken to be able to read out to the outside simultaneously in parallel is the shortest.

As described above, in the device 101, the delay circuit 3 and the latch circuit 6 are provided, so that the transmission of the data signal from the eight pairs of transmission gates 16 and 17 to the eight latch circuits 6 can be performed. It is done serially in pieces. That is, the data signals passing through the sense amplifier 4 are multiplexed eight times. As a result, the number of sense amplifiers 4 is unified while maintaining simultaneous 8-bit parallel output to the outside. As a result, the sense amplifier 4, which occupies a relatively large area in the semiconductor chip, is reduced, which leads to downsizing of the device. This also contributes to the reduction of production costs.

Further, by reducing the number of sense amplifiers 4 which are the circuit parts that consume the largest current, the current consumption of the device is reduced. In particular, the sense amplifier 4 has a peak current of about 1/8 of that of the conventional device 150 because it is a main factor of the peak current, that is, the consumption current that flows in a large amount in a peak at a certain time during the operation of the device.
It is greatly reduced to. This results in a significant reduction of electrical noise, resulting in increased operational stability and device reliability.

<2. Second Preferred Embodiment> FIG. 6 shows a second preferred embodiment.
3 is a circuit diagram showing a configuration of a main part of the semiconductor memory device of FIG.
Like the device 101, the device 102 is also configured as an SRAM capable of simultaneously inputting and outputting 8-bit signals in parallel. The storage capacity is also the same as that of the device 101.

In the device 102, the areas B1 to B8 are the first group consisting of the areas B1 and B2, the second group consisting of the areas B3 and B4, the third group consisting of the areas B5 and B6, and the area B7. , B8 are conceptually divided into a fourth group, and two pairs of transmission gates 16 and 17 belonging to each group are commonly connected to a single sense amplifier 4.

In each group, a signal line A and a signal line A1 on the output side of the delay circuit 3 connected in series to the signal line A are provided on the gate electrodes of the two pairs of transmission gates 16 and 17, respectively. It is connected. As a result, in each group, the two pairs of transmission gates 16 and 17 play a role of selecting one of the two pairs of data signals and connecting it to the sense amplifier 4.

That is, the two pairs of transmission gates 16 and 17 are turned on in a time division manner based on the control signal sent to the signal line A. As a result, a pair of data signals input to the two pairs of transmission gates 16 and 17 (for example, in the area B1, the data signals I / O1 and I
/ O1 ^* and data signals I / O2, I / O2 ^* ) are selected in a time division manner and transmitted to a single sense amplifier 4.

The sense amplifiers 4 are installed by the number of groups (that is, four). Further, the number of latch circuits 6 (that is, two) corresponding to the number of regions belonging to one group is connected to the output side of each sense amplifier 4. A signal line A and a signal line A1 on the output side of the delay circuit 3 connected to the signal line A are connected to the two latch circuits 6 connected to each sense amplifier 4. The signals on these signal lines A and A1 function as clock pulses for each latch circuit 6.

Eight buffer circuits 7 are individually connected to the output side of the latch circuits 6 provided with eight devices 102 as a whole. Then, the data signals D1 to D8 held by the eight latch circuits 6 are input to the buffer circuit 7,
It is temporarily stored in the buffer circuit 7. The data signals D1 to D8 accumulated in the buffer circuit 7 are simultaneously read out in parallel to the outside. That is, the device 102, like the device 101, is configured to be able to read 8-bit signals simultaneously in parallel.

FIG. 7 is a timing chart showing changes in signals on the respective signal lines during the read operation of the device 102. As shown in FIG. 7, data signals I / O1 and I / O1 ^* are applied to eight pairs of transmission gates 16 and 17 ^.
While I to O8 and I / O8 ^* are input, the control signal propagates from the signal line A to the signal line A1 with a delay of Td.

While the active level control signal is being sent to the signal line A, the data signals D1, D3, D5 and D7 are accumulated in the buffer circuit 7 with some delay from the rising timing. Similarly, while the active level control signal is being sent to the signal line A1, the data signals D2, D4, D6 and D8 are accumulated in the buffer circuit 7 with a similar delay.

Also in the device 102, it is desirable that the pulse width of the control signal sent to the signal line A is set so as to substantially match the delay time Td. At this time, the time required to capture all the eight data signals D1 to D8 into the eight buffer circuits 7 is the shortest.

As described above, in the device 102, the area B1
B8 are grouped into four groups, two of which belong to each group, and the transmission of the data signal from the transmission gates 16 and 17 belonging to each group to the latch circuit 6 is serially performed in a time division manner. To be done.
As a result, the number of sense amplifiers 4 is reduced to half that of the conventional device 150 while maintaining simultaneous 8-bit parallel output to the outside.

As a result, the size of the device is reduced and the current consumption is reduced. In particular, the peak current is significantly reduced to about 1/2 of that of the conventional device 150. As a result, electrical noise is significantly reduced, and operational stability and device reliability are improved. Further, compared with the device 101, the current consumption is somewhat increased, but the time required to store the data signals D1 to D8 in all the buffer circuits 7 is shortened to about 1/4. There is an advantage that the delay time required until the data signals D1 to D8 can be output to the outside is shortened.

<3. Modified Example> (1) In the second embodiment, the regions B1 to B8 are conceptually divided into groups to which two each belong, and two pairs of transmission gates 16 and 17 belonging to each group are set to one. It was commonly connected to the individual sense amplifiers 4. Generally, areas B1 to B8 are divided into groups so that a plurality of areas (for example, four areas) belong to each group, and a plurality of pairs of transmission gates 16 and 17 are included in one group. Amplifier 4
Connected to.

That is, the degree of multiplexing of data signals passing through the sense amplifier 4 (multiplicity) can be arbitrarily selected. That is, considering the effect of reducing the consumption current, which is in a trade-off relationship with each other, in particular, the effect of reducing the peak current, and the saving of the delay time until all the data signals D1 to D8 can be output, depending on the application. It is recommended to select an appropriate multiplicity.

(2) First and Second Embodiments and Modifications
In (1), the example in which the data signals output simultaneously in parallel are 8 bits has been taken up. Needless to say, however, generally, the data signals output in parallel at the same time may have a plurality of bits, that is, 2 bits or more. That is, in general, M (M ≧
2) Grouping into J (= M / L) groups so that bit data signals are simultaneously output in parallel and L (2 ≦ L ≦ M) pairs of transmission gates 16 and 17 belong to each group. Should be done. This L is above
This corresponds to the multiplicity described in (1). The peak current is about 1 / L as compared with the conventional device 150.

(3) In the first and second embodiments, the SRAM is taken as an example. However, the present invention can be applied to general semiconductor memory devices including a DRAM, a ROM, etc., which simultaneously output a plurality of bits of data signals in parallel and have a sense amplifier.

[0057]

In the device according to the first aspect of the invention, the L switch circuits belonging to each group are supplied with the pulsed control signals so as to be sequentially delayed, so that the L switch circuits are commonly connected. L data signals are serially input to one sense amplifier. Since the pulsed clock signals are sequentially delayed and supplied to the L latch circuits commonly connected to the output of one sense amplifier, the L serial circuits amplified by one sense amplifier are supplied. 1 of each data signal is individually held in the L latch circuits. Therefore, it is possible to output M data signals in parallel.

That is, by multiplexing the data signals passing through the sense amplifiers by the switch circuit at the multiplicity L and demultiplexing them by the latch circuit, the number of sense amplifiers can be reduced while maintaining the simultaneous parallel output of M bits. The number of devices is reduced from M to M / L. For this reason, the area of the semiconductor chip occupied by the sense amplifier is reduced, so that the manufacturing cost can be reduced and the device can be downsized.

Further, since the current consumed by the sense amplifier is reduced, the average current consumption of the device is reduced and at the same time,
Particularly, the peak current is greatly reduced to about 1 / L as compared with the conventional device. For this reason, electrical noise is suppressed to a low level, so that operational stability and device reliability are improved.
Further, since the delay circuit is used, the sequentially delayed control signal and clock signal can be obtained by a simple circuit configuration which is easy to manufacture and has a small occupied area.

In the device of the second invention, since the pulse width of the signal generated by the control signal generation circuit is substantially equal to the delay time defined by the delay circuit, data can be simultaneously output from M latches in parallel. The time required to achieve this is most saved under the condition that the multiplicity L is constant.

In the device of the third invention, since L = M, one sense amplifier is sufficient. Therefore, the effect of reducing the size of the device, the effect of reducing the peak current, and the effect of reducing the electrical noise can be most remarkably obtained.

In the device of the fourth aspect of the invention, since the delay time is defined by the on-resistances of the plurality of transistors and the capacitive element which form the first stage inverter circuit, the number of these plurality of transistors and the capacitance of the capacitive element are determined. The adjustment provides the desired delay time. For this reason, the number of stages of inverters that require wiring for mutual connection is sufficient, so that the area occupied by the delay circuit in the semiconductor chip can be saved. That is, the miniaturization of the device is further enhanced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of a device according to a first embodiment.

FIG. 2 is a circuit diagram of a control signal generation circuit of the device of FIG.

3 is a circuit diagram of a delay circuit of the device of FIG.

4 is a circuit diagram of a latch circuit of the device of FIG.

5 is a timing chart showing the operation of the apparatus of FIG.

FIG. 6 is a circuit diagram of a main part of the device according to the second embodiment.

7 is a timing chart showing the operation of the apparatus shown in FIG.

FIG. 8 is a circuit diagram showing a main part of a conventional device.

[Explanation of symbols]

3 delay circuits, 4 sense amplifiers, 16 and 17 transmission gates (switch circuits), 29 control signal generation circuits, 30 capacitance elements, 31 PMOS transistors, 32 NMOS transistors, 36 and 37 inverter circuits, MC memory cells.

Claims (4)

[Claims] 1. A semiconductor memory device capable of simultaneously outputting in parallel a data signal of M (M ≧ 2) bits read from a memory cell and amplified by a sense amplifier, and read from the memory cell. M switch circuits for receiving the M data signals generated and transmitting the M data signals to the sense amplifier in response to a control signal are interposed between the memory cell and the sense amplifier. The switch circuit is conceptually divided into J (= M / L) groups to which L (2 ≦ L ≦ M) units belong, and the sense amplifier corresponds to each 1 of the J groups. One switch is provided for each of the J groups, and L switch circuits belonging to each of the J groups are commonly connected to the input side of the corresponding one sense amplifier. The output side of A latch circuit for holding the output of the sense amplifier in response to a clock signal is connected in common to each one of the sense amplifiers, and a control signal generation circuit for generating a pulse signal and a cascade connection thereof are provided. And at least L-1 delay circuits connected to each other, the control signals of the L switch circuits belonging to each 1 of the J groups, and the L latches connected to each 1 of the sense amplifiers. A semiconductor memory device, wherein a clock signal of a circuit is supplied so as to be sequentially delayed from one of L pieces to the other. 2. The semiconductor memory device according to claim 1, wherein the pulse width of the signal generated by the control signal generation circuit is substantially equal to the delay time in the delay circuit. 3. The semiconductor memory device according to claim 1 or 2, wherein L = M. 4. The semiconductor memory device according to claim 1, wherein the delay circuit includes two cascaded inverter circuits, a signal line connecting them, and a constant potential. A capacitive element interposed between the line and a line, wherein the first stage of the two-stage inverter circuit has a plurality of PMOS transistors and a plurality of NMOS transistors connected in a complementary manner. The plurality of PMOS transistors are connected in series with each other, and the plurality of NMOs are connected to each other.
A semiconductor memory device characterized in that S transistors are also connected in series with each other.