JPH09198110A - Optimization method for ladder sequence circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the optimization of a ladder sequence circuit by extracting an output element out of an extracted ladder sequence circuit, searching for the block of the ladder sequence circuit having the same output element as the extracted one out of an assembled ladder sequence circuit, and rewriting both ladder sequence circuits having the same output element into an output element common circuit. SOLUTION: A B block including an output coil YOOO is called out and both output coils YOOO of the B block and a taken-out A block are compared with each other if the B block does not reach the end of a file. When no coincidence is confirmed between both coils, the integration of output logic is impossible. Thus the next instruction block including a coil Y000 is called out. On the other hand, the integration of output logic is possible when the coincidence is confirmed between both output coils. Then the input system logic of both output coils are connected together via an OR and the A block is rewritten into a new instruction YOOO with deletion of the B block instruction. As a result, both output coils of A and B blocks can be integrated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, for example, creates a new program by combining existing modularized programs (ladder sequence circuits), or modifies an existing program, and then executes these programs. The present invention relates to an optimization method of a ladder sequence circuit to be optimized.

[0002]

2. Description of the Related Art A sequencer is used to control a small-scale production machine to a large-scale production machine. Input elements such as various sensors and switches and output elements such as motors and solenoids are connected to this sequencer. In a large-scale production machine, the number of input elements and output elements becomes enormous.

Generally, a sequencer includes a ladder sequence circuit that associates an input element with an output element. This ladder sequence circuit is generally created by a designer inputting one element at a time while operating an input device, or by combining ladder sequence circuits that are modularized and stored in existing equipment.

[0004]

When creating a new sequence circuit, for a relatively small-scale production machine,
It is possible to build a ladder sequence circuit by inputting one element at a time while looking at the ladder diagram created in advance, but in a large-scale production machine, since the number of input / output elements is enormous as described above, Since the ladder sequence circuit also becomes complicated and the method of inputting one element at a time is inefficient, in such a case, as shown in FIG. 12, a new ladder sequence circuit is combined by combining modularized ladder sequence circuits. Create a sequence circuit. That is, a ladder sequence circuit is created by a method of taking out modules from the standard ladder sequence 1 and the standard ladder sequence 2 stored in two types of equipment and synthesizing the extracted modules.

According to such a method, it is certainly possible to efficiently create a ladder sequence circuit,
Since the ladder sequence circuit is assembled simply by the operation of synthesis, the ladder sequence circuit after synthesis contains logic inconsistency or logic duplication occurs, which causes the machine to make unintended movements or runaway. Or, on the contrary, it may become stuck or the operation speed may decrease. In addition, such a problem may be a problem even when a large-scale production machine is modified.

In order to avoid such a problem in advance, it is necessary to complete the assembled ladder sequence circuit. It is necessary to debug on a desk or actually operate the production machine to obtain a desired movement. However, it is difficult for humans to perform complete debugging, especially debugging of unnecessary logics whose logics are duplicated. In addition, it takes a long time to perform a complete debugging, and the merit of the module synthesis in which the ladder sequence circuit is easily assembled is halved. Note that such a problem also occurs when a large-scale change is made to the existing ladder sequence circuit.

The present invention has been made in order to solve such a conventional problem, and provides a method for optimizing a ladder sequence circuit that can automatically optimize a ladder sequence circuit after it has been created. With the goal.

[0008]

The present invention for achieving the above object is constituted by the following means.

First, the invention according to claim 1 is characterized in that the rule of contact combination is applied to the assembled ladder sequence circuit to automatically correct the logical duplication of the ladder sequence circuit. This is a circuit optimization method.

Applying this contact combination law,
It is easier to correct logic errors such as logic inconsistency of the assembled ladder sequence circuit compared to the conventional method (because the ladder sequence circuit after optimization is composed of the minimum number of logic elements), It will be possible to complete the debugging process, and simplification of duplicate logic will be done automatically and reliably.
It is possible to configure the ladder sequence circuit from the minimum necessary number of logical elements, and it is possible to always set the work speed of the production machine to be controlled to the maximum speed possible.

According to a second aspect of the present invention, one block of the ladder sequence circuit is extracted from the assembled ladder sequence circuit, an output element is extracted from the extracted ladder sequence circuit, and the extracted output element is A ladder sequence circuit block having the same output element is searched from the assembled ladder sequence circuit, and the ladder sequence circuits having the same output element are rewritten to a circuit having the same output element. This is an optimization method for a ladder sequence circuit. According to this method, the number of duplicate output elements existing in the ladder sequence circuit can be reduced, so that the processing speed can be improved and the working speed of the production machine can be afforded. Will be able to.

According to a third aspect of the present invention, one block of the ladder sequence circuit is extracted from the assembled ladder sequence circuit, the input logic element included in the extracted ladder sequence circuit is extracted, and the extracted. A circuit in which a block of a ladder sequence circuit having the same input logic element as the input logic element is searched from the assembled ladder sequence circuit, and the ladder sequence circuits having the same input logic element share the input logic element. It is a method of optimizing a ladder sequence circuit, which is characterized by rewriting to. According to this method, it is possible to reduce the number of duplicated input logic elements included in the ladder sequence circuit, so that the processing speed can be improved and the working speed of the production machine can be afforded. Will be able to.

According to a fourth aspect of the present invention, one block of the ladder sequence circuit is extracted from the assembled ladder sequence circuit, the input logic element included in the extracted ladder sequence circuit is extracted, and the extracted. A ladder sequence circuit block having the same input logic element as the input logic element is searched from the assembled ladder sequence circuit, and a new ladder sequence circuit block having the same input logic element is created, and the same ladder logic circuit block is created. A ladder sequence circuit optimization method is characterized in that a ladder sequence circuit block having an input logic element is replaced with a new ladder sequence circuit block. According to this method, it is possible to reduce the number of duplicated input logic elements included in the ladder sequence circuit, so that the processing speed can be improved and the working speed of the production machine can be afforded. Will be able to.

According to a fifth aspect of the present invention, one block of the ladder sequence circuit is extracted from the assembled ladder sequence circuit, and the ladder sequence circuit of the same type as the extracted one block of the ladder sequence circuit is used. From the assembled ladder sequence circuit, create a new ladder sequence circuit subroutine block from both blocks of the same type ladder sequence circuit, and add both blocks of the same type of ladder sequence circuit to the new block. It is a method for optimizing a ladder sequence circuit, characterized in that it is replaced with a subroutine block of the ladder sequence circuit. According to this method, the number of duplicated logic elements included in the ladder sequence circuit can be drastically reduced, so that the processing speed can be improved and the working speed of the production machine can be afforded. Will be able to.

[0015]

According to the ladder sequence circuit optimizing method of the present invention having the above-described structure, the following effects can be obtained.

(1) Effects common to the inventions described in claims 1 to 5 By optimizing the ladder sequence circuit by the method described in each claim, a logic contradiction is eliminated. It will be easier to find and debugging will be more efficient. Further, since it is possible to surely eliminate the logic duplication, the size of the ladder sequence circuit (program size) can be minimized, and the processing speed can be improved.

(2) Effects peculiar to each invention described in claims 1 to 5 In the invention described in claim 1, inconsistent logic is searched out from the entire ladder sequence circuit. , Since overlapping logic can be integrated, fine-tuned optimization can be performed.

According to the second aspect of the present invention, since all the output elements of the ladder sequence circuit can be integrated, it is possible to configure the ladder sequence circuit with the minimum necessary output elements. .

According to the third aspect of the invention, since the ladder sequence circuit can be integrated for each input element (consisting of a plurality of logics), optimization can be performed for each input element. it can.

According to the invention of claim 4, since the ladder sequence circuit can be integrated in block units of input elements (composed of a plurality of logics), optimization in block units is required. You can

According to the fifth aspect of the present invention, since the ladder sequence circuit can be integrated by making it into a subroutine for each block of input / output elements (consisting of a plurality of logics), it can be integrated for each block. Can be optimized.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

The method of the present invention minimizes the size of the ladder sequence circuit by using the following rules of contact combination such as output logic integration processing, input logic integration processing, partial block replacement processing, and subroutine processing. It is intended to improve the speed of.

FIG. 1 is a diagram showing a schematic configuration of an apparatus for realizing the method of the present invention.

The sequencer 10 shown in the drawing controls the operation of a production machine (not shown), and stores a ladder sequence circuit for controlling the operation. The I / O 12 mediates exchange of signals between the sequencer 10 and input / output elements (input elements such as various sensors and switches, output elements such as motors and solenoids).

Ladder sequence programming terminal 14
Is a function of inputting the ladder sequence circuit before the optimization processing stored in the sequencer 10 and outputting it to the ladder sequence programming optimization terminal 16, and the optimization processing performed by the ladder sequence programming optimization terminal 16. It has a function of inputting the ladder sequence circuit after being broken and returning it to the sequencer.

The ladder sequence programming optimization terminal 16 is the terminal on which the method of the present invention is actually carried out. That is, here, as shown in the flowchart of FIG.
Output logic integration processing (S1), input logic integration processing (S
2), the partial block replacement process (S3), and the subroutine process (S4) are performed in this order for the optimization process of the ladder sequence circuit.

The processing procedure of the above four processing will be described in detail below.

The output logic integration processing shown in the flowchart of FIG. 3 is an embodiment corresponding to claim 2.

An example of this processing will be described with reference to the ladder sequence circuit of FIG.

The ladder sequence programming optimization terminal 16 opens the input file of the ladder sequence circuit before the optimization processing (S11), and calls an instruction block including an output coil which is an output element. In the circuit of FIG. 5A, the block A including the output coil [Y000] is called (S12). If the end of the file has not been reached (S13), the next instruction block including the output coil is called, and if the end of the file has been reached, there is no need to call any more, so the file is closed (S20). In the circuit of FIG. 5A, the block B including the output coil [Y000] is called (S14). If the end of the file has not been reached (S15), the extracted output coils of the A block and B block are compared (S16). In the circuit of FIG. 5A, the output coil [Y000] of the A block is compared with the output coil [Y000] of the B block.

As a result of this comparison, if they are not equal, the output logics cannot be integrated, so that the next instruction block including the output coil is called. On the other hand, as a result of this comparison, if it is determined that they are equal, the output logics can be integrated. Therefore, the input system logics connected to both output coils are connected by OR, and the A block is given a new command. Rewrite as ([Y000]) and delete the instruction on the B block side. By this processing, the output coils of both A and B blocks can be integrated. In the circuit of FIG. 5A, since both output coils are equal to [Y000], the logic of the input system on the A block side is connected with the logic of the input system on the B block side by OR, and Output coil [Y0
00] is deleted (S17 to S19). By this processing, the common output coil existing in the two blocks can be integrated, and the output coil is simplified as shown in FIG.

The input logic integration processing shown in the flowchart of FIG. 4 is an embodiment corresponding to claim 3.

An example of this processing will be described with reference to the ladder sequence circuit of FIG.

The ladder sequence programming optimization terminal 16 opens the input file of the ladder sequence circuit before the optimization processing (S21), and calls an instruction block including an output coil which is an output element. In the circuit of FIG. 6A, the block A including the output coil [Y001] is called (S22). If the end of the file has not been reached (S23), the next instruction block including the output coil is called, and if the end of the file has been reached, there is no need to call any more, so the file is closed (S31). In the circuit of FIG. 6A, the block B including the output coil [Y002] is called (S24). If the end of the file has not been reached (S25), the logic of the input system, which is the input logic element of the extracted A block and B block, is compared (S26).
In the circuit of FIG. 6A, the logics of the input systems of the A block and the B block are compared in every combination.

In this comparison, if there is no logic that can be integrated (invalid), the input logic cannot be integrated, and the next instruction block including the output coil is called. On the other hand, as a result of this comparison, if there is a logic that can be integrated (if it is valid), it is possible to integrate the input logic. , The input logic that can be integrated is integrated, and the A block is given a new command ([Y001], [Y00
2]), and the instruction ([Y00
2]) is deleted. By this processing, the input logic of both A and B blocks can be integrated. In the circuit of FIG. 6A, among the logics of the input system, [X001], [X00
2] and [X003] can be integrated (can be replaced by one input logic), the input logic is integrated in the A block as shown in FIG. Output coil of [Y001]
To [Y001] and [Y002] to delete the output coil [Y002] on the B block side (S27).
~ S30). By this processing, the common input logic existing in the two blocks can be integrated, and the input logic is simplified as shown in FIG.

The partial block replacement process shown in the flowchart of FIG. 7 is an embodiment corresponding to claim 4.

An example of this processing will be described with reference to the ladder sequence circuit of FIG.

The ladder sequence programming optimization terminal 16 opens the input file of the ladder sequence circuit before optimization processing (S41) and calls an instruction block including an output coil which is an output element. In the circuit of FIG. 8A, the block A including the output coil [Y000] is called (S42). If the end of the file has not been reached (S43), the next command block including the output coil is called. In the circuit of FIG. 8 (A),
The block B including the output coil [Y001] is called (S44). If the end of the file has not been reached (S45), whether the same block or a block to be the C block described later exists from the input system logic that is the input logical elements of the A block and the B block that have been taken out. Is searched (S46). FIG.
In the circuit (A), whether or not the same block exists in the logic of the input system of the A block and the B block is searched by considering all combinations.

In this search, if there is no replaceable block (invalid), the block cannot be replaced, and the next instruction block including the output coil is called. On the other hand, as a result of this search, if a replaceable block exists (if valid), the block can be replaced. Therefore, the replaceable block is copied as a C block and the B block is buffered. After that, the B block is deleted (S47 to S50). In the circuit of FIG. 8A, [X002], [X003], [X004],
Since the block composed of the input logical element of [X005] is common to both A and B blocks and can be replaced, this block is copied as a C block, the B block is stored in the buffer, and the B block is deleted. To do.

When the above processing is repeated until the end of the file, an intermediate coil is added to the C block created assuming that the file can be replaced (S51, S52), and the A block is stored in the buffer. The replacement process is executed and the file is closed (S53, S54).
In the circuit of FIG. 8 (A), the input logic element [X
002], [X003], [X004], [X005]
Since the replacement block composed of can be replaced by both A and B blocks, as shown in FIG. 6 (B), first, an intermediate coil [M000] is added to this block to create the A block. The replacement block of the B block is replaced with the contact of the intermediate coil to create the C block, and the replacement block of the old A block is replaced with the contact of the intermediate coil to create the B block. By this processing, the common partial blocks existing in the two blocks can be integrated, and the circuit has a simplified input logic as shown in FIG.

The subroutine processing shown in the flowchart of FIG. 9 is an embodiment corresponding to claim 5.

An example of this processing will be described with reference to the ladder sequence circuits of FIGS.

The ladder sequence programming optimization terminal 16 opens the input file of the ladder sequence circuit before the optimization processing (S61) and calls an instruction block including an output coil which is an output element. In the circuit of FIG. 10, block A containing the output coil [E200]
Will be called (S62). If the end of the file has not been reached (S63), the next command block including the output coil is called. In the circuit of FIG. 10, the block B including the output coil [E201] is called (S64). If the end of the file is not reached (S65), the instruction types of the fetched A block and B block are compared, and if the instruction types are the same, the parameters for integrating both blocks are determined (S66, S6).
7). Taking the circuit of FIG. 10 as an example, comparing the A block and the B block, it can be seen that the configurations of the input logic elements for operating the output coils are exactly the same, and the contact numbers thereof are simply different. . That is, it can be seen that the instruction types are the same. In such a case, since there is a possibility that both blocks can be integrated, the parameters are determined. In other words, if attention is paid to the contact number, there is regularity between both blocks, so as shown in FIG.
Determine a parameter such as% 1 + α.

It is checked whether the parameters thus determined are valid (S68). In this way, the validity check is performed, for example, in B block 1
This is because when the number of one input contact is a unique number, it may not be possible to integrate both blocks with the determined parameters. If the parameters are judged to be valid in this validity check, it is possible to make a subroutine, so a subroutine as shown in FIG. 11A is created and the subroutine as shown in FIG. The replacement is performed (S69, S70). By performing such processing, the size of the ladder sequence circuit can be drastically reduced.

The ladder sequence programming optimizing terminal 16 that has completed the above-mentioned processing is the ladder sequence programming terminal 14 after the optimized ladder sequence circuit.
The ladder sequence circuit from the ladder sequence programming terminal 14 is input to the sequencer 10, and thereafter, the operation of the production machine is controlled by the optimized ladder sequence circuit.

As described above, common output logic is integrated by output logic integration processing, common input logic is integrated by input logic integration processing, output logic and input logic are integrated, and partial block replacement is performed. Depending on the processing, the input integration that cannot be integrated by the processing is partially integrated, and the overall integration including the input / output logic is performed by the subroutine processing so that the modules are simply combined. Even with the created ladder sequence circuit, logical duplication can be removed efficiently and reliably, and a ladder sequence program with a minimum size can be reconfigured.

The above output logic integration processing, input logic integration processing, partial block replacement processing, and subroutine processing can be applied individually, but the same effect can be obtained, but preferably all processing is applied. Preferably.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an apparatus for executing the method of the present invention.

FIG. 2 is a main flow chart of the method of the present invention.

FIG. 3 is a flowchart showing an output logic integration process.

FIG. 4 is a flowchart showing an input logic integration process.

5A and 5B are diagrams for explaining a specific example of output logic integration processing, in which FIG. 5A shows a ladder sequence circuit before processing and FIG. 5B shows a ladder sequence circuit after processing.

6A and 6B are diagrams for explaining a specific example of input logic integration processing, in which FIG. 6A shows a ladder sequence circuit before processing and FIG. 6B shows a ladder sequence circuit after processing.

FIG. 7 is a flowchart showing a partial block replacement process.

8A and 8B are diagrams illustrating a specific example of partial block replacement processing, in which FIG. 8A shows a ladder sequence circuit before processing and FIG. 8B shows a ladder sequence circuit after processing.

FIG. 9 is a flowchart showing a subroutine process.

FIG. 10 is a diagram for explaining a specific example of the subroutine processing, showing a ladder sequence circuit before processing.

11A and 11B are diagrams for explaining a specific example of the subroutine processing, in which FIG. 11A is used for parameter determination, and FIG. 11B shows a ladder sequence circuit after processing.

FIG. 12 is a diagram for explaining a conventional method of creating a ladder sequence circuit.

[Explanation of symbols]

 10 ... Sequencer, 12 ... I / O, 14 ... Ladder sequence programming terminal, 16 ... Ladder sequence programming optimization terminal.

Claims (5)

[Claims] 1. A method for optimizing a ladder sequence circuit, which is characterized by applying the law of contact combination to the assembled ladder sequence circuit and automatically correcting the logic duplication of the ladder sequence circuit. 2. A ladder having one block of the ladder sequence circuit extracted from the assembled ladder sequence circuit, extracting an output element from the extracted ladder sequence circuit, and having the same output element as the extracted output element. A method of optimizing a ladder sequence circuit, wherein a block of a sequence circuit is searched from the assembled ladder sequence circuit, and the ladder sequence circuits having the same output element are rewritten into a circuit having the same output element. . 3. A ladder sequence circuit of one block is extracted from the assembled ladder sequence circuit, an input logic element included in the extracted ladder sequence circuit is extracted, and the same input as the extracted input logic element is extracted. A ladder sequence circuit block having a logic element is searched from the assembled ladder sequence circuit, and the ladder sequence circuits having the same input logic element are rewritten into a circuit having the same input logic element. Ladder sequence circuit optimization method. 4. A ladder sequence circuit of one block is extracted from the assembled ladder sequence circuit, an input logic element included in the extracted ladder sequence circuit is extracted, and the same input as the extracted input logic element is extracted. A ladder sequence circuit block having a logic element is searched for in the assembled ladder sequence circuit, a new ladder sequence circuit block having the same input logic element is created, and the ladder sequence having the same input logic element is created. A method of optimizing a ladder sequence circuit, characterized in that a block of the circuit is replaced with a block of the new ladder sequence circuit. 5. A ladder sequence circuit of one block is extracted from the assembled ladder sequence circuit, and a block of the ladder sequence circuit of the same type as the extracted one block ladder sequence circuit is formed into the assembled ladder sequence. Find out from the circuit, create a subroutine block of a new ladder sequence circuit from both blocks of the same type of ladder sequence circuit, and make both blocks of the same type of ladder sequence circuit a subroutine block of the new ladder sequence circuit. A method for optimizing a ladder sequence circuit, characterized in that