JPH09195068A - Lead frame, method for partially plating lead frame with noble metal and semiconductor device formed by using the lead frame - Google Patents
Lead frame, method for partially plating lead frame with noble metal and semiconductor device formed by using the lead frameInfo
- Publication number
- JPH09195068A JPH09195068A JP8055316A JP5531696A JPH09195068A JP H09195068 A JPH09195068 A JP H09195068A JP 8055316 A JP8055316 A JP 8055316A JP 5531696 A JP5531696 A JP 5531696A JP H09195068 A JPH09195068 A JP H09195068A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- lead frame
- copper
- silver
- thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000007747 plating Methods 0.000 title claims abstract description 389
- 239000004065 semiconductor Substances 0.000 title claims abstract description 107
- 238000000034 method Methods 0.000 title claims abstract description 96
- 229910000510 noble metal Inorganic materials 0.000 title claims abstract description 86
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 174
- 229910052709 silver Inorganic materials 0.000 claims abstract description 174
- 239000004332 silver Substances 0.000 claims abstract description 174
- 239000010949 copper Substances 0.000 claims abstract description 101
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 91
- 229910052802 copper Inorganic materials 0.000 claims abstract description 91
- 229910000881 Cu alloy Inorganic materials 0.000 claims abstract description 85
- 239000011347 resin Substances 0.000 claims abstract description 75
- 229920005989 resin Polymers 0.000 claims abstract description 75
- 238000007789 sealing Methods 0.000 claims abstract description 68
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims abstract description 48
- 239000000463 material Substances 0.000 claims abstract description 48
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 31
- 239000000956 alloy Substances 0.000 claims abstract description 29
- 229910052737 gold Inorganic materials 0.000 claims abstract description 26
- 239000010931 gold Substances 0.000 claims abstract description 26
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 20
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 13
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 67
- 239000010970 precious metal Substances 0.000 claims description 61
- 239000005751 Copper oxide Substances 0.000 claims description 56
- 229910000431 copper oxide Inorganic materials 0.000 claims description 56
- 238000009713 electroplating Methods 0.000 claims description 15
- 238000007772 electroless plating Methods 0.000 claims description 13
- 238000004833 X-ray photoelectron spectroscopy Methods 0.000 claims description 7
- 230000008569 process Effects 0.000 abstract description 41
- 238000004519 manufacturing process Methods 0.000 abstract description 25
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000006735 deficit Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 105
- 230000032798 delamination Effects 0.000 description 48
- 239000000243 solution Substances 0.000 description 18
- 230000000694 effects Effects 0.000 description 16
- 230000004048 modification Effects 0.000 description 15
- 238000012986 modification Methods 0.000 description 15
- 230000000052 comparative effect Effects 0.000 description 14
- 238000010438 heat treatment Methods 0.000 description 14
- 239000002585 base Substances 0.000 description 12
- 230000000873 masking effect Effects 0.000 description 12
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 10
- 239000002253 acid Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 8
- 238000000576 coating method Methods 0.000 description 8
- 238000004070 electrodeposition Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 230000002265 prevention Effects 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000012937 correction Methods 0.000 description 6
- 238000002845 discoloration Methods 0.000 description 6
- 238000004649 discoloration prevention Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 230000009471 action Effects 0.000 description 4
- 230000004913 activation Effects 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000007864 aqueous solution Substances 0.000 description 4
- QRUDEWIWKLJBPS-UHFFFAOYSA-N benzotriazole Chemical compound C1=CC=C2N[N][N]C2=C1 QRUDEWIWKLJBPS-UHFFFAOYSA-N 0.000 description 4
- 239000012964 benzotriazole Substances 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- 238000005238 degreasing Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000011156 evaluation Methods 0.000 description 4
- 230000033444 hydroxylation Effects 0.000 description 4
- 238000005805 hydroxylation reaction Methods 0.000 description 4
- 238000006467 substitution reaction Methods 0.000 description 4
- 238000004381 surface treatment Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000010953 base metal Substances 0.000 description 2
- 239000007767 bonding agent Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 230000010485 coping Effects 0.000 description 2
- DOBRDRYODQBAMW-UHFFFAOYSA-N copper(i) cyanide Chemical compound [Cu+].N#[C-] DOBRDRYODQBAMW-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 229910000833 kovar Inorganic materials 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000006386 neutralization reaction Methods 0.000 description 2
- 125000001741 organic sulfur group Chemical group 0.000 description 2
- 238000005554 pickling Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- LFAGQMCIGQNPJG-UHFFFAOYSA-N silver cyanide Chemical compound [Ag+].N#[C-] LFAGQMCIGQNPJG-UHFFFAOYSA-N 0.000 description 2
- 229940098221 silver cyanide Drugs 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 238000010301 surface-oxidation reaction Methods 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
Classifications
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- H—ELECTRICITY
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- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
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Abstract
Description
【０００２】[0002]
【従来の技術】従来より、半導体装置の組立部材として
用いられる（単層）リードフレームは、通常、コバー
ル、４２合金（４２％ニッケル−鉄合金）、銅系合金の
ような金属から成り、プレス法もしくはエッチング法に
より形成されていた。一般的なプラスチックパッケージ
であるＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）
用のリードフレームは、図７（ｂ）（イ）に示すよう
に、半導体素子を搭載するためのダイパッド７１１と、
ダイパッド７１１の周囲に設けられた半導体素子と結線
するためのインナーリード７１２と、該インナーリード
７１２に連続して外部回路との結線を行うためのアウタ
ーリード７１３、樹脂封止する際のダムとなるダムバー
７１４、リードフレーム７１０全体を支持するフレーム
（枠）部７１５等を備えている。そして、リードフレー
ム７１０は、図７（ａ）に示すように、ダイパッド部７
１１をインナーリード７１２形成面よりもダウンセット
した状態でダイパッド７１１に半導体素子７２０を搭載
し、半導体素子７２０の電極パッド（端子）７２１とイ
ンナーリード７１２の先端部とを金などのワイヤ７３０
で結線を行った後に、樹脂７４０にて封止して、ダムバ
ー７１４部の切断工程、アウターリード７１３部のフオ
ーミング工程を経て半導体装置７００を作製していた。
尚、図７（ｂ）（ロ）は、図７（ｂ）（イ）のＦ１−Ｆ
２における断面図である。2. Description of the Related Art Conventionally, a (single layer) lead frame used as an assembly member of a semiconductor device is usually made of a metal such as Kovar, 42 alloy (42% nickel-iron alloy), and copper alloy. It was formed by the etching method or the etching method. QFP (Quad Flat Package) which is a general plastic package
The lead frame for use has a die pad 711 for mounting a semiconductor element, as shown in FIGS.
Inner leads 712 for connecting to a semiconductor element provided around the die pad 711, outer leads 713 for connecting to an external circuit continuously to the inner leads 712, and a dam for resin sealing The dam bar 714, a frame (frame) portion 715 for supporting the entire lead frame 710, and the like are provided. Then, the lead frame 710, as shown in FIG.
The semiconductor element 720 is mounted on the die pad 711 in a state where 11 is set down from the surface on which the inner lead 712 is formed, and the electrode pad (terminal) 721 of the semiconductor element 720 and the tip of the inner lead 712 are connected to the wire 730 such as gold.
The semiconductor device 700 was manufactured through the step of cutting the dam bar 714 and the forming step of the outer lead 713 after sealing with the resin 740.
7 (b) and (b) are F1-F of FIG. 7 (b) (a).
It is sectional drawing in 2.
【０００３】このようなリードフレームは、半導体素子
７２０の電極パッド（端子）７２１とインナーリード７
１２の先端部とを金などのワイヤ７３０でワイヤボンデ
ィング（結線）、半導体素子の搭載の際に、強い結合力
と導電性を確保するために、貴金属めっきを、少なくと
もインナーリード７１２先端部、ダイパッド７１１の半
導体搭載側の面に施していた。貴金属めっきとしては、
銀めっき処理が一般には採られていた。Such a lead frame is composed of the electrode pad (terminal) 721 of the semiconductor element 720 and the inner lead 7.
The tip of 12 is wire-bonded with a wire 730 made of gold or the like, and at the time of mounting a semiconductor element, precious metal plating is applied to at least the tip of the inner lead 712 and the die pad in order to secure a strong bonding force and conductivity. It was applied to the semiconductor mounting side of 711. For precious metal plating,
A silver plating process was commonly used.
【０００４】従来のリードフレームにおいては、図６
（ａ）に示すように、ダイパッド１１１の半導体素子搭
載側とインナーリード１１２の先端部に、リードフレー
ム素材（銅合金）１２０上に、順に銅ストライクめっき
１４０、銀めっき１５０を形成しており、その部分銀め
っき工程は、図６（ｂ）に示すように、外形加工された
リードフレーム素材１２０に対し、脱脂、酸洗い等の前
処理（図６（ｂ）（イ））を行ってから、一般に下地め
っきとして０．１〜０．３μｍ厚程度の銅（Ｃｕ）スト
ライクめっきを施し（図６（ｂ）（ロ））、所望の領域
に１．５〜１０μｍ厚の銀めっきが施こした（図６
（ｂ）（ハ））後に、必要に応じて本来不要である部分
に薄くついた銀（モレなど）を除去する電解剥離処理を
してから、ベンゾトリアゾール系等の有機系薬品により
被膜を作り、酸化、水酸化による変色を防止する変色防
止処理（図６（ｂ）（ニ））を施すものであった。銀め
っき方法としては、マスキング治具を用いリードフレー
ムの所定領域を覆い露出部へ銀めっき液を吹きかけて部
分的に銀めっきを施す方法や、リードフレームに電着レ
ジストを塗膜した後、電着レジストを製版して所定の部
分のみ露出した状態でめっき液に浸漬してめっきを施す
方法等が用いられている。このように、マスキング治具
や電着レジストをマスクとしてリードフレームの所望の
部分にのみめっきを施すことを部分めっきと言ってお
り、図６に示す銀めっきのことを以下部分銀めっきと言
う。このような処理が施された銅合金を素材としたリー
ドフレームにおいては、半導体装置の作製工程や半導体
装置の実装工程においても、下地めっきが通常剥離する
ことはなく、半導体装置に使用された場合にも、銅スト
ライク部の剥離はないとされていた。FIG. 6 shows a conventional lead frame.
As shown in (a), a copper strike plating 140 and a silver plating 150 are sequentially formed on a lead frame material (copper alloy) 120 at the semiconductor element mounting side of the die pad 111 and the tip of the inner lead 112, In the partial silver plating step, as shown in FIG. 6B, after pretreatment such as degreasing and pickling (FIGS. 6B and 6B) is performed on the externally processed lead frame material 120. Generally, copper (Cu) strike plating having a thickness of about 0.1 to 0.3 μm is applied as a base plating (FIGS. 6B and 6B), and silver plating having a thickness of 1.5 to 10 μm is applied to a desired area. (Fig. 6
After (b) and (c)), if necessary, electrolytic stripping treatment is performed to remove the thin silver (more) that is originally not needed, and then a film is formed with an organic chemical such as benzotriazole. The discoloration preventing treatment (FIG. 6 (b) (d)) was performed to prevent discoloration due to oxidation and hydroxylation. As a silver plating method, a masking jig is used to cover a predetermined area of the lead frame to spray a silver plating solution on the exposed portion to partially perform silver plating, or after the lead frame is coated with an electrodeposition resist, an electrodeposition resist is applied. For example, a method is used in which a coating resist is made into a plate, and a predetermined portion is exposed so that the plating is dipped in a plating solution to perform plating. As described above, plating only on a desired portion of the lead frame using the masking jig or the electrodeposition resist as a mask is called partial plating, and the silver plating shown in FIG. 6 is hereinafter called partial silver plating. In the case of a lead frame made of a copper alloy that has been subjected to such a treatment, the base plating does not usually peel off even during the semiconductor device manufacturing process or the semiconductor device mounting process However, it was said that there was no peeling of the copper strike part.
【０００５】しかしながら、最近、このような処理が施
された銅合金を素材とするリードフレームを用いた場
合、リードフレームに起因したパッケージのデラミネー
ション（剥離）が半導体装置組み立て工程や実装工程で
生じていることが分かってきた。尚、パッケージのデラ
ミネーション（剥離）とは、ＩＣパッケージ内の各界
面、即ちＩＣチップ（半導体素子）と封止用樹脂との界
面、ダイボンディング剤とＩＣチップ（半導体素子）と
の界面等での剥離を言うが、リードフレームに起因する
デラミネーション（剥離）は封止用樹脂とダイパッド裏
面との界面での剥離等である。封止用樹脂とダイパッド
裏面との界面でのデラミネーション（剥離）の発生は、
銅合金を素材とするリードフレームの表面処理や組み立
て条件と密接な関係があることも次第に分かってきた。
銀めっきの下地めっきとして銅ストライクめっきが施こ
され、銀めっき後に電解剥離と変色防止が施された、銅
合金を素材とするリードフレームにおいては、ＩＣ（半
導体装置）組み立て工程中の加熱工程で、銅合金表面に
酸化膜が生じ、酸化膜と金属（銅合金）との間の密着強
度が不十分であることが、デラミネーション（剥離）発
生の原因と考えられている。However, recently, when a lead frame made of a copper alloy which has been subjected to such a treatment is used, delamination (peeling) of the package due to the lead frame occurs in a semiconductor device assembling process and a mounting process. I have come to understand that. The delamination of the package means each interface in the IC package, that is, the interface between the IC chip (semiconductor element) and the sealing resin, the interface between the die bonding agent and the IC chip (semiconductor element), and the like. The delamination caused by the lead frame is peeling at the interface between the sealing resin and the back surface of the die pad. The occurrence of delamination at the interface between the sealing resin and the back surface of the die pad
It has gradually become clear that there is a close relationship with the surface treatment and assembly conditions of lead frames made of copper alloy.
In a lead frame made of copper alloy, which has been subjected to copper strike plating as a base plating of silver plating, and electrolytic peeling and discoloration prevention have been applied after silver plating, the heating process during the IC (semiconductor device) assembly process It is considered that delamination occurs because an oxide film is formed on the surface of the copper alloy and the adhesion strength between the oxide film and the metal (copper alloy) is insufficient.
【０００６】このような状況のもと、封止用樹脂とダイ
パッド裏面との界面、さらには、封止用樹脂とリードフ
レーム全面との界面の接着強度を向上させ、デラミ発生
を防止するための方法として、特表平７−５０３１０３
号（特願平５−５１２６８８号）等が提案されている。
特表平７−５０３１０３号（特願平５−５１２６８８
号）では、クロムと亜鉛の混合体あるいはそれぞれの単
体からなる薄い被膜で全面を覆ったリードフレームが開
示されている。しかし、このリードフレームは、銀めっ
き部分も他の金属被膜で覆われるため、金ワイヤボンデ
ィング性が劣るという問題がある。Under these circumstances, the adhesive strength at the interface between the encapsulating resin and the back surface of the die pad, and further at the interface between the encapsulating resin and the entire surface of the lead frame is improved to prevent the occurrence of delamination. As a method, the special table 7-503103
Japanese Patent Application No. 5-512688 is proposed.
Japanese Patent Publication No. 7-503103 (Japanese Patent Application No. 5-512688)
No.) discloses a lead frame which is entirely covered with a thin film of a mixture of chromium and zinc or a simple substance of each. However, this lead frame has a problem that the gold wire bondability is poor because the silver-plated portion is also covered with another metal film.
【０００７】また、ＩＣ組み立て工程の条件は、組立を
実施するＩＣメーカーにより異なり、銅合金製リードフ
レームの表面酸化状態、酸化膜形成過程もメーカー毎に
異なる為、リードフレームに起因するデラミネーション
の発生状況がＩＣ組み立てメーカーによって異なってい
た。例えば、ベンゾトリアゾール系の被膜により、銅の
酸化、水酸化による変色を防止する処理方法では、ＩＣ
組み立て温度が低いメーカに対しては、デラミネーショ
ン防止効果が得られるが、ＩＣ組み立て温度が高いメー
カではデラミネーション防止効果が得られない。このた
め、従来はデラミネーションに対する対策をＩＣ組み立
て条件に合わせて各メーカ毎に行っていたのが実状で、
ＩＣの組み立て条件によらず、リードフレームに起因す
るデラミネーションに対応できる手段が求められてい
た。Further, the conditions of the IC assembling process differ depending on the IC maker who carries out the assembling, and the surface oxidation state of the copper alloy lead frame and the oxide film forming process also differ depending on the maker, so that delamination caused by the lead frame may occur. The occurrence situation was different depending on the IC assembly manufacturer. For example, in a treatment method for preventing discoloration due to copper oxidation or hydroxylation by a benzotriazole-based coating,
The delamination prevention effect can be obtained for a manufacturer whose assembly temperature is low, but the delamination prevention effect cannot be obtained for a manufacturer whose IC assembly temperature is high. For this reason, in the past, each manufacturer has taken measures against delamination according to the IC assembly conditions.
There has been a demand for means capable of coping with delamination caused by the lead frame, regardless of IC assembly conditions.
【０００８】[0008]
【発明が解決しようとする課題】このように、銅合金製
のリードフレームにおいては、リードフレーム表面の銅
酸化膜生成に起因した半導体装置（ＩＣ）におけるデラ
ミネーションを防止し、ＩＣの信頼性低下、ＩＣ組み立
て工程、実装工程における良品率の低下を防止すること
が望まれており、特に、ＩＣの組み立て条件によらず、
リードフレームに起因するデラミネーションの発生を防
止できるものが求められていた。本発明は、このような
状況のもと、ＩＣの組み立て条件によらず、リードフレ
ーム表面の銅酸化膜生成に起因したデラミネーションの
発生を防止でき、且つ、ボンディング性を損なわない銅
合金製のリードフレームを提供しようとするものであ
る。As described above, in the copper alloy lead frame, delamination in the semiconductor device (IC) due to the formation of a copper oxide film on the surface of the lead frame is prevented, and the reliability of the IC is reduced. It is desired to prevent a reduction in the non-defective rate in the IC assembly process and the mounting process.
There has been a demand for a material that can prevent delamination caused by the lead frame. Under the circumstances, the present invention is made of a copper alloy that can prevent delamination due to the formation of a copper oxide film on the surface of the lead frame and does not impair the bondability regardless of the IC assembly conditions. It is intended to provide a lead frame.
【０００９】[0009]
【課題を解決するための手段】本発明のリードフレーム
は、銅合金材を母材とし、ワイヤボンディング用ないし
ダイボンディング用の、銀、金、パラジウムの少なくと
も１つからなる部分貴金属めっきが施され、且つ、該部
分貴金属銀めっきの下地めっきとして銅ストライクめっ
きを施してある樹脂封止型の半導体装置用リードフレー
ムであって、少なくとも封止樹脂と接する側の銅合金材
表面の全部ないし所定の部分に銀、金、白金、パラジウ
ムの少なくとも１つからなる薄い貴金属めっきが施さ
れ、該薄い貴金属めっき上に銅めっきが形成されてお
り、且つ、銅めっき上の所定の領域に前記部分貴金属め
っきが形成されていることを特徴とするものである。そ
して、上記において、薄い貴金属めっきの厚みが０．５
μｍ以下、０．００１μｍ以上であることを特徴とする
ものである。そしてまた、上記における部分貴金属めっ
きは部分銀めっきであり、且つ、薄い貴金属めっきが薄
い銀めっきであることを特徴とするものである。本発明
のリードフレームの部分貴金属めっき方法は、銅合金材
を母材とし、ワイヤボンディング用ないしダイボンディ
ング用の、銀、金、パラジウムの少なくとも１つからな
る部分貴金属めっきが施され、且つ、該部分貴金属銀め
っきの下地めっきとして銅ストライクめっきを施してあ
る樹脂封止型の半導体装置用リードフレームの部分貴金
属めっき方法であって、少なくとも、順に、（Ａ）外形
加工された銅合金材からなるリードフレーム素材の表面
の全部ないし所定の部分に、厚みが０．００１〜０．５
μｍの銀、金、白金、パラジウムの少なくとも１つから
なる薄い貴金属めっきを施す工程と、（Ｂ）薄い貴金属
めっきが施されたリードフレームの表面の全部ないし少
なくとも前記部分貴金属めっき領域を含む部分に銅めっ
きを施す工程と、（Ｃ）銅めっきが施されたリードフレ
ームの表面の所定領域に部分貴金属めっきを施す工程と
を有することを特徴とするものである。そして、上記に
おいて、薄い貴金属めっきを、電解めっきないし無電解
めっきにより施すことを特徴とするものである。そして
また、上記において、部分貴金属めっきは部分銀めっき
であり、且つ、薄い貴金属めっきが薄い銀めっきである
ことを特徴とするものである。本発明の半導体装置は、
本発明のリードフレームを用いたことを特徴とするもき
であり、少なくとも封止用樹脂と接するリードフレーム
表面の全部ないし所定の部分の銅酸化膜形成領域におい
て、貴金属の濃度が、Ｘ線光電子分光による測定で、
０．１原子％以上〜２０原子％未満であることを特徴と
するものである。尚、上記において、部分貴金属めっき
とは、リードフレームを用いて半導体装置を作製する際
のワイヤボンディング用ないしダイボンディング用に、
リードフレームのインナーリード先端部やダイバッド部
の表面に貴金属めっきを施すもので、上記における所定
の領域とは、このインナーリード先端部やダイバッド部
の表面領域を言う。一般には、マスキング治具を用い、
リードフレームの所定の領域にのみめっき液を吹きつけ
て、または電着レジスト等により所定の領域のみをめっ
き液に接するようにしてリードフレーム全体をめっき液
に浸しながら、リードフレームの所定領域にのみめっき
を施す。The lead frame of the present invention is formed of a copper alloy material as a base material and is subjected to partial precious metal plating for wire bonding or die bonding, which is made of at least one of silver, gold and palladium. A resin-encapsulated lead frame for a semiconductor device, which has been subjected to copper strike plating as an undercoat of the partial noble metal silver plating, wherein at least the entire or predetermined surface of the copper alloy material on the side in contact with the sealing resin A thin noble metal plating made of at least one of silver, gold, platinum, and palladium is applied to a part, copper plating is formed on the thin noble metal plating, and the partial noble metal plating is provided in a predetermined region on the copper plating. Are formed. And in the above, the thickness of the thin precious metal plating is 0.5.
It is characterized by being less than or equal to μm and greater than or equal to 0.001 μm. The partial noble metal plating in the above is partial silver plating, and the thin noble metal plating is thin silver plating. A method for partially plating a noble metal of a lead frame according to the present invention is performed by using a copper alloy material as a base material and performing a partial noble metal plating of at least one of silver, gold, and palladium for wire bonding or die bonding, and A partial precious metal plating method for a resin-encapsulated lead frame for a semiconductor device, in which copper strike plating is applied as an undercoat of a partial precious metal silver plating, which is composed of at least (A) an externally processed copper alloy material. The thickness of 0.001 to 0.5 is applied to the entire surface of the lead frame material or to a predetermined portion of the surface.
the step of applying a thin noble metal plating of at least one of μm of silver, gold, platinum, and palladium, and (B) the entire surface of the lead frame plated with the thin noble metal or at least a part including the partial noble metal plating region. It is characterized by including a step of performing copper plating and (C) a step of performing partial noble metal plating on a predetermined region of the surface of the lead frame on which the copper plating has been performed. In the above, thin precious metal plating is performed by electrolytic plating or electroless plating. Further, in the above, the partial precious metal plating is a partial silver plating, and the thin precious metal plating is a thin silver plating. The semiconductor device of the present invention
The lead frame of the present invention is used, wherein the concentration of the noble metal is X-ray photoelectron in at least the entire or predetermined portion of the copper oxide film forming region of the lead frame surface in contact with the sealing resin. By spectroscopic measurement,
It is characterized by being 0.1 atomic% or more and less than 20 atomic%. In the above, the partial precious metal plating is used for wire bonding or die bonding when manufacturing a semiconductor device using a lead frame,
Noble metal plating is applied to the surface of the inner lead tip portion or the dibad portion of the lead frame. The predetermined area in the above means the surface area of the inner lead tip portion or the dibad portion. Generally, using a masking jig,
Only by spraying the plating solution only on the specified area of the lead frame, or by immersing the entire lead frame in the plating solution so that only the specified area is in contact with the plating solution with an electrodeposition resist, etc. Apply plating.
【００１０】[0010]
【作用】本発明のリードフレームは、上記のような構成
にすることにより、ＩＣの組み立て条件によらず、リー
ドフレームに起因する半導体装置における封止樹脂のデ
ラミネーションの発生を防止でき、且つ、ボンディング
性を損なわない銅合金製のリードフレームの提供を可能
としている。詳しくは、少なくとも封止樹脂と接する側
の銅合金材表面の全部ないし所定の部分に薄い貴金属め
っきが施され、該薄い貴金属めっき上に銅めっきが形成
されており、且つ、銅めっき上の所定の領域に部分貴金
属めっきが形成されていることにより、リードフレーム
表面の銅酸化膜に起因したデラミネーション（剥離）を
防止できるものとしている。即ち、薄い貴金属めっきが
銅合金材の表面に施された箇所においては、貴金属はＩ
Ｃ組み立て工程中における加熱により銅酸化膜内部に拡
散するため、銅合金材の表面に施された薄い貴金属めっ
きは銅めっき部および銅合金材の酸化を抑えて、酸化膜
厚を低減するとともに、酸化膜生成の際にはＣｕＯより
Ｃｕ2 Ｏの生成を優先させ、酸化膜自体が破壊されにく
くなり、封止樹脂とのデラミネーションの発生を抑える
ことができるのである。特に、半導体素子を搭載する側
でないダイパッド裏面の銅部表面に、薄い貴金属めっ
き、銅めっきを順次施してある場合には、少なくとも、
ダイパッド裏面でのリードフレーム表面の銅酸化膜に起
因したデラミネーション（剥離）を効果的に防止できる
ものとしている。また、薄い貴金属めっき、銅めっき
が、リードフレーム表面全体に施した場合には、ダイパ
ッド裏面を含みリードフレームと封止用樹脂との全ての
界面でのリードフレーム表面の銅酸化膜に起因したデラ
ミネーション（剥離）を防止できるものとしており、且
つ、ダイパッドの裏面のみに部分的にめっきを施す場合
と異なり、めっき用治具等を必要としないものとしてい
る。そして、薄い貴金属めっきの厚みを０．５μｍ以
下、０．００１μｍ以上としていることにより、デラミ
ネーション（剥離）の防止の効果が得られる適切な膜厚
としている。即ち、薄い貴金属めっきの厚みが０．００
１μｍより薄い場合には、銅ストライクめっき中に拡散
する銀の濃度が小さく、上記効果が得られず、厚みを
０．５μｍより厚くするとめっき時間と費用がかかるば
かりでなく、ＩＣ組み立て工程で貴金属が銅酸化膜内部
に十分に拡散しないため封止樹脂との密着強度が劣化す
ると考えられる。また、薄い貴金属めっきが銅めっきの
下に施されているため、その後の貴金属めっき工程、ワ
イヤボンディング工程は、従来の処理と同様の工程にて
処理でき、貴金属めっきの密着性も問題なく、ワイヤボ
ンディング適性も問題がない。また、半田めっき性に関
しては、半田めっきの前処理として行われる酸洗浄や化
学研磨処理によって銅酸化膜が除去される為、従来の図
６（ａ）に示すリードフレームとかわらず良好である。
更に、部分貴金属めっきを施す際に、不要部分に貴金属
モレが生じることが多々あり、これを電解剥離により除
去をすることがあるが、薄い貴金属めっきが銅めっきの
下に施されているため、薄い貴金属めっき部への影響を
与えずに貴金属モレ部のみを除去することができる。ま
た、薄い貴金属めっきが銅めっきの下に施されているた
め、図６（ａ）に示す従来のものと同じ外観を確保でき
る。また、部分貴金属めっきは部分銀めっきであり、且
つ、薄い貴金属めっきが、薄い銀めっきであることによ
り、従来使用されている電解めっき方法や無電解めっき
方法により、比較的簡単にめっきを安定的に行うことが
でき、生産コストを下げることができる。With the lead frame of the present invention having the above-mentioned structure, it is possible to prevent the occurrence of delamination of the sealing resin in the semiconductor device due to the lead frame, regardless of the IC assembly conditions, and It is possible to provide a lead frame made of copper alloy that does not impair the bondability. Specifically, at least all or a predetermined portion of the surface of the copper alloy material on the side in contact with the sealing resin is plated with a thin noble metal, and the copper plating is formed on the thin noble metal plating. By forming the partial noble metal plating in the area (2), delamination (peeling) due to the copper oxide film on the surface of the lead frame can be prevented. That is, in the place where a thin precious metal plating is applied to the surface of the copper alloy material, the precious metal is I
Since the copper noble metal plating applied to the surface of the copper alloy material suppresses the oxidation of the copper plated part and the copper alloy material to reduce the oxide film thickness, since the copper noble metal plating is diffused into the copper oxide film by heating during the assembly process. When forming the oxide film, the generation of Cu 2 O is given priority over that of CuO, the oxide film itself is less likely to be destroyed, and the occurrence of delamination with the sealing resin can be suppressed. In particular, on the surface of the copper portion on the back surface of the die pad that is not the side on which the semiconductor element is mounted, at least when thin precious metal plating and copper plating are sequentially performed,
It is supposed that delamination (peeling) due to the copper oxide film on the surface of the lead frame on the back surface of the die pad can be effectively prevented. In addition, when a thin precious metal plating or copper plating is applied to the entire surface of the lead frame, the depletion caused by the copper oxide film on the surface of the lead frame at all interfaces between the lead frame and the sealing resin including the back surface of the die pad. Lamination (peeling) can be prevented, and unlike the case where only the back surface of the die pad is partially plated, no plating jig or the like is required. The thickness of the thin precious metal plating is set to 0.5 μm or less and 0.001 μm or more, so that an appropriate film thickness that can obtain the effect of preventing delamination (peeling) is obtained. That is, the thickness of the thin precious metal plating is 0.00
If the thickness is less than 1 μm, the concentration of silver diffused during copper strike plating is small and the above effect cannot be obtained. If the thickness is more than 0.5 μm, not only the plating time and cost will be increased, but also precious metal in the IC assembly process. Is not sufficiently diffused inside the copper oxide film, it is considered that the adhesion strength with the sealing resin deteriorates. In addition, since the thin precious metal plating is applied under the copper plating, the subsequent precious metal plating process and wire bonding process can be performed in the same process as the conventional process, and the adhesion of the precious metal plating does not cause any problems. There is no problem in bonding suitability. Further, regarding the solder plating property, the copper oxide film is removed by the acid cleaning or the chemical polishing process which is performed as the pretreatment of the solder plating, and therefore, the solder plating property is good regardless of the conventional lead frame shown in FIG.
Furthermore, when performing partial noble metal plating, noble metal leak often occurs in unnecessary parts, and this may be removed by electrolytic peeling, but since a thin noble metal plating is applied below the copper plating, Only the precious metal leak portion can be removed without affecting the thin precious metal plating portion. Further, since the thin precious metal plating is applied under the copper plating, the same appearance as the conventional one shown in FIG. 6A can be secured. In addition, since the partial noble metal plating is the partial silver plating and the thin precious metal plating is the thin silver plating, it is possible to stabilize the plating relatively easily by the electrolytic plating method or the electroless plating method that has been conventionally used. Can be carried out, and the production cost can be reduced.
【００１１】本発明のリードフレームの部分貴金属めっ
き方法は、上記のような構成にすることにより、本発明
のリードフレームの製造を可能とするものである。そし
て、電解めっきないし無電解めっきにより薄い貴金属め
っきを施すことにより、薄い貴金属めっきの膜厚の制御
を簡単なものとしている。特に、上記において、薄い貴
金属めっき、銅めっきをリードフレーム全体に施す場合
には、マスキング治具を必要とせず各めっきの被膜生成
作業を簡単なものとできる。尚、薄い貴金属めっきを施
す方法としては、電解めっき、無電解めっきいずれも使
用できるが、めっき速度を速くして、めっき厚を精度良
く制御するためには電解めっき法が適し、複雑な形状で
あるリードフレームに対するめっきのつきまわり性を求
める場合には無電解めっき法が適している。上記におい
て、部分貴金属めっきは部分銀めっきであり、且つ、薄
い貴金属めっきが薄い銀めっきであることにより、従来
使用の電解めっき方法や無電解めっき方法により比較的
簡単に、めっきを安定的に行うことができるものとして
いる。同時に、金めっきや白金めっきに比べ生産コスト
を下げることができる。The method of partially plating a noble metal of a lead frame according to the present invention makes it possible to manufacture the lead frame of the present invention with the above-mentioned structure. The thin precious metal plating is applied by electrolytic plating or electroless plating to simplify the control of the film thickness of the thin precious metal plating. In particular, in the above case, when thin noble metal plating or copper plating is applied to the entire lead frame, a masking jig is not required, and the work of forming a coating film for each plating can be simplified. As a method of applying a thin precious metal plating, either electrolytic plating or electroless plating can be used. However, the electrolytic plating method is suitable for increasing the plating speed and accurately controlling the plating thickness, and the complicated shape is used. The electroless plating method is suitable for obtaining the throwing power of the plating on a certain lead frame. In the above, since the partial noble metal plating is the partial silver plating and the thin noble metal plating is the thin silver plating, the plating is stably performed relatively easily by the conventionally used electrolytic plating method or electroless plating method. It is supposed to be possible. At the same time, the production cost can be reduced compared to gold plating or platinum plating.
【００１２】本発明の半導体装置は、上記本発明のリー
ドフレームを用いることにより、ワイヤボンディング工
程における熱処理等を経て、封止樹脂と接するリードフ
レーム表面の全部ないし所定の部分に、金、銀、白金、
パラジウムの少なくとも１つと銅酸化膜からなる領域を
もつ表面部を形成でき、これにより、封止樹脂と接する
部分の剥離を防止できるものとしている。そして、封止
樹脂と接するリードフレーム表面の全部ないし所定の部
分の銅酸化膜形成領域において、貴金属の濃度が、Ｘ線
光電子分光による測定で、０．１原子％以上であること
により、銅酸化膜ないし銅酸化膜と銅合金との境での破
壊強度を充分なものとでき、２０原子％未満であること
により、封止樹脂との密着性が劣る銀の特質をカバーす
ることができ、銅酸化膜と封止樹脂との密着性を充分な
ものとしている。In the semiconductor device of the present invention, by using the lead frame of the present invention, heat treatment or the like in the wire bonding step is performed, and gold, silver, or silver is formed on all or predetermined portions of the lead frame surface in contact with the sealing resin. platinum,
A surface portion having a region composed of at least one of palladium and a copper oxide film can be formed, whereby peeling of a portion in contact with the sealing resin can be prevented. When the concentration of the noble metal is 0.1 atom% or more as measured by X-ray photoelectron spectroscopy in the copper oxide film forming region on the entire surface or a predetermined portion of the lead frame surface in contact with the sealing resin, the copper oxide The breaking strength at the boundary between the film or the copper oxide film and the copper alloy can be made sufficient, and when it is less than 20 atomic%, it is possible to cover the characteristic of silver having poor adhesion to the sealing resin, Adhesion between the copper oxide film and the sealing resin is sufficient.
【００１３】[0013]
【実施例】本発明のリードフレームの実施例を以下、図
にそって説明する。先ず、実施例１のリードフレームを
挙げて説明する。図１は本発明のリードフレームの実施
例１を示したもので、図１（ｂ）はその平面図を、図１
（ａ）はＡ１−Ａ２における断面の要部拡大図である。
図１中、１１０はリードフレーム、１１１はダイパッ
ド、１１２はインナーリード、１１３はアウターリー
ド、１１４はダムバー、１１５はフレーム、１１６は吊
りバー、１２０はリードフレーム素材（銅合金）、１３
０は薄い銀めっき、１４０は銅めっき、１５０は部分銀
めっきである。本実施例のリードフレーム１１０は、厚
さ０．１５ｍｍの銅合金材（古河電気工業株式会社製Ｅ
ＦＴＥＣ６４Ｔ−１／２Ｈ材）からエッチング加工によ
り図１（ｂ）のような形状に外形加工されたリードフレ
ーム素材１２０に対し、薄い銀めっき１３０、銅めっき
１４０を順次、リードフレームの表面全面に施してか
ら、この上に所定の領域にのみに部分銀めっき１５０を
施したものである。本実施例においては、薄い銀めっき
を厚さ０．０１μｍ、銅めっきを厚さ０．１μｍ、部分
銀めっきを厚さ３μｍとしたが、銅めっきの厚さとして
は、０．１〜０．３μｍ、部分銀めっきの厚さとしては
１．５〜１０μｍ、薄い銀めっき１３０の厚さとしては
０．００１μｍ以上、０．５μｍ以下が好ましい。ま
た、リードフレーム素材１２０として古河電気工業株式
会社製の銅合金ＥＦＴＥＣ６４Ｔ−１／２Ｈ材を用いて
いるが、本発明はこれに限定されることはなく、他の銅
合金でも良い。Embodiments of the lead frame of the present invention will be described below with reference to the drawings. First, the lead frame of Example 1 will be described. 1 shows a first embodiment of a lead frame of the present invention, and FIG. 1 (b) is a plan view thereof.
(A) is an enlarged view of a main part of a cross section taken along line A1-A2.
In FIG. 1, 110 is a lead frame, 111 is a die pad, 112 is an inner lead, 113 is an outer lead, 114 is a dam bar, 115 is a frame, 116 is a suspension bar, 120 is a lead frame material (copper alloy), 13
0 is thin silver plating, 140 is copper plating, and 150 is partial silver plating. The lead frame 110 of this embodiment is a copper alloy material (E manufactured by Furukawa Electric Co., Ltd.) having a thickness of 0.15 mm.
Thin lead plating 130 and copper plating 140 are sequentially applied to the entire surface of the lead frame on a lead frame material 120 that has been externally processed into a shape as shown in FIG. 1B by etching from FTEC64T-1 / 2H material). Then, the partial silver plating 150 is applied only to a predetermined area on the above. In this embodiment, the thin silver plating has a thickness of 0.01 μm, the copper plating has a thickness of 0.1 μm, and the partial silver plating has a thickness of 3 μm, but the thickness of the copper plating is 0.1 to 0. 3 μm, the thickness of the partial silver plating is 1.5 to 10 μm, and the thickness of the thin silver plating 130 is preferably 0.001 μm or more and 0.5 μm or less. Further, although the copper alloy EFTEC64T-1 / 2H made by Furukawa Electric Co., Ltd. is used as the lead frame material 120, the present invention is not limited to this, and other copper alloys may be used.
【００１４】本実施例のリードフレームは、図１（ａ）
に示すように、外形加工されたリードフレーム素材１２
０に対し、薄い銀めっき１３０、銅１４０を順次、全面
に施してから、この上に所定の領域にのみに部分銀めっ
き１５０を施したものであり、薄い銀めっき１３０を設
けていることにより、母材金属（銅合金材）と酸化膜と
の密着性が向上し、結果として、半導体装置を作製する
場合には封止樹脂とのデラミネーションの発生を抑える
ことができるものとしている。The lead frame of this embodiment is shown in FIG.
As shown in, the lead frame material 12 is
In contrast to 0, a thin silver plating 130 and a copper 140 are sequentially applied to the entire surface, and then a partial silver plating 150 is applied only to a predetermined area on the entire surface. By providing the thin silver plating 130, The adhesion between the base metal (copper alloy material) and the oxide film is improved, and as a result, delamination with the sealing resin can be suppressed when a semiconductor device is manufactured.
【００１５】次に、実施例２のリードフレームを挙げて
説明する。図２は本発明のリードフレームの実施例２を
示したもので、図２（ｂ）はその下面図を、図２（ａ）
はＡ３−Ａ４における断面の要部拡大図である。図２
中、１１０はリードフレーム、１１１はダイパッド、１
１２はインナーリード、１１３はアウターリード、１１
４はダムバー、１１５はフレーム、１２０はリードフレ
ーム素材（銅合金）、１３０は薄い銀めっき、１４０は
銅めっき、１５０は部分銀めっきである。本実施例のリ
ードフレームが、実施例１と異なるのは、薄い銀めっき
１３０を半導体素子を搭載する側でないダイパッド１１
１の裏面にのみ施した点のみで、他は実施例１と同じで
ある。Next, the lead frame of the second embodiment will be described. 2 shows a second embodiment of the lead frame of the present invention, and FIG. 2 (b) is a bottom view thereof, and FIG.
FIG. 4 is an enlarged view of a main part of a cross section taken along line A3-A4. FIG.
Inside, 110 is a lead frame, 111 is a die pad, 1
12 is an inner lead, 113 is an outer lead, 11
4 is a dam bar, 115 is a frame, 120 is a lead frame material (copper alloy), 130 is thin silver plating, 140 is copper plating, and 150 is partial silver plating. The lead frame of this embodiment differs from that of the first embodiment in that the thin silver plating 130 is not on the side on which the semiconductor element is mounted.
1 is the same as Example 1 except that it was applied only to the back surface of No. 1.
【００１６】次に、実施例１、実施例２と併せ、変形例
と比較例についての封止樹脂密着強度、酸化膜剥れ状態
を評価した。変形例１、変形例２、変形例３は、それぞ
れ実施例１と同じ構成のもので薄い銀めっきの厚さを
０．１μｍ、０．５μｍ、１．０μｍとしたものであ
る。また、比較例１としては、図６に示す従来例で変色
防止処理を施したものを、比較例２としては、従来例に
おいて変色防止処理を施して無いものを用いた。尚、上
記実施例１、実施例２、変形例、比較例とも、銅めっき
の厚さは０．１μｍ、部分銀めっきの厚さ３μｍとし
た。封止樹脂密着強度は、封止樹脂密着強度評価用の専
用フレーム（ベタ状板）に実施例１、各変形例および比
較例と同じ表面処理を施し、ワイヤボンディング想定加
熱条件、２８０°Ｃ、３分間の条件で加熱した後、銅合
金材面に一定面積の封止樹脂を成形し、シエア法により
密着強度を測定した。さらに、試験後の封止樹脂への酸
化膜の付着状態を観察し、母材からの酸化膜剥がれを評
価した。シエア法による密着強度の判定、酸化膜剥れの
判定は、２．０Ｎ／ｍｍ2 以上を可（○）とし、２．０
Ｎ／ｍｍ2 未満を不可（×）とした。 Next, together with Examples 1 and 2, the sealing resin adhesion strength and oxide film peeling state of the modified example and the comparative example were evaluated. The modification 1, modification 2, and modification 3 each have the same configuration as that of the embodiment 1, and have thin silver plating thicknesses of 0.1 μm, 0.5 μm, and 1.0 μm. Further, as Comparative Example 1, the one which has been subjected to the discoloration prevention treatment in the conventional example shown in FIG. 6 is used, and as Comparative Example 2, one which has not been subjected to the discoloration prevention treatment in the conventional example is used. The thickness of the copper plating was 0.1 μm and the thickness of the partial silver plating was 3 μm in each of the above-mentioned Examples 1, 2 and the modifications and comparative examples. The sealing resin adhesion strength was determined by subjecting a dedicated frame (solid plate) for evaluating the sealing resin adhesion strength to the same surface treatment as in Example 1, each modified example and comparative example, and assuming the wire bonding heating conditions at 280 ° C. After heating under the condition of 3 minutes, a sealing resin having a certain area was molded on the surface of the copper alloy material, and the adhesion strength was measured by the shear method. Further, the adhesion state of the oxide film to the sealing resin after the test was observed, and the peeling of the oxide film from the base material was evaluated. The adhesion strength and the oxide film peeling by the shear method are 2.0 N / mm 2 or more (OK), and 2.0
A value less than N / mm 2 was regarded as unacceptable (x).
【００１７】表１に示すように、薄い銀めっきを行っ
た、実施例１、実施例２、変形例１、変形例２は、封止
樹脂密着強度、酸化膜剥れの点において、図６に示す方
法により部分銀めっきが施された比較例１よりも優れて
いることが分かった。また、比較例２は、酸化膜剥れの
評価において、実施例１、実施例２、変形例１、変形例
２に劣ることが分かった。また、変形例３は封止樹脂密
着強度の点で実施例１、実施例２、変形例１、変形例２
に劣り、薄い銀めっきの厚さが厚過ぎても薄い銀めっき
を設けることの効果がなくなることも分かる。これよ
り、上記本発明の実施例１、実施例２、変形例１、変形
例２リードフレームが、図６（ｂ）に示す工程にてめっ
きされた従来のリードフレームに比べ、半導体装置に用
いられた際には、銅酸化膜生成に起因するＩＣパッケー
ジのデラミネーションの発生を効果的に抑えることがで
きると判断される。As shown in Table 1, Examples 1, 2 and 1 and 2 which were thinly plated with silver are shown in FIG. 6 in terms of sealing resin adhesion strength and oxide film peeling. It was found to be superior to Comparative Example 1 in which partial silver plating was applied by the method shown in FIG. Further, it was found that Comparative Example 2 was inferior to Example 1, Example 2, Modification 1 and Modification 2 in evaluation of oxide film peeling. In addition, the modified example 3 is different from the example 1 in the sealing resin adhesion strength in the example 1, the example 2, the modified example 1, and the modified example 2.
It is also understood that the effect of providing thin silver plating is lost even if the thickness of thin silver plating is too thick. Thus, the lead frames of Example 1, Example 2, Modification 1 and Modification 2 of the present invention are used in the semiconductor device as compared with the conventional lead frame plated in the step shown in FIG. 6B. In this case, it is judged that the delamination of the IC package due to the formation of the copper oxide film can be effectively suppressed.
【００１８】次に、本発明のリードフレームの貴金属部
分めっき方法の実施例を挙げ、図３に基づいて簡単に説
明する。本実施例のリードフレームの貴金属部分めっき
方法は、上記本発明のリードフレームの実施例１を作製
するためのめっき方法である。尚、図３図は、図１
（ａ）に相当する部分である。先ず、エッチングにて外
形加工された銅合金からなるリードフレーム１１０Ａの
全面をアルカリ水溶液で電解脱脂し、純水で洗浄した
後、酸性液で表面に形成されている酸化膜を除去する酸
活性化処理を行い、リードフレーム素材１２０である銅
合金の表面を活性化して、再度純水で洗浄した。（図３
（ａ）） 次いで、薄い銀めっき１３０をリードフレーム１１０Ａ
の全面に、厚さ０．０１μｍの厚さで形成した。（図３
（ｂ）） 尚、この薄い銀めっきは、シアン化銀水溶液中に浸漬し
て電解めっきにて行った。本発明のリードフレームの実
施例２を作製する場合には、薄い銀めっきをダイパッド
部のみに施すため、所定の部分をマスキングしてめっき
を行う必要がある。次いで、アルカリ中和処理、酸活性
化処理を経て、純水でリードフレーム表面を洗浄した
後、銀めっきが施されたリードフレーム１１０Ａの全面
に、液温５０°Ｃで約２０秒間シアン化銅めっきを行
い、０．１μｍの厚さで銅めっき１４０を施した。（図
３（ｃ）） 次いで、純水で銅めっき１４０が施されたリードフレー
ム１１０Ａ表面を洗浄した後、銀めっき処理時に不要な
部分に銀が析出しないように、全面に銀の置換防止処理
を行なった。置換防止処理は、室温で有機硫黄系の溶液
に浸し薄い被膜を形成したものである。次いで、リード
フレームの半導体素子を搭載する側のダイバッド部、イ
ンナーリード先端領域のみを露出させるようにマスキン
グ治具で覆い、リードフレームを陰極として、めっき液
をノズルより噴射により吹きかける方式の部分めっきに
より、厚さ３μｍの銀めっきをードフレームの所定の領
域に施した後、純水でリードフレームを洗浄し、温風で
乾燥して、実施例のリードフレームを得た。（図３
（ｄ））Next, an example of the method for partially plating a noble metal of a lead frame of the present invention will be given and briefly described with reference to FIG. The noble metal partial plating method for the lead frame of this example is a plating method for producing the above-described lead frame of Example 1 of the present invention. It should be noted that FIG.
This is a part corresponding to (a). First, after electrolytically degreasing the entire surface of the lead frame 110A made of a copper alloy that has been externally processed by etching with an alkaline aqueous solution and washing with pure water, acid activation for removing an oxide film formed on the surface with an acid solution After the treatment, the surface of the copper alloy that is the lead frame material 120 was activated and washed again with pure water. (Fig. 3
(A)) Next, the thin silver plating 130 is applied to the lead frame 110A.
Was formed on the entire surface of the substrate with a thickness of 0.01 μm. (Fig. 3
(B)) This thin silver plating was performed by electrolytic plating by immersing it in an aqueous solution of silver cyanide. When manufacturing Example 2 of the lead frame of the present invention, since thin silver plating is applied only to the die pad portion, it is necessary to mask and plate a predetermined portion. Then, after alkali neutralization treatment and acid activation treatment, the lead frame surface is washed with pure water, and then the entire surface of the silver-plated lead frame 110A is treated with copper cyanide at a liquid temperature of 50 ° C. for about 20 seconds. The plating was performed, and the copper plating 140 was applied to a thickness of 0.1 μm. (FIG. 3 (c)) Next, after cleaning the surface of the lead frame 110A that has been plated with copper 140 with pure water, silver substitution prevention treatment is performed on the entire surface so that silver does not deposit on unnecessary portions during silver plating treatment. Was done. The substitution prevention treatment is a thin film formed by immersing the solution in an organic sulfur solution at room temperature. Then, by covering with a masking jig so as to expose only the die pad portion of the lead frame on which the semiconductor element is mounted and the inner lead tip region, the lead frame is used as a cathode and the plating solution is sprayed from a nozzle by partial plating. After a silver plating having a thickness of 3 μm was applied to a predetermined region of the lead frame, the lead frame was washed with pure water and dried with warm air to obtain a lead frame of the example. (Fig. 3
(D))
【００１９】次に、本発明の半導体装置の実施例を挙
げ、図にそって説明する。実施例１の半導体装置は、上
記本発明のリードフレームの実施例１を用いたもので、
図４（ａ）はその概略断面図であり、図４（ｂ）は図４
（ａ）のＢ１、Ｂ２における断面の状態を拡大して示し
たものである。尚、説明を分かり易くするため、図６
（ａ）に示す従来のリードフレームを用い、本実施例の
半導体装置と同じ条件にて作製した半導体装置における
Ｂ１、Ｂ２に相当する位置の状態を拡大して図４（ｃ）
に示しておく。本実施例の半導体装置は、図５（ｃ）に
示すワイヤボンディング工程、図５（ｄ）に示す樹脂封
止工程を経て作製されたものである。Next, an example of a semiconductor device of the present invention will be given and described with reference to the drawings. The semiconductor device of Example 1 uses the above-described Example 1 of the lead frame of the present invention.
4 (a) is a schematic sectional view thereof, and FIG. 4 (b) is shown in FIG.
It is an enlarged view of the cross-sectional state of B1 and B2 in (a). In addition, in order to make the explanation easy to understand, FIG.
FIG. 4C is an enlarged view of the state of positions corresponding to B1 and B2 in the semiconductor device manufactured under the same conditions as the semiconductor device of this embodiment using the conventional lead frame shown in FIG.
Will be shown. The semiconductor device of the present embodiment is manufactured through the wire bonding process shown in FIG. 5C and the resin sealing process shown in FIG. 5D.
【００２０】実施例２の半導体装置は、上記本発明のリ
ードフレームの実施例２を用いたもので、実施例１と同
様、ワイヤボンディング工程、樹脂封止工程を経て作製
されたものであるが、外見上は、図４に示す実施例１と
同じであるが、表面の銅酸化膜の厚さや、拡散された銀
の存在する領域が異なる。実施例１、実施例２の半導体
装置とも、デラミネーションの発生は見られなかった。The semiconductor device of Example 2 uses the above-described Example 2 of the lead frame of the present invention and is manufactured through the wire bonding step and the resin sealing step as in Example 1. The appearance is the same as that of the first embodiment shown in FIG. 4, but the thickness of the copper oxide film on the surface and the region where the diffused silver exists are different. No occurrence of delamination was observed in the semiconductor devices of Examples 1 and 2.
【００２１】前述の実施例のリードフレームを用いて半
導体装置（ＩＣパッケージ）を作製する工程を図５を用
いて簡単に説明しておく。先ず、図１に示す実施例のリ
ードフレーム１１０のダイパッド１１１を、ダウンセッ
ト加工し（図５（ａ））、ダイパッド１１１上に銀ペー
スト１７０を介して半導体素子１６０を接合する。（図
５（ｂ）） 次いで、銀ペースト１７０を加熱キュアした後、半導体
素子１６０の電極パッド（端子）１６１とリードフレー
ム１１０の部分銀めっき１４０が施されたインナーリー
ド１１２の先端とをワイヤ（金線）１８０でワイヤボン
ディングして電気的に結線する。（図５（ｃ）） 次いで、樹脂封止、ダムバーの除去、アウターリードの
フォーミング処理、半田めっきを経て、半導体装置２０
０を得る。（図５（ｄ）） 以上の工程を経て、図１に示すリードフレーム１１０表
面の銅めっき１４０、ないしリードフレーム素材（銅合
金）１２０の一部は酸化され、図５（ｃ）に示す銅酸化
膜１９０を形成する。これと同時に、図１に示す銅めっ
き１４０下の薄い銀めっき１３０は、銅酸化膜１９０お
よびリードフレーム素材（銅合金）１２０中へ拡散され
る。A process of manufacturing a semiconductor device (IC package) using the lead frame of the above-mentioned embodiment will be briefly described with reference to FIG. First, the die pad 111 of the lead frame 110 of the embodiment shown in FIG. 1 is downset processed (FIG. 5A), and the semiconductor element 160 is bonded onto the die pad 111 via the silver paste 170. (FIG. 5B) Next, after the silver paste 170 is cured by heating, the electrode pads (terminals) 161 of the semiconductor element 160 and the tips of the inner leads 112 of the lead frame 110 on which the partial silver plating 140 is applied are formed by a wire ( A gold wire) 180 is wire-bonded and electrically connected. (FIG. 5C) Next, the semiconductor device 20 is subjected to resin sealing, dam bar removal, outer lead forming processing, and solder plating.
Get 0. (FIG. 5D) Through the above steps, the copper plating 140 on the surface of the lead frame 110 shown in FIG. 1 or a part of the lead frame material (copper alloy) 120 is oxidized and the copper shown in FIG. An oxide film 190 is formed. At the same time, the thin silver plating 130 under the copper plating 140 shown in FIG. 1 is diffused into the copper oxide film 190 and the lead frame material (copper alloy) 120.
【００２２】上記実施例のリードフレームを用いた半導
体装置２００の作製方法においては、図５（ｃ）の段階
で、加熱されたことによってダイパッド１１１における
銅の表面では、Ｘ線光電子分光分析（ＥＳＣＡ）で観察
すると、図４（ｂ）に示すようになっていた。尚、図４
（ｂ）中、２２０は銅酸化膜、２３０は拡散された銀の
存在領域、１２０はリードフレーム素材（銅合金）を示
している。図１に示す薄い銀めっき１３０の銀は、銅酸
化膜２２０及びリードフレーム素材（銅合金）２２０中
に拡散され、拡散された銀の存在領域２３０は、図４
（ｂ）に示すよう、銅酸化膜領域２２０とリードフレー
ム素材（銅合金）２１０の一部に跨がる。銅酸化膜領域
２２０は、ＣｕＯ２２０Ｂを表面側にして、ＣｕＯ２２
０ＢとＣｕ2 Ｏ２２０Ａを形成する。薄い銀めっき１３
０の膜厚さ、加熱条件を変えることにより、銅酸化膜の
内側に銀が拡散している状態が異なる。銀の拡散は銅酸
化膜２２０のみならずリードフレーム素材（銅合金）１
２０まで及ぶ。In the method of manufacturing the semiconductor device 200 using the lead frame of the above embodiment, the copper surface of the die pad 111 which has been heated at the stage of FIG. 5C is subjected to X-ray photoelectron spectroscopy (ESCA). ), It was as shown in FIG. FIG.
In (b), 220 indicates a copper oxide film, 230 indicates an area where diffused silver exists, and 120 indicates a lead frame material (copper alloy). The silver of the thin silver plating 130 shown in FIG. 1 is diffused into the copper oxide film 220 and the lead frame material (copper alloy) 220, and the diffused silver existing region 230 is shown in FIG.
As shown in (b), the copper oxide film region 220 and a part of the lead frame material (copper alloy) 210 are straddled. The copper oxide film region 220 has the CuO 220B on the front surface side and the CuO 22
OB and Cu 2 O 220A are formed. Thin silver plating 13
By changing the film thickness of 0 and heating conditions, the state in which silver is diffused inside the copper oxide film differs. Diffusion of silver is not only copper oxide film 220 but also lead frame material (copper alloy) 1
Up to 20.
【００２３】これに対し、図５に示す工程と同じ工程に
て、従来の図６（ａ）に示す、銅めっきと部分銀めっき
のみを施したリードフレームを用い、半導体装置を作製
した場合には、図５（ｃ）に相当する工程での銅の酸化
状態は図４（ｃ）のようになる。従来の図６（ａ）に示
すリードフレームの場合には、銅表面に薄い銀めっきが
施されていないため、銅の酸化は速く、結果的に酸化膜
厚は、本実例の場合と比べ、厚くなり、且つ、銀の拡散
が無いため、実施例のリードフレームを用いた場合に比
べ、ＣｕＯよりＣｕ2 Ｏの生成が優先されることはな
い。On the other hand, in the case where a semiconductor device is manufactured by using the conventional lead frame shown in FIG. 6 (a), which is only plated with copper and partially silver, in the same process as shown in FIG. 4C shows the oxidation state of copper in the step corresponding to FIG. 5C. In the case of the conventional lead frame shown in FIG. 6 (a), since the thin silver plating is not applied to the copper surface, the copper oxidizes quickly, and as a result, the oxide film thickness is smaller than that of this example. Since the thickness is increased and there is no silver diffusion, the production of Cu 2 O is not prioritized over CuO as compared with the case where the lead frame of the example is used.
【００２４】図１、図２に示す実施例のリードフレーム
１１０は、薄い銀めっき１３０を設けていることによ
り、図５（ｃ）の工程において、銅酸化膜２２０の形成
を抑えている。即ち、図４（ｂ）、図４（ｃ）に示すよ
うに、実施例のリードフレームを用いて半導体装置を作
製した場合には、薄い銀めっきを設けていない従来のリ
ードフレームを用いた場合に比べ、銅酸化膜２２０の膜
厚を低減していることが分かる。また、実施例のリード
フレーム１１０を用いた場合、銅酸化膜２２０生成の
際、ＣｕＯよりＣｕ2 Ｏの生成を優先させるため、銅酸
化膜自体を破壊されにくくしており、結果として、樹脂
封止した際には、封止樹脂とのデラミネーションの発生
を抑えることができるものとしている。Since the lead frame 110 of the embodiment shown in FIGS. 1 and 2 is provided with the thin silver plating 130, the formation of the copper oxide film 220 is suppressed in the step of FIG. 5C. That is, as shown in FIGS. 4B and 4C, when a semiconductor device is manufactured using the lead frame of the embodiment, when a conventional lead frame without thin silver plating is used, It can be seen that the film thickness of the copper oxide film 220 is reduced as compared with. Further, in the case of using the lead frame 110 of the embodiment, when the copper oxide film 220 is formed, the generation of Cu 2 O is prioritized over CuO, so that the copper oxide film itself is less likely to be destroyed, and as a result, the resin sealing is performed. When stopped, the delamination with the sealing resin can be suppressed.
【００２５】また、別に、本発明のリードフレームの実
施例１において、薄い銀めっきに代え、薄いパラジウム
めっき（以下Ｐｄめっきとも表現する。）を０．００１
μｍ、０．０１μｍ、０、１μｍ、０．５μｍの厚さで
設けたもの、および、リードフレーム素材（銅合金）上
にＰｄめっきを１．０μｍの厚さで設けたもの、従来の
薄いめっきを設けないものについて、ダイパッド裏面酸
化膜の密着性、封止樹脂の密着強度を評価したが、以下
の表２に示すように、表１に示す薄い銀めっきを設けた
場合と、薄いＰｄめっきを設けた場合についても、ほぼ
同じ結果が得られた。尚、評価方法、条件は表１に示す
薄い銀めっきを設けた場合と同じである。 Separately, in Example 1 of the lead frame of the present invention, 0.001 of thin palladium plating (hereinafter also referred to as Pd plating) is used instead of thin silver plating.
μm, 0.01 μm, 0, 1 μm, 0.5 μm thick, and lead frame material (copper alloy) with Pd plating 1.0 μm thick, conventional thin plating The adhesiveness of the oxide film on the back surface of the die pad and the adhesive strength of the sealing resin were evaluated for those not provided with, but as shown in Table 2 below, when the thin silver plating shown in Table 1 was provided and when the thin Pd plating was provided. The same result was obtained in the case of providing. The evaluation method and conditions are the same as in the case of providing the thin silver plating shown in Table 1.
【００２６】上記においては、リードフレームに薄い銀
めっき、薄いＰｄめっきを施した場合について説明した
が、薄い銀めっき、薄いＰｄめっきに代え、薄い金めっ
き、薄い白金めっきを施した場合も同様の作用効果が得
られると判断される。更に、これらの銀、Ｐｄ（パラジ
ウム）、金、白金の複数種類からなる薄いめっきを施し
た場合も同様の作用効果が得られると判断される。これ
らのリードフレームを用いた半導体装置についても、上
記実施例と同様、同じ作用効果が得られると判断され
る。また、部分銀めっきに代え、部分金めっき、部分Ｐ
ｄめっきとした場合にも、上記薄いめっきを設けること
が有効であることは言うまでもない。In the above description, the case where the lead frame is thinly silver-plated or thin Pd-plated has been described, but the same is true when the thin silver-plated or thin Pd-plated is replaced by thin gold-plated or thin platinum-plated. It is judged that the action and effect can be obtained. Further, it is judged that the same action and effect can be obtained when thin plating made of plural kinds of silver, Pd (palladium), gold and platinum is applied. It is judged that the semiconductor device using these lead frames can also obtain the same effects as in the above embodiment. Also, instead of partial silver plating, partial gold plating, partial P
Needless to say, it is effective to provide the above thin plating even when d plating is used.
【００２７】[0027]
【発明の効果】本発明は、上記のように、ＩＣの組み立
て条件によらず、リードフレームに起因するデラミネー
ションの発生を防止でき、且つ、ボンディング性を損な
わない、銅合金製のリードフレームを用いた半導体装置
の提供を可能としており、同時に、本発明の半導体装置
に用いられるリードフレームと、その製造方法の提供を
可能としている。そしてまた、本発明のリードフレーム
の部分貴金属めっき方法は、本発明のリードフレームの
製造を可能とするものであるが、特に、薄い貴金属めっ
きを均一性良く所定の厚さに形成できるものとしてい
る。そして、薄い貴金属めっき、銅めっきをリードフレ
ーム全体に施す場合には、マスキング治具を必要とせず
各めっきの被膜生成作業を簡単なものとできる。As described above, the present invention provides a lead frame made of a copper alloy, which can prevent the occurrence of delamination due to the lead frame and does not impair the bondability regardless of the IC assembling conditions. It is possible to provide the used semiconductor device, and at the same time, it is possible to provide the lead frame used for the semiconductor device of the present invention and the manufacturing method thereof. Further, the method for plating a partial noble metal of a lead frame of the present invention enables the production of the lead frame of the present invention, and in particular, it is supposed that a thin noble metal plating can be uniformly formed to a predetermined thickness. . When a thin noble metal plating or copper plating is applied to the entire lead frame, a masking jig is not required and the work of forming a coating film for each plating can be simplified.
【図１】本発明のリードフレームの実施例１の概略図FIG. 1 is a schematic view of a lead frame according to a first embodiment of the present invention.
【図２】本発明のリードフレームの実施例２の概略図FIG. 2 is a schematic diagram of Embodiment 2 of the lead frame of the present invention.
【図３】本発明のリードフレームの部分めっき方法の実
施例工程図FIG. 3 is a process chart of an embodiment of a method of partially plating a lead frame of the present invention.
【図４】本発明の半導体装置の概略図FIG. 4 is a schematic view of a semiconductor device of the present invention.
【図５】本発明の半導体装置の製造製作工程図FIG. 5 is a manufacturing process diagram of a semiconductor device of the present invention.
【図６】従来のリードフレームの部分銀めっきとめっき
工程を説明するための図FIG. 6 is a diagram for explaining a partial silver plating of a conventional lead frame and a plating process.
【図７】半導体装置とリードフレームを説明するための
図FIG. 7 is a diagram for explaining a semiconductor device and a lead frame.
１１０ リードフレーム １１０Ａ 外形加工された銅合金からなるリー
ドフレーム １１１ ダイパッド １１２ インナーリード １１３ アウターリード １１４ ダムバー １１５ フレーム １１６ 吊りバー １２０ リードフレーム素材（銅合金） １３０ 薄い銀めっき １４０ 銅めっき １５０ 部分銀めっき １６０ 半導体素子 １６１ 電極パッド（端子） １７０ 銀ペースト １８０ ワイヤ（金線） １９０、２２０ 銅酸化膜 ２００ 半導体装置 ２１０ 封止樹脂 ２２０Ａ Ｃｕ2 Ｏ ２２０Ｂ ＣｕＯ ２３０ 拡散された銀の存在領域 ７００ 樹脂封止型半導体装置 ７１０ リードフレーム ７１１ ダンパッド ７１２ インナリード ７１３ アウターリード ７１４ ダムバー ７１５ フレーム（枠）部 ７２０ 半導体素子 ７２１ 電極パッド（端子） ７３０ ワイヤ ７４０ 樹脂110 Lead frame 110A Lead frame made of copper alloy that has been externally processed 111 Die pad 112 Inner lead 113 Outer lead 114 Dam bar 115 Frame 116 Hanging bar 120 Lead frame material (copper alloy) 130 Thin silver plating 140 Copper plating 150 Partial silver plating 160 Semiconductor Element 161 Electrode pad (terminal) 170 Silver paste 180 Wire (gold wire) 190, 220 Copper oxide film 200 Semiconductor device 210 Encapsulation resin 220A Cu 2 O 220B CuO 230 Presence region of diffused silver 700 Resin encapsulation type semiconductor device 710 Lead frame 711 Dan pad 712 Inner lead 713 Outer lead 714 Dam bar 715 Frame (frame) part 720 Semiconductor element 721 Electrode pad (terminal) 730 wai 740 resin
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成８年３月２１日[Submission date] March 21, 1996
【手続補正１】[Procedure amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】特許請求の範囲[Correction target item name] Claims
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【特許請求の範囲】[Claims]
【手続補正２】[Procedure amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】発明の詳細な説明[Correction target item name] Detailed description of the invention
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【発明の詳細な説明】Detailed Description of the Invention
【０００１】[0001]
【産業上の利用分野】本発明は，封止樹脂とリードフレ
ームとの密着性を向上させた半導体装置と、それに用い
られるリードフレームに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having improved adhesion between a sealing resin and a lead frame, and a lead frame used for the same.
【０００２】[0002]
【従来の技術】従来より、半導体装置の組立部材として
用いられる（単層）リードフレームは、通常、コバー
ル、４２合金（４２％ニッケル−鉄合金）、銅系合金の
ような金属から成り、プレス法もしくはエッチング法に
より形成されていた。一般的なプラスチックパッケージ
であるＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）
用のリードフレームは、図７（ｂ）（イ）に示すよう
に、半導体素子を搭載するためのダイパッド７１１と、
ダイパッド７１１の周囲に設けられた半導体素子と結線
するためのインナーリード７１２と、該インナーリード
７１２に連続して外部回路との結線を行うためのアウタ
ーリード７１３、樹脂封止する際のダムとなるダムバー
７１４、リードフレーム７１０全体を支持するフレーム
（枠）部７１５等を備えている。そして、リードフレー
ム７１０は、図７（ａ）に示すように、ダイパッド部７
１１をインナーリード７１２形成面よりもダウンセット
した状態でダイパッド７１１に半導体素子７２０を搭載
し、半導体素子７２０の電極パッド（端子）７２１とイ
ンナーリード７１２の先端部とを金などのワイヤ７３０
で結線を行った後に、樹脂７４０にて封止して、ダムバ
ー７１４部の切断工程、アウターリード７１３部のフオ
ーミング工程を経て半導体装置７００を作製していた。
尚、図７（ｂ）（ロ）は、図７（ｂ）（イ）のＦ１−Ｆ
２における断面図である。2. Description of the Related Art Conventionally, a (single layer) lead frame used as an assembly member of a semiconductor device is usually made of a metal such as Kovar, 42 alloy (42% nickel-iron alloy), and copper alloy. It was formed by the etching method or the etching method. QFP (Quad Flat Package) which is a general plastic package
The lead frame for use has a die pad 711 for mounting a semiconductor element, as shown in FIGS.
Inner leads 712 for connecting to a semiconductor element provided around the die pad 711, outer leads 713 for connecting to an external circuit continuously to the inner leads 712, and a dam for resin sealing The dam bar 714, a frame (frame) portion 715 for supporting the entire lead frame 710, and the like are provided. Then, the lead frame 710, as shown in FIG.
The semiconductor element 720 is mounted on the die pad 711 in a state where 11 is set down from the surface on which the inner lead 712 is formed, and the electrode pad (terminal) 721 of the semiconductor element 720 and the tip of the inner lead 712 are connected to the wire 730 such as gold.
The semiconductor device 700 was manufactured through the step of cutting the dam bar 714 and the forming step of the outer lead 713 after sealing with the resin 740.
7 (b) and (b) are F1-F of FIG. 7 (b) (a).
It is sectional drawing in 2.
【０００３】このようなリードフレームは、半導体素子
７２０の電極パッド（端子）７２１とインナーリード７
１２の先端部とを金などのワイヤ７３０でワイヤボンデ
ィング（結線）、半導体素子の搭載の際に、強い結合力
と導電性を確保するために、貴金属めっきを、少なくと
もインナーリード７１２先端部、ダイパッド７１１の半
導体搭載側の面に施していた。貴金属めっきとしては、
銀めっき処理が一般には採られていた。Such a lead frame is composed of the electrode pad (terminal) 721 of the semiconductor element 720 and the inner lead 7.
The tip of 12 is wire-bonded with a wire 730 made of gold or the like, and at the time of mounting a semiconductor element, precious metal plating is applied to at least the tip of the inner lead 712 and the die pad in order to secure a strong bonding force and conductivity. It was applied to the semiconductor mounting side of 711. For precious metal plating,
A silver plating process was commonly used.
【０００４】従来のリードフレームにおいては、図６
（ａ）に示すように、ダイパッド１１１の半導体素子搭
載側とインナーリード１１２の先端部に、リードフレー
ム素材（銅合金）１２０上に、順に銅ストライクめっき
１４０、銀めっき１５０を形成しており、その部分銀め
っき工程は、図６（ｂ）に示すように、外形加工された
リードフレーム素材１２０に対し、脱脂、酸洗い等の前
処理（図６（ｂ）（イ））を行ってから、一般に下地め
っきとして０．１〜０．３μｍ厚程度の銅（Ｃｕ）スト
ライクめっきを施し（図６（ｂ）（ロ））、所望の領域
に１．５〜１０μｍ厚の銀めっきが施こした（図６
（ｂ）（ハ））後に、必要に応じて本来不要である部分
に薄くついた銀（モレなど）を除去する電解剥離処理を
してから、ベンゾトリアゾール系等の有機系薬品により
被膜を作り、酸化、水酸化による変色を防止する変色防
止処理（図６（ｂ）（ニ））を施すものであった。銀め
っき方法としては、マスキング治具を用いリードフレー
ムの所定領域を覆い露出部へ銀めっき液を吹きかけて部
分的に銀めっきを施す方法や、リードフレームに電着レ
ジストを塗膜した後、電着レジストを製版して所定の部
分のみ露出した状態でめっき液に浸漬してめっきを施す
方法等が用いられている。このように、マスキング治具
や電着レジストをマスクとしてリードフレームの所望の
部分にのみめっきを施すことを部分めっきと言ってお
り、図６に示す銀めっきのことを以下部分銀めっきと言
う。このような処理が施された銅合金を素材としたリー
ドフレームにおいては、半導体装置の作製工程や半導体
装置の実装工程においても、下地めっきが通常剥離する
ことはなく、半導体装置に使用された場合にも、銅スト
ライク部の剥離はないとされていた。FIG. 6 shows a conventional lead frame.
As shown in (a), a copper strike plating 140 and a silver plating 150 are sequentially formed on a lead frame material (copper alloy) 120 at the semiconductor element mounting side of the die pad 111 and the tip of the inner lead 112, In the partial silver plating step, as shown in FIG. 6B, after pretreatment such as degreasing and pickling (FIGS. 6B and 6B) is performed on the externally processed lead frame material 120. Generally, copper (Cu) strike plating having a thickness of about 0.1 to 0.3 μm is applied as a base plating (FIGS. 6B and 6B), and silver plating having a thickness of 1.5 to 10 μm is applied to a desired area. (Fig. 6
After (b) and (c)), if necessary, electrolytic stripping treatment is performed to remove the thin silver (more) that is originally not needed, and then a film is formed with an organic chemical such as benzotriazole. The discoloration preventing treatment (FIG. 6 (b) (d)) was performed to prevent discoloration due to oxidation and hydroxylation. As a silver plating method, a masking jig is used to cover a predetermined area of the lead frame to spray a silver plating solution on the exposed portion to partially perform silver plating, or after the lead frame is coated with an electrodeposition resist, an electrodeposition resist is applied. For example, a method is used in which a coating resist is made into a plate, and a predetermined portion is exposed so that the plating is dipped in a plating solution to perform plating. As described above, plating only on a desired portion of the lead frame using the masking jig or the electrodeposition resist as a mask is called partial plating, and the silver plating shown in FIG. 6 is hereinafter called partial silver plating. In the case of a lead frame made of a copper alloy that has been subjected to such a treatment, the base plating does not usually peel off even during the semiconductor device manufacturing process or the semiconductor device mounting process However, it was said that there was no peeling of the copper strike part.
【０００５】しかしながら、最近、このような処理が施
された銅合金を素材とするリードフレームを用いた場
合、リードフレームに起因したパッケージのデラミネー
ション（剥離）が半導体装置組み立て工程や実装工程で
生じていることが分かってきた。尚、パッケージのデラ
ミネーション（剥離）とは、ＩＣパッケージ内の各界
面、即ちＩＣチップ（半導体素子）と封止用樹脂との界
面、ダイボンディング剤とＩＣチップ（半導体素子）と
の界面等での剥離を言うが、リードフレームに起因する
デラミネーション（剥離）は封止用樹脂とダイパッド裏
面との界面での剥離等である。封止用樹脂とダイパッド
裏面との界面でのデラミネーション（剥離）の発生は、
銅合金を素材とするリードフレームの表面処理や組み立
て条件と密接な関係があることも次第に分かってきた。
銀めっきの下地めっきとして銅ストライクめっきが施こ
され、銀めっき後に電解剥離と変色防止が施された、銅
合金を素材とするリードフレームにおいては、ＩＣ（半
導体装置）組み立て工程中の加熱工程で、銅合金表面に
酸化膜が生じ、酸化膜と金属（銅合金）との間の密着強
度が不十分であることが、デラミネーション（剥離）発
生の原因と考えられている。However, recently, when a lead frame made of a copper alloy which has been subjected to such a treatment is used, delamination (peeling) of the package due to the lead frame occurs in a semiconductor device assembling process and a mounting process. I have come to understand that. The delamination of the package means each interface in the IC package, that is, the interface between the IC chip (semiconductor element) and the sealing resin, the interface between the die bonding agent and the IC chip (semiconductor element), and the like. The delamination caused by the lead frame is peeling at the interface between the sealing resin and the back surface of the die pad. The occurrence of delamination at the interface between the sealing resin and the back surface of the die pad
It has gradually become clear that there is a close relationship with the surface treatment and assembly conditions of lead frames made of copper alloy.
In a lead frame made of copper alloy, which has been subjected to copper strike plating as a base plating of silver plating, and electrolytic peeling and discoloration prevention have been applied after silver plating, the heating process during the IC (semiconductor device) assembly process It is considered that delamination occurs because an oxide film is formed on the surface of the copper alloy and the adhesion strength between the oxide film and the metal (copper alloy) is insufficient.
【０００６】このような状況のもと、封止用樹脂とダイ
パッド裏面との界面、さらには、封止用樹脂とリードフ
レーム全面との界面の接着強度を向上させ、デラミ発生
を防止するための方法として、特表平７−５０３１０３
号（特願平５−５１２６８８号）等が提案されている。
特表平７−５０３１０３号（特願平５−５１２６８８
号）では、クロムと亜鉛の混合体あるいはそれぞれの単
体からなる薄い被膜で全面を覆ったリードフレームが開
示されている。しかし、このリードフレームは、銀めっ
き部分も他の金属被膜で覆われるため、金ワイヤボンデ
ィング性が劣るという問題がある。Under these circumstances, the adhesive strength at the interface between the encapsulating resin and the back surface of the die pad, and further at the interface between the encapsulating resin and the entire surface of the lead frame is improved to prevent the occurrence of delamination. As a method, the special table 7-503103
Japanese Patent Application No. 5-512688 is proposed.
Japanese Patent Publication No. 7-503103 (Japanese Patent Application No. 5-512688)
No.) discloses a lead frame which is entirely covered with a thin film of a mixture of chromium and zinc or a simple substance of each. However, this lead frame has a problem that the gold wire bondability is poor because the silver-plated portion is also covered with another metal film.
【０００７】また、ＩＣ組み立て工程の条件は、組立を
実施するＩＣメーカーにより異なり、銅合金製リードフ
レームの表面酸化状態、酸化膜形成過程もメーカー毎に
異なる為、リードフレームに起因するデラミネーション
の発生状況がＩＣ組み立てメーカーによって異なってい
た。例えば、ベンゾトリアゾール系の被膜により、銅の
酸化、水酸化による変色を防止する処理方法では、ＩＣ
組み立て温度が低いメーカに対しては、デラミネーショ
ン防止効果が得られるが、ＩＣ組み立て温度が高いメー
カではデラミネーション防止効果が得られない。このた
め、従来はデラミネーションに対する対策をＩＣ組み立
て条件に合わせて各メーカ毎に行っていたのか実状で、
ＩＣの組み立て条件によらず、リードフレームに起因す
るデラミネーションに対応できる手段が求められてい
た。Further, the conditions of the IC assembling process differ depending on the IC maker who carries out the assembling, and the surface oxidation state of the copper alloy lead frame and the oxide film forming process also differ depending on the maker, so that delamination caused by the lead frame may occur. The occurrence situation was different depending on the IC assembly manufacturer. For example, in a treatment method for preventing discoloration due to copper oxidation or hydroxylation by a benzotriazole-based coating,
The delamination prevention effect can be obtained for a manufacturer whose assembly temperature is low, but the delamination prevention effect cannot be obtained for a manufacturer whose IC assembly temperature is high. For this reason, in the past, whether measures against delamination were taken by each maker according to the IC assembly conditions.
There has been a demand for means capable of coping with delamination caused by the lead frame, regardless of IC assembly conditions.
【０００８】[0008]
【発明が解決しようとする課題】このように、銅合金製
のリードフレームにおいては、リードフレーム表面の銅
酸化膜生成に起因した半導体装置（ＩＣ）におけるデラ
ミネーションを防止し、ＩＣの信頼性低下、ＩＣ組み立
て工程、実装工程における良品率の低下を防止すること
が望まれており、特に、ＩＣの組み立て条件によらず、
リードフレームに起因するデラミネーションの発生を防
止できるものが求められていた。本発明は、このような
状況のもと、ＩＣの組み立て条件によらず、リードフレ
ーム表面の銅酸化膜生成に起因したデラミネーションの
発生を防止でき、且つ、ボンディング性を損なわない銅
合金製のリードフレームを提供しようとするものであ
る。As described above, in the copper alloy lead frame, delamination in the semiconductor device (IC) due to the formation of a copper oxide film on the surface of the lead frame is prevented, and the reliability of the IC is reduced. It is desired to prevent a reduction in the non-defective rate in the IC assembly process and the mounting process.
There has been a demand for a material that can prevent delamination caused by the lead frame. Under the circumstances, the present invention is made of a copper alloy that can prevent delamination due to the formation of a copper oxide film on the surface of the lead frame and does not impair the bondability regardless of the IC assembly conditions. It is intended to provide a lead frame.
【０００９】[0009]
【課題を解決するための手段】本発明のリードフレーム
は、銅合金材を母材とし、ワイヤボンディング用ないし
ダイボンディング用の、銀、金、パラジウムの少なくと
も１つからなる部分貴金属めっきが施され、且つ、該部
分貴金属銀めっきの下地めっきとして銅ストライクめっ
きを施してある樹脂封止型の半導体装置用リードフレー
ムであって、少なくとも封止樹脂と接する側の銅合金材
表面の全部ないし所定の部分に銀、金、白金、パラジウ
ムの少なくとも１つからなる薄い貴金属めっきが施さ
れ、該薄い貴金属めっき上に銅めっきが形成されてお
り、且つ、銅めっき上の所定の領域に前記部分貴金属め
っきが形成されていることを特徴とするものである。そ
して、上記において、薄い貴金属めっきの厚みが０．５
μｍ以下、０．００１μｍ以上であることを特徴とする
ものである。そしてまた、上記における部分貴金属めっ
きは部分銀めっきであり、且つ、薄い貴金属めっきが薄
い銀めっきであることを特徴とするものである。本発明
のリードフレームの部分貴金属めっき方法は、銅合金材
を母材とし、ワイヤボンディング用ないしダイボンディ
ング用の、銀、金、パラジウムの少なくとも１つからな
る部分貴金属めっきが施され、且つ、該部分貴金属銀め
っきの下地めっきとして銅ストライクめっきを施してあ
る樹脂封止型の半導体装置用リードフレームの部分貴金
属めっき方法であって、少なくとも、順に、（Ａ）外形
加工された銅合金材からなるリードフレーム素材の表面
の全部ないし所定の部分に、厚みが０．００１〜０．５
μｍの銀、金、白金、パラジウムの少なくとも１つから
なる薄い貴金属めっきを施す工程と、（Ｂ）薄い貴金属
めっきが施されたリードフレームの表面の全部ないし少
なくとも前記部分貴金属めっき領域を含む部分に銅めっ
きを施す工程と、（Ｃ）銅めっきが施されたリードフレ
ームの表面の所定領域に部分貴金属めっきを施す工程と
を有することを特徴とするものである。そして、上記に
おいて、薄い貴金属めっきを、電解めっきないし無電解
めっきにより施すことを特徴とするものである。そして
また、上記において、部分貴金属めっきは部分銀めっき
であり、且つ、薄い貴金属めっきが薄い銀めっきである
ことを特徴とするものである。本発明の半導体装置は、
本発明のリードフレームを用いたことを特徴とするもき
であり、少なくとも封止用樹脂と接するリードフレーム
表面の全部ないし所定の部分の銅酸化膜形成領域におい
て、貴金属の濃度が、Ｘ線光電子分光による測定で、
０．１原子％以上〜２０原子％未満であることを特徴と
するものである。尚、上記において、部分貴金属めっき
とは、リードフレームを用いて半導体装置を作製する際
のワイヤボンディング用ないしダイボンディング用に、
リードフレームのインナーリード先端部やダイバッド部
の表面に貴金属めっきを施すもので、上記における所定
の領域とは、このインナーリード先端部やダイバッド部
の表面領域を言う。一般には、マスキング治具を用い、
リードフレームの所定の領域にのみめっき液を吹きつけ
て、または電着レジスト等により所定の領域のみをめっ
き液に接するようにしてリードフレーム全体をめっき液
に浸しながら、リードフレームの所定領域にのみめっき
を施す。The lead frame of the present invention is formed of a copper alloy material as a base material and is subjected to partial precious metal plating for wire bonding or die bonding, which is made of at least one of silver, gold and palladium. A resin-encapsulated lead frame for a semiconductor device, which has been subjected to copper strike plating as an undercoat of the partial noble metal silver plating, wherein at least the entire or predetermined surface of the copper alloy material on the side in contact with the sealing resin A thin noble metal plating made of at least one of silver, gold, platinum, and palladium is applied to a part, copper plating is formed on the thin noble metal plating, and the partial noble metal plating is provided in a predetermined region on the copper plating. Are formed. And in the above, the thickness of the thin precious metal plating is 0.5.
It is characterized by being less than or equal to μm and greater than or equal to 0.001 μm. The partial noble metal plating in the above is partial silver plating, and the thin noble metal plating is thin silver plating. A method for partially plating a noble metal of a lead frame according to the present invention is performed by using a copper alloy material as a base material and performing a partial noble metal plating of at least one of silver, gold, and palladium for wire bonding or die bonding, and A partial precious metal plating method for a resin-encapsulated lead frame for a semiconductor device, in which copper strike plating is applied as an undercoat of a partial precious metal silver plating, which is composed of at least (A) an externally processed copper alloy material. The thickness of 0.001 to 0.5 is applied to the entire surface of the lead frame material or to a predetermined portion of the surface.
the step of applying a thin noble metal plating of at least one of μm of silver, gold, platinum, and palladium, and (B) the entire surface of the lead frame plated with the thin noble metal or at least a part including the partial noble metal plating region. It is characterized by including a step of performing copper plating and (C) a step of performing partial noble metal plating on a predetermined region of the surface of the lead frame on which the copper plating has been performed. In the above, thin precious metal plating is performed by electrolytic plating or electroless plating. Further, in the above, the partial precious metal plating is a partial silver plating, and the thin precious metal plating is a thin silver plating. The semiconductor device of the present invention
The lead frame of the present invention is used, wherein the concentration of the noble metal is X-ray photoelectron in at least the entire or predetermined portion of the copper oxide film forming region of the lead frame surface in contact with the sealing resin. By spectroscopic measurement,
It is characterized by being 0.1 atomic% or more and less than 20 atomic%. In the above, the partial precious metal plating is used for wire bonding or die bonding when manufacturing a semiconductor device using a lead frame,
Noble metal plating is applied to the surface of the inner lead tip portion or the dibad portion of the lead frame. The predetermined area in the above means the surface area of the inner lead tip portion or the dibad portion. Generally, using a masking jig,
Only by spraying the plating solution only on the specified area of the lead frame, or by immersing the entire lead frame in the plating solution so that only the specified area is in contact with the plating solution with an electrodeposition resist, etc. Apply plating.
【００１０】[0010]
【作用】本発明のリードフレームは、上記のような構成
にすることにより、ＩＣの組み立て条件によらず、リー
ドフレームに起因する半導体装置における封止樹脂のデ
ラミネーションの発生を防止でき、且つ、ボンディング
性を損なわない銅合金製のリードフレームの提供を可能
としている。詳しくは、少なくとも封止樹脂と接する側
の銅合金材表面の全部ないし所定の部分に薄い貴金属め
っきが施され、該薄い貴金属めっき上に銅めっきが形成
されており、且つ、銅めっき上の所定の領域に部分貴金
属めっきが形成されていることにより、リードフレーム
表面の銅酸化膜に起因したデラミネーション（剥離）を
防止できるものとしている。即ち、薄い貴金属めっきが
銅合金材の表面に施された箇所においては、貴金属はＩ
Ｃ組み立て工程中における加熱により銅酸化膜内部に拡
散するため、銅合金材の表面に施された薄い貴金属めっ
きは銅めっき部および銅合金材の酸化を抑えて、酸化膜
厚を低減するとともに、酸化膜生成の際にはＣｕＯより
ＣＵ２Ｏの生成を優先させ、酸化膜自体が破壊されにく
くなり、封止樹脂とのデラミネーションの発生を抑える
ことができるのである。特に、半導体素子を搭載する側
でないダイパッド裏面の銅部表面に、薄い貴金属めっ
き、銅めっきを順次施してある場合には、少なくとも、
ダイパッド裏面でのリードフレーム表面の銅酸化膜に起
因したデラミネーション（剥離）を効果的に防止できる
ものとしている。また、薄い貴金属めっき、銅めっき
が、リードフレーム表面全体に施した場合には、ダイパ
ッド裏面を含みリードフレームと封止用樹脂との全ての
界面でのリードフレーム表面の銅酸化膜に起因したデラ
ミネーション（剥離）を防止できるものとしており、且
つ、ダイパッドの裏面のみに部分的にめっきを施す場合
と異なり、めっき用治具等を必要としないものとしてい
る。そして、薄い貴金属めっきの厚みを０．５μｍ以
下、０．００１μｍ以上としていることにより、デラミ
ネーション（剥離）の防止の効果が得られる適切な膜厚
としている。即ち、薄い貴金属めっきの厚みが０．００
１μｍより薄い場合には、銅ストライクめっき中に拡散
する銀の濃度が小さく、上記効果が得られず、厚みを
０．５μｍより厚くするとめっき時間と費用がかかるば
かりでなく、ＩＣ組み立て工程で貴金属が銅酸化膜内部
に十分に拡散しないため封止樹脂との密着強度が劣化す
ると考えられる。また、薄い貴金属めっきが銅めっきの
下に施されているため、その後の貴金属めっき工程、ワ
イヤボンディング工程は、従来の処理と同様の工程にて
処理でき、貴金属めっきの密着性も問題なく、ワイヤボ
ンディング適性も問題がない。また、半田めっき性に関
しては、半田めっきの前処理として行われる酸洗浄や化
学研磨処理によって銅酸化膜が除去される為、従来の図
６（ａ）に示すリードフレームとかわらず良好である。
更に、部分貴金属めっきを施す際に、不要部分に貴金属
モレが生じることが多々あり、これを電解剥離により除
去をすることがあるが、薄い貴金属めっきが銅めっきの
下に施されているため、薄い貴金属めっき部への影響を
与えずに貴金属モレ部のみを除去することができる。ま
た、薄い貴金属めっきが銅めっきの下に施されているた
め、図６（ａ）に示す従来のものと同じ外観を確保でき
る。また、部分貴金属めっきは部分銀めっきであり、且
つ、薄い貴金属めっきが、薄い銀めっきであることによ
り、従来使用されている電解めっき方法や無電解めっき
方法により、比較的簡単にめっきを安定的に行うことが
でき、生産コストを下げることができる。With the lead frame of the present invention having the above-mentioned structure, it is possible to prevent the occurrence of delamination of the sealing resin in the semiconductor device due to the lead frame, regardless of the IC assembly conditions, and It is possible to provide a lead frame made of copper alloy that does not impair the bondability. Specifically, at least all or a predetermined portion of the surface of the copper alloy material on the side in contact with the sealing resin is plated with a thin noble metal, and the copper plating is formed on the thin noble metal plating. By forming the partial noble metal plating in the area (2), delamination (peeling) due to the copper oxide film on the surface of the lead frame can be prevented. That is, in the place where a thin precious metal plating is applied to the surface of the copper alloy material, the precious metal is I
Since the copper noble metal plating applied to the surface of the copper alloy material suppresses the oxidation of the copper plated part and the copper alloy material to reduce the oxide film thickness, since the copper noble metal plating is diffused into the copper oxide film by heating during the assembly process. When forming the oxide film, CU 2 O is given priority over CuO, the oxide film itself is less likely to be destroyed, and delamination with the sealing resin can be suppressed. In particular, on the surface of the copper portion on the back surface of the die pad that is not the side on which the semiconductor element is mounted, at least when thin precious metal plating and copper plating are sequentially performed,
It is supposed that delamination (peeling) due to the copper oxide film on the surface of the lead frame on the back surface of the die pad can be effectively prevented. In addition, when a thin precious metal plating or copper plating is applied to the entire surface of the lead frame, the depletion caused by the copper oxide film on the surface of the lead frame at all interfaces between the lead frame and the sealing resin including the back surface of the die pad. Lamination (peeling) can be prevented, and unlike the case where only the back surface of the die pad is partially plated, no plating jig or the like is required. The thickness of the thin precious metal plating is set to 0.5 μm or less and 0.001 μm or more, so that an appropriate film thickness that can obtain the effect of preventing delamination (peeling) is obtained. That is, the thickness of the thin precious metal plating is 0.00
If the thickness is less than 1 μm, the concentration of silver diffused during copper strike plating is small and the above effect cannot be obtained. If the thickness is more than 0.5 μm, not only the plating time and cost will be increased, but also precious metal in the IC assembly process. Is not sufficiently diffused inside the copper oxide film, it is considered that the adhesion strength with the sealing resin deteriorates. In addition, since the thin precious metal plating is applied under the copper plating, the subsequent precious metal plating process and wire bonding process can be performed in the same process as the conventional process, and the adhesion of the precious metal plating does not cause any problems. There is no problem in bonding suitability. Further, regarding the solder plating property, the copper oxide film is removed by the acid cleaning or the chemical polishing process which is performed as the pretreatment of the solder plating, and therefore, the solder plating property is good regardless of the conventional lead frame shown in FIG.
Furthermore, when performing partial noble metal plating, noble metal leak often occurs in unnecessary parts, and this may be removed by electrolytic peeling, but since a thin noble metal plating is applied below the copper plating, Only the precious metal leak portion can be removed without affecting the thin precious metal plating portion. Further, since the thin precious metal plating is applied under the copper plating, the same appearance as the conventional one shown in FIG. 6A can be secured. In addition, since the partial noble metal plating is the partial silver plating and the thin precious metal plating is the thin silver plating, it is possible to stabilize the plating relatively easily by the electrolytic plating method or the electroless plating method that has been conventionally used. Can be carried out, and the production cost can be reduced.
【００１１】本発明のリードフレームの部分貴金属めっ
き方法は、上記のような構成にすることにより、本発明
のリードフレームの製造を可能とするものである。そし
て、電解めっきないし無電解めっきにより薄い貴金属め
っきを施すことにより、薄い貴金属めっきの膜厚の制御
を簡単なものとしている。特に、上記において、薄い貴
金属めっき、銅めっきをリードフレーム全体に施す場合
には、マスキング治具を必要とせず各めっきの被膜生成
作業を簡単なものとできる。尚、薄い貴金属めっきを施
す方法としては、電解めっき、無電解めっきいずれも使
用できるが、めっき速度を速くして、めっき厚を精度良
く制御するためには電解めっき法が適し、複雑な形状で
あるリードフレームに対するめっきのつきまわり性を求
める場合には無電解めっき法が適している。上記におい
て、部分貴金属めっきは部分銀めっきであり、且つ、薄
い貴金属めっきが薄い銀めっきであることにより、従来
使用の電解めっき方法や無電解めっき方法により比較的
簡単に、めっきを安定的に行うことができるものとして
いる。同時に、金めっきや白金めっきに比べ生産コスト
を下げることができる。The method of partially plating a noble metal of a lead frame according to the present invention makes it possible to manufacture the lead frame of the present invention with the above-mentioned structure. The thin precious metal plating is applied by electrolytic plating or electroless plating to simplify the control of the film thickness of the thin precious metal plating. In particular, in the above case, when thin noble metal plating or copper plating is applied to the entire lead frame, a masking jig is not required, and the work of forming a coating film for each plating can be simplified. As a method of applying a thin precious metal plating, either electrolytic plating or electroless plating can be used. However, the electrolytic plating method is suitable for increasing the plating speed and accurately controlling the plating thickness, and the complicated shape is used. The electroless plating method is suitable for obtaining the throwing power of the plating on a certain lead frame. In the above, since the partial noble metal plating is the partial silver plating and the thin noble metal plating is the thin silver plating, the plating is stably performed relatively easily by the conventionally used electrolytic plating method or electroless plating method. It is supposed to be possible. At the same time, the production cost can be reduced compared to gold plating or platinum plating.
【００１２】本発明の半導体装置は、上記本発明のリー
ドフレームを用いることにより、ワイヤボンディング工
程における熱処理等を経て、封止樹脂と接するリードフ
レーム表面の全部ないし所定の部分に、金、銀、白金、
パラジウムの少なくとも１つと銅酸化膜からなる領域を
もつ表面部を形成でき、これにより、封止樹脂と接する
部分の剥離を防止できるものとしている。そして、封止
樹脂と接するリードフレーム表面の全部ないし所定の部
分の銅酸化膜形成領域において、貴金属の濃度が、Ｘ線
光電子分光による測定で、０．１原子％以上であること
により、銅酸化膜ないし銅酸化膜と銅合金との境での破
壊強度を充分なものとでき、２０原子％未満であること
により、封止樹脂との密着性が劣る銀の特質をカバーす
ることができ、銅酸化膜と封止樹脂との密着性を充分な
ものとしている。In the semiconductor device of the present invention, by using the lead frame of the present invention, heat treatment or the like in the wire bonding step is performed, and gold, silver, or silver is formed on all or predetermined portions of the lead frame surface in contact with the sealing resin. platinum,
A surface portion having a region composed of at least one of palladium and a copper oxide film can be formed, whereby peeling of a portion in contact with the sealing resin can be prevented. When the concentration of the noble metal is 0.1 atom% or more as measured by X-ray photoelectron spectroscopy in the copper oxide film forming region on the entire surface or a predetermined portion of the lead frame surface in contact with the sealing resin, the copper oxide The breaking strength at the boundary between the film or the copper oxide film and the copper alloy can be made sufficient, and when it is less than 20 atomic%, it is possible to cover the characteristic of silver having poor adhesion to the sealing resin, Adhesion between the copper oxide film and the sealing resin is sufficient.
【００１３】[0013]
【実施例】本発明のリードフレームの実施例を以下、図
にそって説明する。先ず、実施例１のリードフレームを
挙げて説明する。図１は本発明のリードフレームの実施
例１を示したもので、図１（ｂ）はその平面図を、図１
（ａ）はＡ１−Ａ２における断面の要部拡大図である。
図１中、１１０はリードフレーム、１１１はダイパッ
ド、１１２はインナーリード、１１３はアウターリー
ド、１１４はダムバー、１１５はフレーム、１１６は吊
りバー、１２０はリードフレーム素材（銅合金）、１３
０は薄い銀めっき、１４０は銅めっき、１５０は部分銀
めっきである。本実施例のリードフレーム１１０は、厚
さ０．１５ｍｍの銅合金材（古河電気工業株式会社製Ｅ
ＦＴＥＣ６４Ｔ−１／２Ｈ材）からエッチング加工によ
り図１（ｂ）のような形状に外形加工されたリードフレ
ーム素材１２０に対し、薄い銀めっき１３０、銅めっき
１４０を順次、リードフレームの表面全面に施してか
ら、この上に所定の領域にのみに部分銀めっき１５０を
施したものである。本実施例においては、薄い銀めっき
を厚さ０．０１μｍ、銅めっきを厚さ０．１μｍ、部分
銀めっきを厚さ３μｍとしたが、銅めっきの厚さとして
は、０．１〜０．３μｍ、部分銀めっきの厚さとしては
１．５〜１０μｍ、薄い銀めっき１３０の厚さとしては
０．００１μｍ以上、０．５μｍ以下が好ましい。ま
た、リードフレーム素材１２０として古河電気工業株式
会社製の銅合金ＥＦＴＥＣ６４Ｔ−１／２Ｈ材を用いて
いるが、本発明はこれに限定されることはなく、他の銅
合金でも良い。Embodiments of the lead frame of the present invention will be described below with reference to the drawings. First, the lead frame of Example 1 will be described. 1 shows a first embodiment of a lead frame of the present invention, and FIG. 1 (b) is a plan view thereof.
(A) is an enlarged view of a main part of a cross section taken along line A1-A2.
In FIG. 1, 110 is a lead frame, 111 is a die pad, 112 is an inner lead, 113 is an outer lead, 114 is a dam bar, 115 is a frame, 116 is a suspension bar, 120 is a lead frame material (copper alloy), 13
0 is thin silver plating, 140 is copper plating, and 150 is partial silver plating. The lead frame 110 of this embodiment is a copper alloy material (E manufactured by Furukawa Electric Co., Ltd.) having a thickness of 0.15 mm.
Thin lead plating 130 and copper plating 140 are sequentially applied to the entire surface of the lead frame on a lead frame material 120 that has been externally processed into a shape as shown in FIG. 1B by etching from FTEC64T-1 / 2H material). Then, the partial silver plating 150 is applied only to a predetermined area on the above. In this embodiment, the thin silver plating has a thickness of 0.01 μm, the copper plating has a thickness of 0.1 μm, and the partial silver plating has a thickness of 3 μm, but the thickness of the copper plating is 0.1 to 0. 3 μm, the thickness of the partial silver plating is 1.5 to 10 μm, and the thickness of the thin silver plating 130 is preferably 0.001 μm or more and 0.5 μm or less. Further, although the copper alloy EFTEC64T-1 / 2H made by Furukawa Electric Co., Ltd. is used as the lead frame material 120, the present invention is not limited to this, and other copper alloys may be used.
【００１４】本実施例のリードフレームは、図１（ａ）
に示すように、外形加工されたリードフレーム素材１２
０に対し、薄い銀めっき１３０、銅１４０を順次、全面
に施してから、この上に所定の領域にのみに部分銀めっ
き１５０を施したものであり、薄い銀めっき１３０を設
けていることにより、母材金属（銅合金材）と酸化膜と
の密着性が向上し、結果として、半導体装置を作製する
場合には封止樹脂とのデラミネーションの発生を抑える
ことができるものとしている。The lead frame of this embodiment is shown in FIG.
As shown in, the lead frame material 12 is
In contrast to 0, a thin silver plating 130 and a copper 140 are sequentially applied to the entire surface, and then a partial silver plating 150 is applied only to a predetermined area on the entire surface. By providing the thin silver plating 130, The adhesion between the base metal (copper alloy material) and the oxide film is improved, and as a result, delamination with the sealing resin can be suppressed when a semiconductor device is manufactured.
【００１５】次に、実施例２のリードフレームを挙げて
説明する。図２は本発明のリードフレームの実施例２を
示したもので、図２（ｂ）はその下面図を、図２（ａ）
はＡ３−Ａ４における断面の要部拡大図である。図２
中、１１０はリードフレーム、１１１はダイパッド、１
１２はインナーリード、１１３はアウターリード、１１
４はダムバー、１１５はフレーム、１２０はリードフレ
ーム素材（銅合金）、１３０は薄い銀めっき、１４０は
銅めっき、１５０は部分銀めっきである。本実施例のリ
ードフレームが、実施例１と異なるのは、薄い銀めっき
１３０を半導体素子を搭載する側でないダイパッド１１
１の裏面にのみ施した点のみで、他は実施例１と同じで
ある。Next, the lead frame of the second embodiment will be described. 2 shows a second embodiment of the lead frame of the present invention, and FIG. 2 (b) is a bottom view thereof, and FIG.
FIG. 4 is an enlarged view of a main part of a cross section taken along line A3-A4. FIG.
Inside, 110 is a lead frame, 111 is a die pad, 1
12 is an inner lead, 113 is an outer lead, 11
4 is a dam bar, 115 is a frame, 120 is a lead frame material (copper alloy), 130 is thin silver plating, 140 is copper plating, and 150 is partial silver plating. The lead frame of this embodiment differs from that of the first embodiment in that the thin silver plating 130 is not on the side on which the semiconductor element is mounted.
1 is the same as Example 1 except that it was applied only to the back surface of No. 1.
【００１６】次に、実施例１、実施例２と併せ、変形例
と比較例についての封止樹脂密着強度、酸化膜剥れ状態
を評価した。変形例１、変形例２、変形例３は、それぞ
れ実施例１と同じ構成のもので薄い銀めっきの厚さを
０．１μｍ、０．５μｍ、１．０μｍとしたものであ
る。また、比較例１としては、図６に示す従来例で変色
防止処理を施したものを、比較例２としては、従来例に
おいて変色防止処理を施して無い、ものを用いた。尚、
上記実施例１、実施例２、変形例、比較例とも、銅めっ
きの厚さは０．１μｍ、部分銀めっきの厚さ３μｍとし
た。封止樹脂密着強度は、封止樹脂密着強度評価用の専
用フレーム（ベタ状板）に実施例１、各変形例および比
較例と同じ表面処理を施し、ワイヤボンディング想定加
熱条件、２８０°Ｃ、３分間の条件で加熱した後、銅合
金材面に一定面積の封止樹脂を成形し、シエア法により
密着強度を測定した。さらに、試験後の封止樹脂への酸
化膜の付着状態を観察し、母材からの酸化膜剥がれを評
価した。シエア法による密着強度の判定、酸化膜剥れの
判定は、２．０Ｎ／ｍｍ２以上を可（○）とし、２．０
Ｎ／ｍｍ２未満を不可（×）とした。 Next, together with Examples 1 and 2, the sealing resin adhesion strength and oxide film peeling state of the modified example and the comparative example were evaluated. The modification 1, modification 2, and modification 3 each have the same configuration as that of the embodiment 1, and have thin silver plating thicknesses of 0.1 μm, 0.5 μm, and 1.0 μm. Further, as Comparative Example 1, the one in which the discoloration prevention treatment was applied in the conventional example shown in FIG. 6 was used, and in Comparative Example 2, the one in which the discoloration prevention treatment was not applied in the conventional example was used. still,
The thickness of the copper plating was 0.1 μm and the thickness of the partial silver plating was 3 μm in each of the above-mentioned Examples 1, 2 and the modified examples and the comparative example. The sealing resin adhesion strength was determined by subjecting a dedicated frame (solid plate) for evaluating the sealing resin adhesion strength to the same surface treatment as in Example 1, each modified example and comparative example, and assuming the wire bonding heating conditions at 280 ° C. After heating under the condition of 3 minutes, a sealing resin having a certain area was molded on the surface of the copper alloy material, and the adhesion strength was measured by the shear method. Further, the adhesion state of the oxide film to the sealing resin after the test was observed, and the peeling of the oxide film from the base material was evaluated. The adhesion strength and the oxide film peeling by the shear method are 2.0 N / mm 2 or more (OK), and 2.0
A value less than N / mm 2 was regarded as unacceptable (x).
【００１７】表１に示すように、薄い銀めっきを行っ
た、実施例１、実施例２、変形例１、変形例２は、封止
樹脂密着強度、酸化膜剥れの点において、図６に示す方
法により部分銀めっきが施された比較例１よりも優れて
いることが分かった。また、比較例２は、酸化膜剥れの
評価において、実施例１、実施例２、変形例１、変形例
２に劣ることが分かった。また、変形例３は封止樹脂密
着強度の点で実施例１、実施例２、変形例１、変形例２
に劣り、薄い銀めっきの厚さが厚過ぎても薄い銀めっき
を設けることの効果がなくなることも分かる。これよ
り、上記本発明の実施例１、実施例２、変形例１、変形
例２リードフレームが、図６（ｂ）に示す工程にてめっ
きされた従来のリードフレームに比べ、半導体装置に用
いられた際には、銅酸化膜生成に起因するＩＣパッケー
ジのデラミネーションの発生を効果的に抑えることがで
きると判断される。As shown in Table 1, Examples 1, 2 and 1 and 2 which were thinly plated with silver are shown in FIG. 6 in terms of sealing resin adhesion strength and oxide film peeling. It was found to be superior to Comparative Example 1 in which partial silver plating was applied by the method shown in FIG. Further, it was found that Comparative Example 2 was inferior to Example 1, Example 2, Modification 1 and Modification 2 in evaluation of oxide film peeling. In addition, the modified example 3 is different from the example 1 in the sealing resin adhesion strength in the example 1, the example 2, the modified example 1, and the modified example 2.
It is also understood that the effect of providing thin silver plating is lost even if the thickness of thin silver plating is too thick. Thus, the lead frames of Example 1, Example 2, Modification 1 and Modification 2 of the present invention are used in the semiconductor device as compared with the conventional lead frame plated in the step shown in FIG. 6B. In this case, it is judged that the delamination of the IC package due to the formation of the copper oxide film can be effectively suppressed.
【００１８】次に、本発明のリードフレームの貴金属部
分めっき方法の実施例を挙げ、図３に基づいて簡単に説
明する。本実施例のリードフレームの貴金属部分めっき
方法は、上記本発明のリードフレームの実施例１を作製
するためのめっき方法である。尚、図３図は、図１
（ａ）に相当する部分である。先ず、エッチングにて外
形加工された銅合金からなるリードフレーム１１０Ａの
全面をアルカリ水溶液で電解脱脂し、純水で洗浄した
後、酸性液で表面に形成されている酸化膜を除去する酸
活性化処理を行い、リードフレーム素材１２０である銅
合金の表面を活性化して、再度純水で洗浄した。（図３
（ａ）） 次いで、薄い銀めっき１３０をリードフレーム１１０Ａ
の全面に、厚さ０．０１μｍの厚さで形成した。（図３
（ｂ）） 尚、この薄い銀めっきは、シアン化銀水溶液中に浸漬し
て電解めっきにて行った。本発明のリードフレームの実
施例２を作製する場合には、薄い銀めっきをダイパッド
部のみに施すため、所定の部分をマスキングしてめっき
を行う必要がある。次いで、アルカリ中和処理、酸活性
化処理を経て、純水でリードフレーム表面を洗浄した
後、銀めっきが施されたリードフレーム１１０Ａの全面
に、液温５０゜Ｃで約２０秒間シアン化銅めっきを行
い、０．１μｍの厚さで銅めっき１４０を施した。（図
３（ｃ）） 次いで、純水で銅めっき１４０が施されたリードフレー
ム１１０Ａ表面を洗浄した後、銀めっき処理時に不要な
部分に銀が析出しないように、全面に銀の置換防止処理
を行なった。置換防止処理は、室温で有機硫黄系の溶液
に浸し薄い被膜を形成したものである。次いで、リード
フレームの半導体素子を搭載する側のダイバッド部、イ
ンナーリード先端領域のみを露出させるようにマスキン
グ治具で覆い、リードフレームを陰極として、めっき液
をノズルより噴射により吹きかける方式の部分めっきに
より、厚さ３μｍの銀めっきをードフレームの所定の領
域に施した後、純水でリードフレームを洗浄し、温風で
乾燥して、実施例のリードフレームを得た。（図３
（ｄ））Next, an example of the method for partially plating a noble metal of a lead frame of the present invention will be given and briefly described with reference to FIG. The noble metal partial plating method for the lead frame of this example is a plating method for producing the above-described lead frame of Example 1 of the present invention. It should be noted that FIG.
This is a part corresponding to (a). First, after electrolytically degreasing the entire surface of the lead frame 110A made of a copper alloy that has been externally processed by etching with an alkaline aqueous solution and washing with pure water, acid activation for removing an oxide film formed on the surface with an acid solution After the treatment, the surface of the copper alloy that is the lead frame material 120 was activated and washed again with pure water. (Fig. 3
(A)) Next, the thin silver plating 130 is applied to the lead frame 110A.
Was formed on the entire surface of the substrate with a thickness of 0.01 μm. (Fig. 3
(B)) This thin silver plating was performed by electrolytic plating by immersing it in an aqueous solution of silver cyanide. When manufacturing Example 2 of the lead frame of the present invention, since thin silver plating is applied only to the die pad portion, it is necessary to mask and plate a predetermined portion. Next, after the alkali neutralization treatment and the acid activation treatment, the surface of the lead frame is washed with pure water, and then the entire surface of the silver-plated lead frame 110A is copper cyanide at a liquid temperature of 50 ° C. for about 20 seconds. The plating was performed, and the copper plating 140 was applied to a thickness of 0.1 μm. (FIG. 3 (c)) Next, after cleaning the surface of the lead frame 110A that has been plated with copper 140 with pure water, silver substitution prevention treatment is performed on the entire surface so that silver does not deposit on unnecessary portions during silver plating treatment. Was done. The substitution prevention treatment is a thin film formed by immersing the solution in an organic sulfur solution at room temperature. Then, by covering with a masking jig so as to expose only the die pad portion of the lead frame on which the semiconductor element is mounted and the inner lead tip region, the lead frame is used as a cathode and the plating solution is sprayed from a nozzle by partial plating. After a silver plating having a thickness of 3 μm was applied to a predetermined region of the lead frame, the lead frame was washed with pure water and dried with warm air to obtain a lead frame of the example. (Fig. 3
(D))
【００１９】次に、本発明の半導体装置の実施例を挙
げ、図にそって説明する。実施例１の半導体装置は、上
記本発明のリードフレームの実施例１を用いたもので、
図４（ａ）はその概略断面図であり、図４（ｂ）は図４
（ａ）のＢ１、Ｂ２における断面の状態を拡大して示し
たものである。尚、説明を分かり易くするため、図６
（ａ）に示す従来のリードフレームを用い、本実施例の
半導体装置と同じ条件にて作製した半導体装置における
Ｂ１、Ｂ２に相当する位置の状態を拡大して図４（ｃ）
に示しておく。本実施例の半導体装置は、図５（ｃ）に
示すワイヤボンディング工程、図５（ｄ）に示す樹脂封
止工程を経て作製されたものである。Next, an example of a semiconductor device of the present invention will be given and described with reference to the drawings. The semiconductor device of Example 1 uses the above-described Example 1 of the lead frame of the present invention.
4 (a) is a schematic sectional view thereof, and FIG. 4 (b) is shown in FIG.
It is an enlarged view of the cross-sectional state of B1 and B2 in (a). In addition, in order to make the explanation easy to understand, FIG.
FIG. 4C is an enlarged view of the state of positions corresponding to B1 and B2 in the semiconductor device manufactured under the same conditions as the semiconductor device of this embodiment using the conventional lead frame shown in FIG.
Will be shown. The semiconductor device of the present embodiment is manufactured through the wire bonding process shown in FIG. 5C and the resin sealing process shown in FIG. 5D.
【００２０】実施例２の半導体装置は、上記本発明のリ
ードフレームの実施例２を用いたもので、実施例１と同
様、ワイヤボンディング工程、樹脂封止工程を経て作製
されたものであるが、外見上は、図４に示す実施例１と
同じであるが、表面の銅酸化膜の厚さや、拡散された銀
の存在する領域が異なる。実施例１、実施例２の半導体
装置とも、デラミネーションの発生は見られなかった。The semiconductor device of Example 2 uses the above-described Example 2 of the lead frame of the present invention and is manufactured through the wire bonding step and the resin sealing step as in Example 1. The appearance is the same as that of the first embodiment shown in FIG. 4, but the thickness of the copper oxide film on the surface and the region where the diffused silver exists are different. No occurrence of delamination was observed in the semiconductor devices of Examples 1 and 2.
【００２１】前述の実施例のリードフレームを用いて半
導体装置（ＩＣパッケージ）を作製する工程を図５を用
いて簡単に説明しておく。先ず、図１に示す実施例のリ
ードフレーム１１０のダイパッド１１１を、ダウンセッ
ト加工し（図５（ａ））、ダイパッド１１１上に銀ペー
スト１７０を介して半導体素子１６０を接合する。（図
５（ｂ）） 次いで、銀ペースト１７０を加熱キュアした後、半導体
素子１６０の電極パッド（端子）１６１とリードフレー
ム１１０の部分銀めっき１４０が施されたインナーリー
ド１１２の先端とをワイヤ（金線）１８０でワイヤボン
ディングして電気的に結線する。（図５（ｃ）） 次いで、樹脂封止、ダムバーの除去、アウターリードの
フォーミング処理、半田めっきを経て、半導体装置２０
０を得る。（図５（ｄ）） 以上の工程を経て、図１に示すリードフレーム１１０表
面の銅めっき１４０、ないしリードフレーム素材（銅合
金）１２０の一部は酸化され、図５（ｃ）に示す銅酸化
膜１９０を形成する。これと同時に、図１に示す銅めっ
き１４０下の薄い銀めっき１３０は、銅酸化膜１９０お
よびリードフレーム素材（銅合金）１２０中へ拡散され
る。A process of manufacturing a semiconductor device (IC package) using the lead frame of the above-mentioned embodiment will be briefly described with reference to FIG. First, the die pad 111 of the lead frame 110 of the embodiment shown in FIG. 1 is downset processed (FIG. 5A), and the semiconductor element 160 is bonded onto the die pad 111 via the silver paste 170. (FIG. 5B) Next, after the silver paste 170 is cured by heating, the electrode pads (terminals) 161 of the semiconductor element 160 and the tips of the inner leads 112 of the lead frame 110 on which the partial silver plating 140 is applied are formed by a wire ( A gold wire) 180 is wire-bonded and electrically connected. (FIG. 5C) Next, the semiconductor device 20 is subjected to resin sealing, dam bar removal, outer lead forming processing, and solder plating.
Get 0. (FIG. 5D) Through the above steps, the copper plating 140 on the surface of the lead frame 110 shown in FIG. 1 or a part of the lead frame material (copper alloy) 120 is oxidized and the copper shown in FIG. An oxide film 190 is formed. At the same time, the thin silver plating 130 under the copper plating 140 shown in FIG. 1 is diffused into the copper oxide film 190 and the lead frame material (copper alloy) 120.
【００２２】上記実施例のリードフレームを用いた半導
体装置２００の作製方法においては、図５（ｃ）の段階
で、加熱されたことによってダイパッド１１１における
銅の表面では、Ｘ線光電子分光分析（ＥＳＣＡ）で観察
すると、図４（ｂ）に示すようになっていた。尚、図４
（ｂ）中、２２０は銅酸化膜、２３０は拡散された銀の
存在領域、１２０はリードフレーム素材（銅合金）を示
している。図１に示す薄い銀めっき１３０の銀は、銅酸
化膜２２０及びリードフレーム素材（銅合金）２２０中
に拡散され、拡散された銀の存在領域２３０は、図４
（ｂ）に示すよう、銅酸化膜領域２２０とリードフレー
ム素材（銅合金）２１０の一部に跨がる。銅酸化膜領域
２２０は、ＣｕＯ２２０Ｂを表面側にして、ＣｕＯ２２
０ＢとＣｕ２Ｏ２２０Ａを形成する。薄い銀めっき１３
０の膜厚さ、加熱条件を変えることにより、銅酸化膜の
内側に銀が拡散している状態が異なる。銀の拡散は銅酸
化膜２２０のみならずリードフレーム素材（銅合金）１
２０まで及ぶ。In the method of manufacturing the semiconductor device 200 using the lead frame of the above embodiment, the copper surface of the die pad 111 which has been heated at the stage of FIG. 5C is subjected to X-ray photoelectron spectroscopy (ESCA). ), It was as shown in FIG. FIG.
In (b), 220 indicates a copper oxide film, 230 indicates an area where diffused silver exists, and 120 indicates a lead frame material (copper alloy). The silver of the thin silver plating 130 shown in FIG. 1 is diffused into the copper oxide film 220 and the lead frame material (copper alloy) 220, and the diffused silver existing region 230 is shown in FIG.
As shown in (b), the copper oxide film region 220 and a part of the lead frame material (copper alloy) 210 are straddled. The copper oxide film region 220 has the CuO 220B on the front surface side and the CuO 22
OB and Cu 2 O 220A are formed. Thin silver plating 13
By changing the film thickness of 0 and heating conditions, the state in which silver is diffused inside the copper oxide film differs. Diffusion of silver is not only copper oxide film 220 but also lead frame material (copper alloy) 1
Up to 20.
【００２３】これに対し、図５に示す工程と同じ工程に
て、従来の図６（ａ）に示す、銅めっきと部分銀めっき
のみを施したリードフレームを用い、半導体装置を作製
した場合には、図５（ｃ）に相当する工程での銅の酸化
状態は図４（ｃ）のようになる。従来の図６（ａ）に示
すリードフレームの場合には、銅表面に薄い銀めっきが
施されていないため、銅の酸化は速く、結果的に酸化膜
厚は、本実例の場合と比べ、厚くなり、且つ、銀の拡散
が無いため、実施例のリードフレームを用いた場合に比
べ、ＣｕＯよりＣｕ２Ｏの生成が優先されることはな
い。On the other hand, in the case where a semiconductor device is manufactured by using the conventional lead frame shown in FIG. 6 (a), which is only plated with copper and partially silver, in the same process as shown in FIG. 4C shows the oxidation state of copper in the step corresponding to FIG. 5C. In the case of the conventional lead frame shown in FIG. 6 (a), since the thin silver plating is not applied to the copper surface, the copper oxidizes quickly, and as a result, the oxide film thickness is smaller than that of this example. Since the thickness is increased and silver is not diffused, the generation of Cu 2 O is not given priority over CuO as compared with the case where the lead frame of the example is used.
【００２４】図１、図２に示す実施例のリードフレーム
１１０は、薄い銀めっき１３０を設けていることによ
り、図５（ｃ）の工程において、銅酸化膜２２０の形成
を抑えている。即ち、図４（ｂ）、図４（ｃ）に示すよ
うに、実施例のリードフレームを用いて半導体装置を作
製した場合には、薄い銀めっきを設けていない従来のリ
ードフレームを用いた場合に比べ、銅酸化膜２２０の膜
厚を低減していることが分かる。また、実施例のリード
フレーム１１０を用いた場合、銅酸化膜２２０生成の
際、ＣｕＯよりＣｕ２Ｏの生成を優先させるため、銅酸
化膜自体を破壊されにくくしており、結果として、樹脂
封止した際には、封止樹脂とのデラミネーションの発生
を抑えることかできるものとしている。Since the lead frame 110 of the embodiment shown in FIGS. 1 and 2 is provided with the thin silver plating 130, the formation of the copper oxide film 220 is suppressed in the step of FIG. 5C. That is, as shown in FIGS. 4B and 4C, when a semiconductor device is manufactured using the lead frame of the embodiment, when a conventional lead frame without thin silver plating is used, It can be seen that the film thickness of the copper oxide film 220 is reduced as compared with. Further, in the case of using the lead frame 110 of the embodiment, when the copper oxide film 220 is formed, the generation of Cu 2 O is prioritized over CuO, so that the copper oxide film itself is less likely to be destroyed, and as a result, the resin sealing is performed. When stopped, the generation of delamination with the sealing resin can be suppressed.
【００２５】また、別に、本発明のリードフレームの実
施例１において、薄い銀めっきに代え、薄いパラジウム
めっき（以下Ｐｄめっきとも表現する。）を０．００１
μｍ、０．０１μｍ、０、１μｍ、０．５μｍの厚さで
設けたもの、および、リードフレーム素材（銅合金）上
にＰｄめっきを１．０μｍの厚さで設けたもの、従来の
薄いめっきを設けないものについて、ダイパッド裏面酸
化膜の密着性、封止樹脂の密着強度を評価したが、以下
の表２に示すように、表１に示す薄い銀めっきを設けた
場合と、薄いＰｄめっきを設けた場合についても、ほぼ
同じ結果が得られた。尚、評価方法、条件は表１に示す
薄い銀めっきを設けた場合と同じである。 Separately, in Example 1 of the lead frame of the present invention, 0.001 of thin palladium plating (hereinafter also referred to as Pd plating) is used instead of thin silver plating.
μm, 0.01 μm, 0, 1 μm, 0.5 μm thick, and lead frame material (copper alloy) with Pd plating 1.0 μm thick, conventional thin plating The adhesiveness of the oxide film on the back surface of the die pad and the adhesive strength of the sealing resin were evaluated for those not provided with, but as shown in Table 2 below, when the thin silver plating shown in Table 1 was provided and when the thin Pd plating was provided. The same result was obtained in the case of providing. The evaluation method and conditions are the same as in the case of providing the thin silver plating shown in Table 1.
【００２６】上記においては、リードフレームに薄い銀
めっき、薄いＰｄめっきを施した場合について説明した
が、薄い銀めっき、薄いＰｄめっきに代え、薄い金めっ
き、薄い白金めっきを施した場合も同様の作用効果が得
られると判断される。更に、これらの銀、Ｐｄ（パラジ
ウム）、金、白金の複数種類からなる薄いめっきを施し
た場合も同様の作用効果が得られると判断される。これ
らのリードフレームを用いた半導体装置についても、上
記実施例と同様、同じ作用効果が得られると判断され
る。また、部分銀めっきに代え、部分金めっき、部分Ｐ
ｄめっきとした場合にも、上記薄いめっきを設けること
が有効であることは言うまでもない。In the above description, the case where the lead frame is thinly silver-plated or thin Pd-plated has been described, but the same is true when the thin silver-plated or thin Pd-plated is replaced by thin gold-plated or thin platinum-plated. It is judged that the action and effect can be obtained. Further, it is judged that the same action and effect can be obtained when thin plating made of plural kinds of silver, Pd (palladium), gold and platinum is applied. It is judged that the semiconductor device using these lead frames can also obtain the same effects as in the above embodiment. Also, instead of partial silver plating, partial gold plating, partial P
Needless to say, it is effective to provide the above thin plating even when d plating is used.
【００２７】[0027]
【発明の効果】本発明は、上記のように、ＩＣの組み立
て条件によらず、リードフレームに起因するデラミネー
ションの発生を防止でき、且つ、ボンディング性を損な
わない、銅合金製のリードフレームを用いた半導体装置
の提供を可能としており、同時に、本発明の半導体装置
に用いられるリードフレームと、その製造方法の提供を
可能としている。そしてまた、本発明のリードフレーム
の部分貴金属めっき方法は、本発明のリードフレームの
製造を可能とするものであるが、特に、薄い貴金属めっ
きを均一性良く所定の厚さに形成できるものとしてい
る。そして、薄い貴金属めっき、銅めっきをリードフレ
ーム全体に施す場合には、マスキング治具を必要とせず
各めっきの被膜生成作業を簡単なものとできる。As described above, the present invention provides a lead frame made of a copper alloy, which can prevent the occurrence of delamination due to the lead frame and does not impair the bondability regardless of the IC assembling conditions. It is possible to provide the used semiconductor device, and at the same time, it is possible to provide the lead frame used for the semiconductor device of the present invention and the manufacturing method thereof. Further, the method for plating a partial noble metal of a lead frame of the present invention enables the production of the lead frame of the present invention, and in particular, it is supposed that a thin noble metal plating can be uniformly formed to a predetermined thickness. . When a thin noble metal plating or copper plating is applied to the entire lead frame, a masking jig is not required and the work of forming a coating film for each plating can be simplified.
Claims (8)
グ用ないしダイボンディング用の、銀、金、パラジウム
の少なくとも１つからなる部分貴金属めっきが施され、
且つ、該部分貴金属銀めっきの下地めっきとして銅スト
ライクめっきを施してある樹脂封止型の半導体装置用リ
ードフレームであって、少なくとも封止樹脂と接する側
の銅合金材表面の全部ないし所定の部分に銀、金、白
金、パラジウムの少なくとも１つからなる薄い貴金属め
っきが施され、該薄い貴金属めっき上に銅めっきが形成
されており、且つ、銅めっき上の所定の領域に前記部分
貴金属めっきが形成されていることを特徴とするリード
フレーム。1. A partial noble metal plating of at least one of silver, gold and palladium for wire bonding or die bonding is applied using a copper alloy material as a base material,
A resin-encapsulated lead frame for a semiconductor device, in which copper strike plating is applied as an undercoat of the noble metal silver plating, and at least the entire or predetermined portion of the copper alloy material surface on the side in contact with the sealing resin. Is plated with a thin noble metal of at least one of silver, gold, platinum, and palladium, copper plating is formed on the thin noble metal plating, and the partial noble metal plating is formed in a predetermined region on the copper plating. A lead frame characterized by being formed.
厚みが０．５μｍ以下、０．００１μｍ以上であること
を特徴とするリードフレーム。2. The lead frame according to claim 1, wherein the thin noble metal plating has a thickness of 0.5 μm or less and 0.001 μm or more.
っきは部分銀めっきであり、且つ、薄い貴金属めっきが
薄い銀めっきであることを特徴とするリードフレーム。3. The lead frame according to claim 1, wherein the partial noble metal plating is partial silver plating, and the thin noble metal plating is thin silver plating.
グ用ないしダイボンディング用の、銀、金、パラジウム
の少なくとも１つからなる部分貴金属めっきが施され、
且つ、該部分貴金属銀めっきの下地めっきとして銅スト
ライクめっきを施してある樹脂封止型の半導体装置用リ
ードフレームの部分貴金属めっき方法であって、少なく
とも、順に、（Ａ）外形加工された銅合金材からなるリ
ードフレーム素材の表面の全部ないし所定の部分に、厚
みが０．００１〜０．５μｍの銀、金、白金、パラジウ
ムの少なくとも１つからなる薄い貴金属めっきを施す工
程と、（Ｂ）薄い貴金属めっきが施されたリードフレー
ムの表面の全部ないし少なくとも前記部分貴金属めっき
領域を含む部分に銅めっきを施す工程と、（Ｃ）銅めっ
きが施されたリードフレームの表面の所定領域に部分貴
金属めっきを施す工程とを有することを特徴とするリー
ドフレームの部分貴金属めっき方法。4. A partial noble metal plating of at least one of silver, gold and palladium for wire bonding or die bonding is applied using a copper alloy material as a base material,
A partial precious metal plating method for a resin-encapsulated lead frame for a semiconductor device, in which copper strike plating is performed as an undercoat of the partial precious metal silver plating, and at least in order (A) an externally processed copper alloy (B) a step of applying a thin precious metal plating of at least one of silver, gold, platinum, and palladium having a thickness of 0.001 to 0.5 μm to all or predetermined portions of the surface of the lead frame material made of A step of copper-plating the entire surface of the lead frame plated with the thin precious metal or at least a portion including the partial precious metal plated region; and (C) a partial precious metal in a predetermined region of the surface of the lead frame plated with copper. A method for plating a partial precious metal of a lead frame, which comprises a step of applying plating.
を、電解めっきないし無電解めっきにより施すことを特
徴とするリードフレームの部分貴金属めっき方法。5. The method for partially plating a noble metal of a lead frame according to claim 4, wherein the thin noble metal plating is performed by electrolytic plating or electroless plating.
部分銀めっきであり、且つ、薄い貴金属めっきが薄い銀
めっきであることを特徴とするリードフレームの部分貴
金属めっき方法。6. The partial noble metal plating method for a lead frame according to claim 5, wherein the partial noble metal plating is partial silver plating, and the thin noble metal plating is thin silver plating.
を用いたことを特徴とする半導体装置。7. A semiconductor device using the lead frame according to claim 1.
とも封止用樹脂と接するリードフレーム表面の全部ない
し所定の部分の銅酸化膜形成領域において、貴金属の濃
度が、Ｘ線光電子分光による測定で、０．１原子％以上
〜２０原子％未満であることを特徴とする半導体装置。 【０００１】 【産業上の利用分野】本発明は，封止樹脂とリードフレ
ームとの密着性を向上させた半導体装置と、それに用い
られるリードフレームに関する。8. The semiconductor device according to claim 7, wherein the concentration of the noble metal is measured by X-ray photoelectron spectroscopy at least in a copper oxide film forming region of the lead frame surface which is in contact with at least the sealing resin, or at a predetermined portion. A semiconductor device having a content of 0.1 atomic% or more and less than 20 atomic%. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having improved adhesion between a sealing resin and a lead frame, and a lead frame used for the same.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05531696A JP3701373B2 (en) | 1995-11-17 | 1996-02-20 | Lead frame, lead frame partial noble metal plating method, and semiconductor device using the lead frame |
| KR1019960043408A KR100266726B1 (en) | 1995-09-29 | 1996-09-25 | Leadframes and Semiconductor Devices with the Leadframes |
| US08/721,265 US6034422A (en) | 1995-09-29 | 1996-09-26 | Lead frame, method for partial noble plating of said lead frame and semiconductor device having said lead frame |
| CA002186695A CA2186695C (en) | 1995-09-29 | 1996-09-27 | Lead frame, method for partial noble plating of said lead frame and semiconductor device having said lead frame |
| DE19640256A DE19640256B4 (en) | 1995-09-29 | 1996-09-30 | Lead frame, method for precious metal plating of the lead frame and semiconductor device with lead frame |
| SG1996010754A SG60018A1 (en) | 1995-09-29 | 1996-09-30 | Lead frame method for partial noble plating of said lead frame and semiconductor device having said lead frame |
| KR1020000009734A KR100271424B1 (en) | 1995-09-29 | 2000-02-28 | Method for partial noble plating of a lead frame and semiconductor device having said lead frame |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32252495 | 1995-11-17 | ||
| JP7-322524 | 1995-11-17 | ||
| JP05531696A JP3701373B2 (en) | 1995-11-17 | 1996-02-20 | Lead frame, lead frame partial noble metal plating method, and semiconductor device using the lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09195068A true JPH09195068A (en) | 1997-07-29 |
| JP3701373B2 JP3701373B2 (en) | 2005-09-28 |
Family
ID=26396215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05531696A Expired - Fee Related JP3701373B2 (en) | 1995-09-29 | 1996-02-20 | Lead frame, lead frame partial noble metal plating method, and semiconductor device using the lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3701373B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000062341A1 (en) * | 1999-04-08 | 2000-10-19 | Shinko Electric Industries Co., Ltd. | Lead frame for semiconductor device |
| KR100548011B1 (en) * | 1998-06-10 | 2006-03-23 | 삼성테크윈 주식회사 | Lead frame for a semiconductor |
| JP2009515367A (en) * | 2005-11-09 | 2009-04-09 | 謝 清雄 | Manufacturing method of surface mount type precision resistor |
| JP2012505307A (en) * | 2008-10-13 | 2012-03-01 | アトテック・ドイチュラント・ゲーエムベーハー | Improved method of adhesion between silver surface and resin material |
| US8203221B2 (en) | 2008-09-01 | 2012-06-19 | Hitachi, Ltd. | Semiconductor device and method for manufacturing the same, and semiconductor sealing resin |
| US8653650B2 (en) | 2009-08-31 | 2014-02-18 | Hitachi, Ltd. | Semiconductor device with acene heat spreader |
| CN108364928A (en) * | 2018-04-11 | 2018-08-03 | 气派科技股份有限公司 | A kind of integrated circuit package structure and its processing method |
-
1996
- 1996-02-20 JP JP05531696A patent/JP3701373B2/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100548011B1 (en) * | 1998-06-10 | 2006-03-23 | 삼성테크윈 주식회사 | Lead frame for a semiconductor |
| WO2000062341A1 (en) * | 1999-04-08 | 2000-10-19 | Shinko Electric Industries Co., Ltd. | Lead frame for semiconductor device |
| US6593643B1 (en) * | 1999-04-08 | 2003-07-15 | Shinko Electric Industries Co., Ltd. | Semiconductor device lead frame |
| JP2009515367A (en) * | 2005-11-09 | 2009-04-09 | 謝 清雄 | Manufacturing method of surface mount type precision resistor |
| US8203221B2 (en) | 2008-09-01 | 2012-06-19 | Hitachi, Ltd. | Semiconductor device and method for manufacturing the same, and semiconductor sealing resin |
| JP2012505307A (en) * | 2008-10-13 | 2012-03-01 | アトテック・ドイチュラント・ゲーエムベーハー | Improved method of adhesion between silver surface and resin material |
| US8653650B2 (en) | 2009-08-31 | 2014-02-18 | Hitachi, Ltd. | Semiconductor device with acene heat spreader |
| CN108364928A (en) * | 2018-04-11 | 2018-08-03 | 气派科技股份有限公司 | A kind of integrated circuit package structure and its processing method |
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| Publication number | Publication date |
|---|---|
| JP3701373B2 (en) | 2005-09-28 |
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