JPH09186637A - Diversity receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute change-over even during reception by comparing the strength of signals received by means of plural antennas at high speed with simple hardware configuration. SOLUTION: The respective signals received by the plural antennas 1 and 2 are selected by a first switch circuit 3 one by one and transmitted to a receiver 4. Voltages indicating the strength of the signals are held in capacitors 8 and 9 corresponding to the respective antennas 1 and 2 by the second switch circuit 16 which is simultaneously changed-over with the first switch circuit 3, level comparing circuits 10 and 11 detects the largest voltage within the respective voltages held in the capacitors 8 and 9 and the first switch circuit 3 is controlled so as to permit only the signal to be transmitted to the receiver for a prescribed period after that.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to mobile communication and indoor wireless communication, and more particularly to a diversity receiver.

[0002]

2. Description of the Related Art Generally, in mobile communication and indoor wireless communication, radio waves are reflected by buildings and indoor structures, and various reflected waves are detected by a receiving antenna. Due to their interference, the received signal can be strengthened or weakened. The situation changes due to the movement of at least one of the receiver, transmitter and reflector. In mobile communication and indoor wireless communication, the situation changes from moment to moment.

Diversity is one of the countermeasures. The spatial diversity, polarization diversity, or angle diversity selective combining method among them is a method in which a plurality of antennas are provided and the one with the best reception state is used. In spatial diversity, the antennas are spaced apart to some extent. In polarization diversity, antennas are installed with different planes of polarization. In the angle diversity, the antenna is provided with directivity to change the angle.

A conventional diversity receiver is shown in FIGS. 2 and 3. In the diversity receiver shown in FIG. 2, the signals received by the two antennas 1 and 2 are switched by the switch circuit 3 and transmitted to the receiver 4, and demodulated by the receiver 4.
Reference numeral 15 is a demodulation output of the signal. At this time, the level detection output 16 representing the strength of the received signal is A / D.
It is converted into a digital signal by the converter 20 and transmitted to the microcontroller 21. The microcontroller 21 then stores it. Micro controller 21
Compares the level detection outputs 16 stored for the antennas 1 and 2, respectively, and selects the switch circuit 3 for the stronger output.
Switch.

However, switching of the switch circuit 3 causes interruption of the signal transmitted to the receiver 4. or,
The A / D converter 20 requires time for conversion, and therefore requires time for comparing the signal intensities and switching the switch circuit 3. Generally, the conversion time of the successive approximation type A / D converter 20 is several μ with an accuracy of 8 to 16 bits.
It is from sec to several hundred μsec.

Considering, for example, the case of transmitting digital data in units of packets, the antennas 1 and 2 are usually switched during a period in which there is no data, which is called a preamble in a packet. Since no data is transmitted during this period, the actual data transmission rate is reduced. Specifically, when transmitting 100 bits as one packet at a data rate of 1 Mbps,
The period of one packet is 100 μsec.

To switch the antennas 1 and 2 using the A / D converter 20 having a conversion time of 12.5 μsec, a preamble of at least 12.5 μsec is required, and the actual transmission rate with respect to the data rate is 1
00 / (100 + 12.5) = 0.889 (88.9
%).

FIG. 3 shows a diversity receiver having another structure. The signals received by the antennas 1 and 2 are demodulated by the separate receivers 22 and 23 and output. At this time, the level detection outputs 26 and 27 are compared by the level comparison circuit 24, and the switch circuit 2 is switched to the one having the stronger output.
Demodulation output 15 is selected by switching 5. In this way, the level detection output 2 of the receivers 22 and 23
By comparing 6 and 27 in the level comparison circuit 24, the signal strengths are always compared, but the circuit scale and power consumption increase.

[0009]

As described above, in the diversity receiver shown in FIG. 2, the signal is interrupted when the switches are switched. In addition, an A / D converter is required to compare the intensities of the received signals, which requires processing time. On the other hand, in the diversity receiver shown in FIG. 3, the signal strength is constantly compared, but the circuit scale and power consumption increase. The present invention solves these problems, and an object of the present invention is to provide a diversity receiver capable of switching the strength of signals received by a plurality of antennas at high speed with a simple hardware configuration and switching even during reception. And

[0010]

In order to achieve the above object, according to the present invention, each signal received by a plurality of antennas is selected one by one by a first switch circuit and transmitted to a receiver. The voltage indicating the strength of these signals is held in the capacitors corresponding to each of the antennas by the second switch circuit that is switched at the same time as the first switch circuit, and is held in the capacitors by the level comparison circuit. The maximum one of the voltages is detected, and the first switch circuit is controlled so that only the signal is transmitted to the receiver for a predetermined time thereafter.

In such a configuration, the signals received by each antenna are selected one by one and transmitted to the receiver. The receiver demodulates the signal and outputs it. At this time, the voltage indicating the signal strength is transmitted to the corresponding capacitors for each antenna, and the voltage is held. The maximum of these voltages is detected by the level comparison circuit, and the first switch circuit is switched so that the corresponding signal is transmitted to the receiver.

According to the present invention, in addition to the above structure,
The first switch circuit and the second switch circuit are switched by a clock signal, and the level comparison circuit stops switching by the clock signal.

In such a configuration, the clock signal causes
The voltage indicating the strength of the signal received by each antenna is automatically held in each capacitor, and the one having a strong strength of the signal received immediately is selected and fixed to it for a predetermined period. . The higher the frequency of the clock signal, the faster the selection of antenna. Further, it becomes possible to select an antenna even during reception.

According to the present invention, in addition to the above configuration,
The level comparison circuit comprises at least one comparator and a controller for processing the output of the comparator. In such a configuration, when the antennas need to be switched, the controller controls the switch circuits to compare the signal strengths of the antennas and automatically switches the switch circuits so that the strength is maximized.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION One embodiment of the present invention is shown in FIG. The signals received by the antennas 1 and 2 are selected by the switch circuit 3 and transmitted to the receiver 4. The receiver 4 demodulates the signal. Reference numeral 15 is a demodulation output of the signal. The level detection output 16 indicating the strength of the received signal is the switch circuit 5
Is transmitted to either of the capacitors 8 and 9 and the voltage thereof is held.

The two switch circuits 3 and 5 are designed to be switched at the same time. For example, the voltage of the level detection output 16 when the antenna 1 is selected is selected in the capacitor 8 and the antenna 2 is selected. The voltage of the level detection output 16 at that time is held in the capacitor 9. These voltages are compared by the comparator 10, and the comparator 10 outputs the judgment output 12 as a digital signal. For example, if the voltage held in the capacitor 8 is higher than the voltage held in the capacitor 9, the judgment output 12 becomes a high voltage level (hereinafter, simply referred to as “1”), and otherwise the judgment output 12 is a low voltage. It becomes a level (hereinafter simply referred to as “0”).

Switching of the switch circuits 3 and 5 is periodically performed by the clock signal 7 via the switch circuit 6. For example, assuming that the frequency of the clock signal 7 is 1 MHz, the voltages of the level detection output 16 corresponding to the antennas 1 and 2 are stored in the capacitors 8 and 9 after 1 μsec has elapsed. This will be described with reference to the timing chart shown in FIG.

In the initial state, the capacitors 8 and 9 are not charged. The clock signal 7 repeats 0 and 1 periodically. The switch circuits 3 and 5 are switched by this signal. In FIG. 5, the antenna 1 and the capacitor 8 are selected when the clock signal 7 is 1, and the antenna 2 and the capacitor 9 are selected when the clock signal 7 is 0. By switching the antennas 1 and 2, the level detection output 16 repeats the voltages A and B according to the clock signal 7. The capacitor 8 holds the voltage B when the antenna 1 is selected, and the capacitor 9 holds the voltage A when the antenna 2 is selected.

However, depending on the switching of the switch circuit 5, either one of the capacitors 8 and 9 is subjected to the level detection output 16
However, since the input impedance of the comparator 10 is high, the capacitors 8 and 9 are less discharged and the voltage is held for a short time. After the elapse of a predetermined time, the microcontroller 11 inputs the determination output 12 output from the comparator 10 and switches the antennas 1 and 2 to the one having the stronger received signal strength. Therefore, the mode selection output 13 and the antenna selection output 14 are output as control signals.

A software flowchart of the microcontroller 11 is shown in FIG. When the microcontroller 11 is instructed to select the antennas 1 and 2, the mode selection output 13 is set to 1 and the antenna selection output 14 is set.
To 0. Then, it waits for a predetermined time. For example, 3μse
c Wait. After that, the microcontroller 11 inputs the judgment output 12 of the comparator 10. If it is 1, the antenna selection output 14 is set to 1, and if it is 0, the antenna selection output 14 is set to 0.

This will be described with reference to the timing chart shown in FIG. Here, the switch control signal represents a signal input to the switch circuits 3 and 5. That is, when the switch control signal is 1, the switch circuits 3, 5
Is in the state in which the antenna 1 is selected, and when the switch control signal is 0, the switch circuits 3 and 5 are in the state in which the antenna 2 is selected.

The frequency of the clock signal 7 is 1 MHz. When the microcontroller 11 is instructed to select the antennas 1 and 2, it outputs the mode selection output 13 to 1
And the antenna selection output 14 is set to 0. When the mode selection output 13 becomes 1, the switch circuit 6 is connected to the clock signal 7, the clock signal 7 is transmitted to the switch circuits 3 and 5 as a switch control signal, and the determination is started. The switch circuits 3 and 5 are switched several times during 3 μsec, and the level detection output 16 is held in the capacitors 8 and 9.

The micro controller 11 reads the result of the judgment output 12 3 μsec after the judgment is started.
In FIG. 6, the determination output 12 is 1. At this time,
The microcontroller 11 outputs the antenna selection output 14 to 1
And the mode selection output is returned to 0. As a result, the switch circuit 6 is connected to the antenna selection output 14, and the switch control signal becomes 1 from the antenna selection output 14. The connection of the switch circuit 3 is fixed to the antenna 1 which has a strong signal strength, and the receiver 4 uses the antenna 1 for normal reception.
Demodulates the signal received by.

In this way, the antennas 1 and 2 are switched at high speed, requiring almost no time. In addition, since the switching of the switch circuits 3 and 5 is fast, the capacitor 8
The decrease amount of the voltage held at 9 due to the discharge becomes small,
The accuracy of the voltage held is improved. Further, if the clock signal 7 is faster than the data rate, the antennas 1 and 2 can be determined and switched even during data transmission.

For example, consider a case where digital data is transmitted by direct spread spectrum spread communication.
In spread spectrum communication, spread modulation is applied at a speed 10 times or more that of data to be transmitted to spread the spectrum. Demodulation is performed by despreading, which is an operation similar to spread modulation. Due to this effect, if the clock signal 7 is faster than the data rate, even if a part of the signal transmitted to the receiver 4 is lost due to the switching, the signal is spread by the despreading operation and the data is restored. .

For this reason, the selection of the antennas 1, 2 can be made at any time during data transmission. When the signal is sent in packet units, the antennas 1 and 2 may be determined in the preamble area sent at the beginning of the packet d and the signal may be switched to the one having a stronger signal strength. In this way, the signal after the preamble area is received after the antennas 1 and 2 are selected. Then, the antennas 1 and 2 are determined for each packet, and the signal is always received by the strong antenna.

[0027]

【The invention's effect】

<Effect of Claim 1> The voltage held in each capacitor is immediately compared in the level comparison circuit, and the antenna having the strongest received signal strength is immediately selected. Judgment at high speed with simple hardware.

<Effect of Claim 2> The received signal is switched to the antenna having a strong signal at a high speed, and the reception state becomes good. Even during reception, the strength of the signal received by the antenna is measured and the antenna can be switched.

<Effect of Claim 3> When the antennas need to be switched, the microcontroller controls each switch circuit to compare the signal strengths of the respective antennas, and automatically switches the strengths to maximize the strength. Switch the circuit.
The switching can be performed at any time when the signal needs to be switched, such as at the start of reception or during reception.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a first configuration diagram of a conventional diversity receiver.

FIG. 3 is a second configuration diagram of a conventional diversity receiver.

FIG. 4 is a flowchart of software of a microcontroller according to an embodiment of the present invention.

FIG. 5 is a time chart of the analog signal.

FIG. 6 is a time chart of the digital signal.

[Explanation of symbols]

 4 Receiver 7 Clock signal 10 Comparator 11 Micro controller 20 A / D converter

Claims (5)

[Claims] 1. Signals received by a plurality of antennas are selected one by one by a first switch circuit and transmitted to a receiver, and a voltage indicating the strength of those signals is transmitted to the first switch circuit. The second switch circuit that is switched at the same time holds the capacitors corresponding to the respective antennas, and the level comparison circuit detects the maximum voltage among the voltages held in the capacitors, and only the signal thereof is detected. The diversity receiver is characterized in that the first switch circuit is controlled so that is transmitted to the receiver for a predetermined period thereafter. 2. The diversity according to claim 1, wherein the first switch circuit and the second switch circuit are switched by a clock signal, and the level comparison circuit stops switching by the clock signal. Receiving machine. 3. The diversity receiver according to claim 1, wherein the level comparison circuit includes at least one comparator and a controller which processes an output of the comparator. 4. The detection is performed in a first period of a signal transmitted in packet units, and the switch is kept in a switching stop state in a second period following the first period. The diversity receiver according to claim 1. 5. The diversity receiver of claim 4, wherein the signal is a spread spectrum signal.