JPH09186535A - Differential input sense amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the operating speed by providing a MOS transistor(TR) whose drain or source connects to an output node of the amplifier circuit and whose gate receives one of differential input voltages. SOLUTION: Two MOS TRs are inserted in series between both nodes VCC and VSS in a 1st stage amplifier circuit 10 and a 2nd stage amplifier circuit 20a in addition to a constant current source TR, and the constant current characteristic is identical for both the amplifier circuits. Thus, an output operating point of the 1st stage amplifier circuit 10 and an output operating point of the 2nd stage amplifier circuit 20a are matched. Since one voltage input Vin1 of the differential input voltages is applied to a gate of the NMOS TR N4, the 2nd stage amplifier circuit 20a starts amplification operation before the output of the 1st stage circuit 10 is confirmed to improve the operating speed of the differential input sense amplifier circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential input type sense amplifier circuit, and more particularly to a second stage amplifying circuit of a differential input type sense amplifier circuit having a two-stage amplification structure, which is used for a semiconductor memory, for example. It is what is done.

[0002]

2. Description of the Related Art In a differential input type sense amplifier circuit used for sensing a bit line potential in a semiconductor memory, the difference in differential input voltage is usually very small, so that the first stage amplification is performed. In some cases, the gain of the circuit itself cannot be sufficiently amplified, and a configuration in which amplification is performed by the second-stage amplification circuit (two-stage amplification configuration) may be adopted.

FIG. 3 shows a conventional example of a differential input type sense amplifier circuit having a two-stage amplification configuration for bit line potential sensing. In FIG. 3, the first-stage amplifier circuit 10 includes NMOS transistors N1 and N2 forming a differential input pair in which respective sources are commonly connected and a differential input voltage is applied to respective gates.
An NMOS transistor N3 for a constant current source having a drain and a source connected between a common source connection node of the differential input pair transistor and a ground potential (VSS) node, and a constant voltage Vref applied to a gate, and a power supply. And a PMOS current mirror circuit connected between the potential (VCC) node and each drain of the differential input pair transistor.

The above-mentioned PMOS current mirror circuit is
An input-side PM in which the source and drain are connected between the node and the drain of one of the transistors N1 of the differential input pair transistors, and the gate and drain are connected to each other.
Between the OS transistor P1 and the drain of the other transistor N2 of the differential input pair transistor,
The drain is connected and the gate is the PMOS on the input side
Output side PMOS connected to the gate of transistor P1
And a transistor P2.

The second-stage amplifier circuit 20 has a VCC node and a V node.
It is composed of a PMOS transistor P3 and an NMOS transistor N5 which are connected in series with the SS node. The gate of the PMOS transistor P3 has the above-mentioned 1
The output node (the drain of the output side PMOS transistor P2 of the PMOS current mirror circuit) of the amplifier circuit 10 of the stage is connected, and the NMOS transistor N5 is connected.
The constant voltage Vref is applied to the gate of the.

The input node of the inverter circuit 30 is connected to the output node of the second-stage amplifier circuit 20 (drain interconnection node of the PMOS transistor P3 and the NMOS transistor N5).

In the differential input type sense amplifier circuit of FIG. 3, the NMOS transistor N of the first stage amplifier circuit 10
If the currents of 1 and N2 are I, respectively, the current of the NMOS transistor N3 for the constant current source is 2I. Further, the PMOS transistor P1 of the second-stage amplifier circuit 20
The currents of the NMOS transistor N5 and the NMOS transistor N5 are, for example, 2I.

Then, the voltage V1 at the output node of the first-stage amplifier circuit 10 is controlled according to the voltage difference between the differential input voltages Vin1 and Vin2, and the second-stage amplifier circuit 10 has two stages according to the output voltage of the first-stage amplifier circuit 10. The voltage V2 of the output node of the eye amplifier circuit 20 is controlled, and the voltage level of the output node of the inverter circuit 30 is determined depending on whether the output voltage of the amplifier circuit 20 of the second stage exceeds the threshold value Vth of the inverter circuit 30.

The voltage V1 at the output node of the first-stage amplifier circuit 10 is the differential input voltage Vin1 + (threshold voltage of NMOS transistor N1)-(absolute value of threshold voltage of PMOS transistor P2).

On the other hand, the voltage V2 at the output node of the second-stage amplifier circuit 20 is V1- (absolute value of the threshold voltage of the PMOS transistor P1). In this case, in the first-stage amplifier circuit 10, two MOS transistors are inserted in series in addition to the constant current source transistor in the current path between the VCC node and the VSS node, whereas the two-stage amplifier circuit 10 has two stages. In the eye amplification circuit 20, in addition to the constant current source transistor, one MOS is provided in the current path between the VCC node and the VSS node.
Since only the transistors are inserted, the constant current characteristics are slightly different between the first-stage amplifier circuit 10 and the second-stage amplifier circuit 20, and the output operating point of the first-stage amplifier circuit 10 and the second-stage amplifier circuit 20. Output operating point (input threshold of the next stage circuit) is not matched (mismatch). As a result, a malfunction may occur in the next-stage circuit at the start of the amplification operation or when a noise signal is input, and the reliability of the differential input type sense amplifier circuit may be reduced.

[0011]

As described above, the conventional differential input type sense amplifier circuit having the two-stage amplification configuration has the output operating point of the first stage amplifying circuit and the output operating point of the second stage amplifying circuit. Since it is not matched with, there is a possibility that it may operate in the reverse direction at the start of amplification operation or when a noise signal is input, and it takes time to bring the output that moved in the reverse direction to normal operation. there were.

The present invention has been made to solve the above problems, and it becomes easy to match the output operating point of the first stage amplifier circuit with the output operating point of the second stage amplifier circuit. ,
It is an object of the present invention to provide a differential input type sense amplifier circuit having a two-stage amplification structure capable of improving the operation speed.

[0013]

A differential input type sense amplifier circuit according to the present invention comprises a first stage amplifier circuit for amplifying a differential input voltage and an amplifier circuit for amplifying an output potential of the first stage amplifier circuit.
And a second stage amplifier circuit, wherein the second stage amplifier circuit is
The drain or source is connected to the output node,
MO in which one of the differential input voltages is input to the gate
It is characterized by having an S transistor.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a differential input type sense amplifier circuit according to the first embodiment of the present invention.

In FIG. 1, reference numeral 10 is a first-stage amplifier circuit for amplifying a differential input voltage, 20a is a second-stage amplifier circuit for amplifying an output potential of the first-stage amplifier circuit 10, and 30 is 2.
It is an inverter circuit to which the output potential of the amplifier circuit of the stage is input.

In the first-stage amplifier circuit 10, the sources are connected in common, and the differential input voltages Vin1 and Vin2 are applied to the gates.
NMOS transistor N forming a differential input pair to which is applied
1, N2, a drain-source connection between the common source connection node of the differential input pair transistor and the VSS node, and a constant current source NMOS transistor N3 to which a constant voltage Vref is applied to the gate, And a PMOS current mirror circuit connected between the Vcc node and the drains of the differential input pair transistors.

The PMOS current mirror circuit has
An input-side PM in which the source and drain are connected between the node and the drain of one of the transistors N1 of the differential input pair transistors, and the gate and drain are connected to each other.
Between the OS transistor P1 and the drain of the other transistor N2 of the differential input pair transistor,
The drain is connected and the gate is the PMOS on the input side
Output side PMOS connected to the gate of transistor P1
And a transistor P2.

The second stage amplifier circuit 20a includes a PMOS transistor P3, NMOS transistors N4 and N5 which are connected in series between the VCC node and the VSS node.
Consists of

The output node of the first stage amplifier circuit 10 (the drain of the output side PMOS transistor P2 of the PMOS current mirror circuit) is connected to the gate of the PMOS transistor P3, and the NMOS transistor N3 is connected.
The gate of No. 4 has one voltage input Vin of the differential input voltage
1 (the gate input voltage of the NMOS transistor N1) is applied, and the constant voltage Vref is applied to the gate of the NMOS transistor N5.

The input node of the inverter circuit 30 is connected to the output node of the second-stage amplifier circuit 20 (the series connection node of the PMOS transistor P3 and the NMOS transistor N4).

In the differential input type sense amplifier circuit of FIG. 1, if the currents of the NMOS transistors N1 and N2 are I, the current of the NMOS transistor N3 for the constant current source is 2I. In addition, the second stage amplifier circuit 20
The currents of the PMOS transistor P1, the NMOS transistor N4, and the NMOS transistor N5 of a are each 2I, for example.

Then, the voltage V1 at the output node of the first-stage amplifier circuit 10 is controlled according to the voltage difference between the differential input voltages Vin1 and Vin2, and the second-stage amplifier circuit 10 has two stages according to the output voltage of the first-stage amplifier circuit 10. The voltage of the output node V2 of the eye amplification circuit 20 is controlled, and the voltage level of the output node of the inverter circuit 30 is determined by whether or not the output voltage of the amplification circuit 20 of the second stage exceeds the threshold value Vth of the inverter circuit 30.

The voltage V1 at the output node of the first-stage amplifier circuit 10 is the differential input voltage Vin1 + (threshold voltage of the NMOS transistor N1)-(absolute value of the threshold voltage of the PMOS transistor P2).

On the other hand, the voltage V2 at the output node of the second-stage amplifier circuit 20 is V1- (absolute value of the threshold voltage of the PMOS transistor P1). In this case, in the first stage amplifier circuit 10, two MOS transistors are inserted in series in the current path between the VCC node and the VSS node in addition to the constant current source transistor. Also in 20a, in addition to the constant current source transistor, two MOS transistors are inserted in the current path between the VCC node and the VSS node.
The constant current characteristics are the same in the amplifier circuit 20a of the stage.

As a result, the output operating point of the first-stage amplifier circuit 10 and the output operating point of the second-stage amplifier circuit 20a (the input threshold value of the next-stage circuit) can be matched. That is, it becomes easier to match the output operating point of the first-stage amplifier circuit 10 with the input threshold value of the second-stage amplifier circuit 20a as compared with the conventional example.

Moreover, since one voltage input Vin1 of the differential input voltage is applied to the gate of the NMOS transistor N4 connected to the output node of the second-stage amplifier circuit 20a, the output of the first-stage amplifier circuit 10 is applied. The amplification operation of the second-stage amplification circuit 20a can be started before is determined.

This reduces the risk that the second-stage amplifier circuit 20a will operate in the reverse direction at the start of the amplifying operation or when a noise signal is input, and the operating speed of the differential input type sense amplifier circuit can be improved. Will be possible.

FIG. 2 shows a modification of the differential input type sense amplifier circuit of FIG. Compared to the sense amplifier circuit shown in FIG. 1, the sense amplifier circuit shown in FIG. 2 uses the voltage V1 at the output node of the first stage amplifier circuit 10 as the gate input voltage of the NMOS transistor N5 in the second stage amplifier circuit 20b. Is different and is the same as the others, so that the same reference numerals as those in FIG. Even in such a configuration, basically, the same effect can be obtained by the same operation as that of the sense amplifier circuit shown in FIG.

[0029]

As described above, according to the differential input type sense amplifier circuit of the present invention, the output operating point of the first stage amplifier circuit and the input threshold value of the second stage amplifier circuit can be matched. It becomes easier and the operation speed can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a differential input type sense amplifier circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a modified example of the differential input type sense amplifier circuit of FIG.

FIG. 3 is a circuit diagram showing a conventional differential input type sense amplifier circuit.

[Explanation of symbols]

 10 ... 1st stage amplifier circuit, 20a ... 2nd stage amplifier circuit, 30 ... Inverter circuit, N1-N5 ... NMOS transistor, P1-P3 ... PMOS transistor.

Claims (3)

[Claims] 1. A first-stage amplifier circuit for amplifying a differential input voltage, and a second-stage amplifier circuit for amplifying an output potential of the first-stage amplifier circuit, wherein the second-stage amplifier circuit is provided. The circuit is a MOS whose drain or source is connected to its output node and one of the differential input voltages is input to its gate.
A differential input type sense amplifier circuit having a transistor. 2. The differential input type sense amplifier circuit according to claim 1, wherein the first-stage amplifier circuit and the second-stage amplifier circuit each have a constant current circuit driven by the same constant voltage. Characteristic differential input type sense amplifier circuit. 3. The differential input type sense amplifier circuit according to claim 1, wherein each of the sources of the first stage amplifier circuit is commonly connected, and a differential input voltage is applied to each gate. Between the first and second MOS transistors of the first conductivity type and the source common connection node of the first and second MOS transistors and the first potential node, and the drain and source are connected to the gate. A source / drain is connected between a third MOS transistor of the first conductivity type for a constant current source to which a constant voltage is applied and a second potential node and the drain of the first MOS transistor. A fourth MO of the second conductivity type in which the drains are connected to each other
S-transistor, the second potential node and the second MOS
The source and drain are connected to the drain of the transistor, and the fourth MOS transistor and the fifth conductivity type fifth MOS transistor having the gates connected to each other are provided. Is a second conductivity type sixth MOS transistor, a first conductivity type seventh MOS transistor and an eighth MOS transistor which are connected in series with each other between the second potential node and the first potential node. The drain of the fifth MOS transistor is connected to the gate of the sixth MOS transistor, and the gate input voltage of the first MOS transistor is applied to the gate of the seventh MOS transistor.
The differential input type sense amplifier circuit, wherein the constant voltage is applied to the gate of the eighth MOS transistor.