JPH09181740A - Flow control method in network node and packet switching system - Google Patents

Abstract

(57) [Abstract] [Problem] To process multimedia traffic such as burst data. SOLUTION: A queuing input buffer 11 for each virtual connection, a resource management cell (RM) management means for generating 13, returning 15 and terminating a resource management cell, and a sending rate controlling scheduler 10 for each virtual connection. An interface section 8a including the traffic shaping means 24 of the outgoing line, an outgoing buffer corresponding to the outgoing line, and a core switch section for performing packet switching are provided, and a virtual connection is made between the input / output buffers via the RM cell. Band allocation or buffer management is performed.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a flow control method in a network node by a resource management cell,
Furthermore, it relates to a packet switching system that processes burst data, etc., and particularly assumes an edge switching system arranged at the connection between the public network and the private network.
The present invention relates to a one-stage packet switching system that realizes multi-QoS (Quality of Service).

[0002]

2. Description of the Related Art A packet switching system that realizes multi-quality of service, that is, accommodates multimedia traffic such as CBR (Constant Bit Rate) and VBR (Variable Bit Rate) is active. Is being developed by. For example, JP-A-7-1071
Japanese Patent Publication No. 16 discloses a packet switching system in which a large capacity low speed buffer is mounted and a small amount of high speed shared buffer is mounted. Further, Japanese Patent Laid-Open No. 6-197128 discloses a packet switching system that requires a small amount of buffer, has a low access speed to the buffer, and can easily process traffic such as multicast. .

[0003]

However, in Japanese Unexamined Patent Publication No. 7-107116, each of the N input buffer control units outputs N input buffer control units if the free space of the shared buffer is N packets or more. It is characterized by controlling to output a packet. However, since cells are input to one shared buffer regardless of the traffic type, when the free space in the shared buffer becomes less than N packets, that is, when backpressure is applied from the shared buffer to the input buffer, Since the output of CBR traffic can also be stopped, there is a problem that the delay of the CBR cell becomes large.

From a mounting point of view, in order to return the back pressure signal from the shared buffer to each input interface by a separate line, a dedicated wiring for transmitting the back pressure signal is required, which increases the capacity of the switch. There was a problem that it was difficult to do. Similarly to this, Japanese Patent Laid-Open No. 6-1
Also in the 97128 publication, in order to return the back pressure signal from the output side to the input side by a separate line, a dedicated wiring for transmitting the back pressure signal is required, which makes it difficult to increase the capacity of the switch. there were.

In any case, since the rate control between the core switch section and the input buffer module or the rate control between the output buffer and the input buffer is performed only by the cell transmission stop control by the back pressure, there is a time bias in the cell flow. Therefore, the delay variation characteristic may be deteriorated. In addition, there is a possibility that the throughput of the input buffer module, which is separated and independent on the side receiving the back pressure, addressed to the same route may be smoothed between the modules. That is, if the number of connections destined for the same line is deviated for each module, there is a possibility that fairness in throughput cannot be maintained.

Therefore, the present invention has been made in view of the above problems. The first object of the present invention is to provide CBR, V
An object of the present invention is to provide a one-stage packet switching system that efficiently accommodates various types of traffic such as BR and ABR (Available Bit Rate). A second object of the present invention is to provide a packet switching system for burst data in which cells are not discarded within a node. A third object of the present invention is to establish a separate line within a node and to perform flow control between nodes,
It is to provide a packet switching system for processing ABR traffic.

[0007]

In order to solve the various problems described above, rate control is performed by the input side module of the packet switch, and the sum of cell flow rates from the input side module is the capacity of the output path of the core switch. The feedback control is performed so as not to exceed the limit.
More specifically, it is as follows. That is, the packet switching system of the first invention controls an input buffer for queuing for each virtual connection, a resource management cell management means for generating, returning, and terminating a resource management cell, and a transmission rate for each virtual connection. A scheduler, an interface unit including traffic shaping means for the outgoing line, an output buffer provided for the outgoing line,
A core switch unit that performs packet switching is provided, and bandwidth allocation to a virtual connection or buffer management is performed between an input buffer and an output buffer via a resource management cell.

Further, the packet switching system of the second invention comprises an input buffer for queuing for each virtual connection, a resource management cell management means for generating, returning and terminating a resource management cell, and a transmission for each virtual connection. An interface section including a scheduler for controlling the rate,
An output buffer provided for the outgoing line and a core switch unit for performing traffic shaping and packet switching of the outgoing line are provided, and a virtual network is provided between the input buffer and the output buffer via a resource management cell. The feature is that bandwidth is allocated to the connection or buffer management is performed.

Further, the packet switching system of the third invention is such that an input buffer for queuing for each virtual connection, a resource management cell managing means for generating, returning and terminating a resource management cell, and transmission for each virtual connection. A scheduler for controlling the rate, an interface section including traffic shaping means for the outgoing line, an output buffer provided for the outgoing line, and a core switch section for performing packet switching are provided, and the input buffer, Alternatively, the buffer of the core switch is divided for each traffic class, and the bandwidth is allocated to the virtual connection or the buffer is managed between the input buffer and the output buffer via the resource management cell.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the packet switching system of the present invention will be described in detail below with reference to FIGS. First, FIG. 1 shows a network configuration as an example of a communication network to which the packet switching system according to the present invention is applied. In the communication network shown in the figure, packet switching systems 2 and 3 are a public network (WAN) 1 and a private network (L), respectively.
AN) 4 and 5 are provided, and ABR traffic class service (for burst data such as inter-computer communication) is provided in each node of the packet switching systems 2 and 3. Also, this communication network is CB
An R service (for voice, for example) and a VBR service (for video, for example) can be provided at the same time. FIG. 10 shows an AB in a packet switching system according to the related art.
Although the R flow control method is shown, the big difference from the conventional method proposed in the ATM forum is that the feedback control of the ABR is performed only in the node as shown in FIG. It is to be able to provide an effective ABR flow control method with reduced delay (note that one embodiment of ABR feedback control is described in detail in the related description of FIG. 3). .

More specifically, the edge-to-edge of the public network, that is, the distance between the packet switching systems 2 and 3 shown in FIG. 10 is generally several hundred km to several thousand km. Therefore, the ABR closed loop is used. The control delay time in feedback control reaches several milliseconds to several tens of milliseconds, and there is a problem in rate controllability when switching and transmitting computer data having a strong burst property. On the other hand, in the present invention, as shown in FIG.
By implementing BR feedback control only within the node, the control delay time was reduced from tens of microseconds to hundreds of microseconds, and ABR feedback controllability could be improved in the order of 2 to 3 digits. is there.

The second difference is that in the conventional method, ABR feedback control is performed between the terminal 6 and the packet switching system 2, between the packet switching systems 2 and 3, and between the packet switching system 3 and the terminal 7. However, in contrast, in the present invention, A
Since the implementation period of the BR feedback control is localized only in each node of the packet switching systems 2 and 3, the terminal not performing the ABR operation, that is, the non-AB terminal.
It is possible to accommodate the traffic from the R terminal. Due to the intra-node localization of ABR feedback control, the packet switching systems 2 and 3 each receive unauthorized burst traffic from the LAN side on the public network (W.
It also functions as a traffic firewall for preventing the inflow to the AN) 1.

FIG. 2 also shows a schematic configuration of an example of each of the packet switching systems 2 and 3 according to the present invention. As a representative, the packet switching system 2 will be described. The packet switching system 2 includes a core switch unit 30, a LAN 4 side interface (INF) 8a to 8n, and a WAN 1 side interface (INF) 8a 'to 8n'. It has become a thing. Data from the LAN 4 side is input to the interfaces 8a to 8n, then switched by the core switch unit 30, and the WAN 1 side interface 8a 'is also switched.
Although the data is transmitted to the WAN1 side through 8n ', such a situation is the same when data is transmitted from the WAN1 side to the LAN4 side.

Now, between the interfaces 8a to 8n and the interfaces 8a 'to 8n', A described below is used.
Although the BR control is performed, in order to perform the ABR control between the transmission side (virtual source) and the reception side (virtual destination), the interfaces 8a to 8a
n and 8a 'to 8n' have both functions of a virtual source and a virtual destination, and accommodate a plurality of virtual channels (VCs) of a plurality of service classes.

FIG. 3 shows an example of the configuration of the interface unit 8 in the packet switching system according to the present invention. The function and configuration of the virtual source and the virtual destination for providing the ABR service will be described below with reference to FIG. That is, the functions of the virtual source of the interface 8 are 1) generation of an RM (resource management) cell, 2) confirmation of the end of the RM cell returned from the facing interface 8 (virtual destination described later) and congestion indication. 3) ACR calculation according to the congestion indication, 4) A calculated from the cell buffer
There is a cell output corresponding to CR. Of these, 1) above
RM cells are generated by the RM cell generation unit 13, and the output thereof is managed by the output management unit 19 in the scheduler 10.
The RM cell terminating unit 14 confirms the RM cell termination and the congestion indication in 2). Specifically, the returned R
Congestion indication bit of M cell (Congestion Indication bi
t: CI bit) is detected and transferred to the scheduler 10. Furthermore, the scheduler 10 performs 3) ACR calculation and 4) cell output. Specifically, the ACR calculation unit 1
7 calculates that the ACR value is lowered when the CI bit given from the RM cell terminating unit 14 indicates congestion (CI = 1), and otherwise, the ACR value is raised. In the cell time slot allocation unit 18, the calculated AC
LCR / ACR is quantized based on R so that cells can be assigned to cell time slots and transmitted. The output management unit 19 outputs the output 2 of the cell time slot allocation unit 18.
2 and various cells (ABR (R
(Including M cells), CBR, and VBR cells) are assigned to cell time slots, and output to the core switch 30 is managed. A line processing unit 16 is provided on the LAN side.

On the other hand, as the function of the virtual destination, 1) the RM cell sent from the facing interface 8 (the virtual source described above) is returned,
2) A congestion indication may be given to the RM cell at the time of returning. These are all RM cell extraction / folding unit 1
Done in 5. Specifically, when an RM cell sent from an opposite virtual source arrives at a virtual destination, congestion of a data cell immediately before the RM cell to a subsequent device occurs immediately before the RM cell as specified in the ATM Forum (ATM-Forum). Display bit (Explicit Forword Congestion
Indication bit: The EFCI bit is "1" indicating congestion, and the CI bit of the RM cell is set to "1". Otherwise, the CI bit of the RM cell is set to "0" and transferred to the virtual source. Is. The transferred RM cell is temporarily stored in the cell buffer 11 and output under the control of the output management unit 19.

FIG. 4 shows an example of the configuration of the core switch section 30 in the packet switching system according to the present invention. Data from the LAN side is input to the core switch unit 30 via the interface unit 8-i. The core switch unit 30 includes a common buffer 31, a multiplexing unit 32, and a demultiplexing unit 33.
However, the above configuration is a known technique of the common buffer switch disclosed in, for example, Japanese Patent Laid-Open No. 4-2766943 (switching system). That is, the buffer 31 is a random-in / random-out memory that is capable of high-speed writing of incoming N packets (N: number of input ports) and high-speed reading of N packets in response to a request from an output port. It is functioning. Incidentally, the common buffer 31 is, for example, a CMO having an on-chip RAM (Random Access Memory).
The S-LSI is used, and the buffer depth is about several hundred cells per route.

The present invention further includes a buffer controller 34 having a function of monitoring the queue length of a queue logically provided on the buffer 31, a function of counting the number of cells passing through the queue, and the like. The congestion information adding unit 35 provided for the side line is provided. As a result of the monitoring by the buffer control unit 34, if the predetermined queue length or the number of passing cells is exceeded, the congestion information adding unit 35 displays the congestion in the data cell, but the cell format of the in-device data cell Figure 7
(A). In this embodiment, the case where the congestion information is marked in the additional header is described, but the UNI or
The header portion of the NNI cell format may be marked. That is, for example, in the standard ATM cell format (53 bytes), the EFCI bit and CLP (Cell L
oss Priority) bit may be marked. By displaying congestion in the data cell, each interface 8
Indicates that congestion has occurred on the upstream side.
The same applies when data is transmitted from the WAN side to the LAN side. The processing in the interface section is as shown in FIG.

FIG. 5 shows a configuration of an example of an interface section in the packet switching system according to the present invention. Data cells from the network 40 are input to the cell buffer 11 via the line processing unit 16 that performs SDH termination, cell synchronization, and the like. As shown in FIG. 8, the input cells are queued by being classified into traffic classes such as CBR, VBR, VBR / ABR, and ABR. In particular, for the ABR class, the buffer control unit 102 performs queuing in units of virtual connections. In this cell buffer 11, the technique of the common buffer is applied similarly to the buffer 31, and the cell buffer 11
A queuing unit 101 is logically provided above. By the way,
The cell buffer 11 is, for example, a low-speed and inexpensive SRAM (St
atic Random Access Memory), and the buffer depth is about several kilocells to several tens of kilocells.

The cells from the cell buffer 11 are output through the selector 12, and the priority in outputting the cells is determined by the scheduler 10 and the buffer control unit 102 by the CBR cell, VBR cell, VBR / ABR cell,
The order is RM cell and ABR cell. Note that the class setting of the logical queue is performed by the bandwidth control table of the buffer control unit 102, as in Japanese Patent Laid-Open No. 4-276943. The VBR / ABR queue is a queue that outputs a VBR cell if it exists and outputs an ABR cell if there is no VBR cell. The bandwidth control table is a table that specifies at which time the packet is read from which queue on the common buffer, and this table is set in the buffer control unit 102.

FIG. 9 shows an example of the structure of the band control table.
As shown in the figure, the cell type and the queue number are designated as a pair according to the time slot. The output frequency for each cell type can be made variable depending on how often the combination of "cell type and queue number" occupies the time slot on the bandwidth control table. For example, as shown in FIG. 8, the CBR cell delay can be reduced by outputting the CBR traffic with the highest priority.

On the other hand, the data cells switched by the core switch section 30 shown in FIG. 5 are output buffers 20 logically provided on the common buffer 31 corresponding to the outgoing lines.
0, then passes through the RM cell extracting / folding unit 15, the shaping unit 24, and the line processing unit 16 to the network 40.
However, in the output buffer 200, if the result of monitoring by the buffer control unit 34 is that the predetermined queue length or the number of passing cells is exceeded, as described in the explanation of FIG. The addition unit 35 displays congestion on the data cell. The deployment position of the output buffer 200 provided for the outgoing line may be the RM cell extraction / folding unit 15.

Now, referring to FIG. 6, data cells are switched from the LAN through the interface section 8-i and switched by the core switch section 30 and then through the interface section 8-j to WA.
The intra-node RM cell flow in the case of being transmitted to N is shown. The intra-node feedback operation will be described below with reference to this and FIG. That is, the interface unit 8
R by the scheduler 10-i deployed in -i
An RM cell is generated from the M cell generation unit 13-i for each virtual connection of ABR traffic, and the selector 12
It is embedded in the data cell stream by -i. The insertion frequency of the RM cell is, for example, about 1 cell per 32 cells or 1 cell per 256 cells per connection. The RM cell is
The core switch unit 30 of FIG. 6 switches to the same route as the data cell flow and reaches the interface unit 8-j. The RM cell extracting / returning unit 15-j extracts the RM cell, and the RM cell is the RM cell terminating unit 14-.
After passing through j, the cell buffer 11-j, and the selector 12-j, the reverse path is followed and looped back to the interface unit 8-i. The RM cell is the RM cell extraction / folding unit 15-i.
And is terminated at the RM cell termination unit 14-i. The RM cell has congestion information collected by the RM cell extraction / return unit 15-j by the following method, for example.

That is, as the first method, the congestion indication of the data cell immediately before the RM cell is read, and if there is congestion, the control information area ((b) of FIG. 7) of the RM cell is read. The congestion indicator bit is set and the interface section 8-i is looped back. If the RM cell terminating unit 14-i reads the information and there is a congestion indication, it issues a command to the scheduler 10 to reduce the transmission rate of the connection. As a second method, the shaping unit 2
The cell rate information to be followed by the RM cell extracting / folding unit 15 is explicitly transmitted via the control line 23 based on the used band actually measured in 4-j or the calculated rate. Then, the RM cell puts this cell speed information into the control information area and is looped back to the interface unit 8-i. RM
The cell terminating unit 14-i reads the information, and based on the cell speed information, issues a command to the scheduler 10 to adjust the transmission rate of the connection. An example of the RM cell format in the device is shown in FIG. 7B, but a congestion indicator bit may be set in the control information area, and the scheduler 1
It is also possible for 0 to explicitly indicate the transmission rate to be followed.

The example in which the shaping unit 24 of the interface unit 8 has the shaping function has been described above, but the buffer control unit 34 of the core switch unit may perform shaping using a band control table. Further, the shaping unit 24 may be configured by a logical queue for each traffic class, as shown in FIG.

As described above, the input buffer for queuing corresponding to the output route, the core switch unit for performing the packet switch, and the output buffer provided for each output route are provided, and the in-channel in the node is provided. By doing flow control, you can pay for the effects of control loop delays,
It is possible to realize effective ABR, that is, traffic management in the packet switching system by flow control. In other words, by performing rate control in the input side module of the packet switch and performing feedback control so that the sum of cell flow rates from the input side module does not exceed the capacity of the output path of the core switch, multi-Qo
An S-capable single-stage packet switching system may be configured.

In any case, by periodically inserting RM cells and performing feedback control within the node, allocation of the outgoing line side band and buffer management can be efficiently performed in-channel, so that wiring dedicated to control is unnecessary. obtain. Also,
By logically dividing the buffers by traffic class, effective packet switching can be performed under the situation where CBR, VBR, and ABR traffic are mixed. Moreover, since the control delay time peculiar to the ABR closed loop feedback control can be reduced by performing the rate-based flow control in the node, an effective ABR can be realized compactly.

[0028]

As described above, according to the present invention,
By providing a packet switching system that handles a wide variety of traffic, it is possible to prevent cell discard due to cell collision in the node especially for ABR class traffic, and by performing rate-based flow control in the node, Since the control delay time peculiar to the ABR closed loop feedback control can be reduced, an effective ABR can be realized compactly.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an example of a communication network to which a packet switching system according to the present invention is applied.

FIG. 2 is a diagram showing a schematic configuration of an example of a packet switching system according to the present invention.

FIG. 3 is a diagram showing a configuration of an example of an interface unit in a packet switching system according to the present invention.

FIG. 4 is a diagram showing an example of a configuration of a core switch unit in the packet switching system.

FIG. 5 is a diagram showing a configuration of an example of an interface unit in the packet switching system according to the present invention.

FIG. 6 is a diagram showing an RM cell flow in a packet switching system according to the present invention.

7 (a) and 7 (b) are diagrams showing a format example of each of a data cell and an RM cell in the packet switching system according to the present invention.

FIG. 8 is a diagram showing an example of a queue configuration on a cell buffer in an interface section in a packet switching system according to the present invention.

FIG. 9 is a diagram showing a configuration of an example of a band control table in the packet switching system according to the present invention.

FIG. 10 is a diagram showing an ABR flow control method in a packet switching system according to a conventional technique.

[Explanation of symbols]

1 ... Public network (WAN), 2, 3 ... Packet switching system, 4, 5 ... Private network (LAN), 6, 7 ... Terminal,
8 (8a to 8n, 8a 'to 8n', 8-i, 8-j) ... interface unit, 9 ... switch, 10 ... scheduler, 1
DESCRIPTION OF SYMBOLS 1 ... Cell buffer, 12 ... Selector, 13 ... RM cell generating section, 14 ... RM cell terminating section, 15 ... RM cell extracting / returning section, 16 ... Line processing section, 17 ... ACR calculating section, 1
8 ... Cell time slot allocation unit, 19 ... Output management unit, 2
4 ... Shaping unit, 30 ... Core switch unit, 31 ... Buffer, 32 ... Multiplexing unit, 33 ... Separation unit, 34 ... Buffer control unit, 35-i, 35-j ... Congestion information addition unit, 101 ... Queuing unit, 102 ... Buffer control unit, 200 ... Output buffer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H04Q 11/04 H04Q 11/04 Z (72) Inventor Akihiko Takase 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Bunka Co., Ltd.Hitachi, Ltd.

Claims (12)

[Claims] 1. A flow control method in a network node, which uses a resource management cell to perform bandwidth allocation to a virtual connection, buffer management, or the like. 2. An input buffer for queuing for each virtual connection, a resource management cell managing means for generating, returning, and terminating a resource management cell, a scheduler for controlling a sending rate for each virtual connection, and an outgoing line. An interface unit including the traffic shaping means, an output buffer provided for the outgoing line, and a core switch unit that performs packet switching are provided, and a resource management cell is provided between the input buffer and the output buffer. A packet switching system characterized by performing bandwidth allocation to a virtual connection or buffer management. 3. The packet switching system according to claim 2, wherein the output buffer is provided in the interface section. 4. The packet switching system according to claim 2, wherein the output buffer is provided in the core switch section. 5. An interface including an input buffer for queuing for each virtual connection, a resource management cell managing means for generating, returning, and terminating a resource management cell, and a scheduler for controlling a transmission rate for each virtual connection. Section, an output buffer provided for the outgoing line, and a core switch section for performing traffic shaping of the outgoing line and packet switching are provided, and a resource management cell is provided between the input buffer and the output buffer. A packet switching system characterized by performing bandwidth allocation to a virtual connection or buffer management. 6. The packet switching system according to claim 2, wherein at least one of the input buffer and the core switch unit is configured by a common buffer. 7. The apparatus further comprises means for displaying congestion on a data cell output from the input buffer when the queue length of the input buffer or the core switch unit exceeds a predetermined value. The packet switching system according to any one of 2 and 5. 8. When the data cell has a congestion indication,
8. The packet switching system according to claim 7, wherein congestion is displayed on the resource management cell and returned to the ingress side interface unit to reduce the transmission rate. 9. The method according to claim 2, wherein when the cell speed of the outgoing line exceeds a predetermined value, congestion is displayed on the resource management cell, the congestion is returned to the incoming interface, and the outgoing rate is adjusted. The packet switching system according to any one of claims. 10. The packet switching system according to claim 2, wherein the input buffer or the buffer of the core switch is divided for each traffic class. 11. The CBR traffic of the traffic classes is output with the highest priority.
The packet switching system described. 12. An in-channel flow control is provided in a node, wherein an input buffer for queuing corresponding to an output route, a core switch unit for performing a packet switch, and an output buffer provided for each output route are provided. A packet switching system characterized in that resource management is performed by performing the following.