JPH09181184A - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

Kind Code: A1 Abstract: The capacity of wirings constituting a semiconductor integrated circuit device having a multilayer wiring structure is reduced. SOLUTION: Circuit blocks 2a to 2 of a semiconductor chip 1
In-block wiring and circuit blocks 2a to
In the inter-block wiring for electrically connecting 2e, the wiring having a relatively long wiring length is arranged in the upper wiring layer, and the wiring having a relatively short wiring length is arranged in the lower wiring layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device technique, and more particularly to a technique effectively applied to a wiring design technique of a semiconductor integrated circuit device having a multilayer wiring structure. Is.

[0002]

2. Description of the Related Art In a multilayer wiring structure, wiring for forming a semiconductor integrated circuit is stacked in multiple layers in the thickness direction of a semiconductor chip to reduce the chip size and improve the degree of integration of elements, and at the same time, to arrange the wiring. This is an important technique that can improve the degree of freedom and facilitate pattern design.

In the wiring arrangement in the multilayer wiring structure, the extending direction of the wiring of each wiring layer (direction of the wiring channel) is generally uniformly determined in the entire semiconductor chip. The direction of the wiring channel of each wiring layer is normally set to intersect with the direction of the wiring channel of the wiring layer immediately above or below the wiring channel, and the wiring channels are arranged in a grid pattern on the entire plane of the semiconductor chip. It is set.

By the way, the multilayer wiring technology studied by the present inventor is, for example, as follows. First, in the multi-layer wiring technology of four layers or more, a standard wiring method has not yet been established, and special wiring such as clock wiring or power supply wiring is placed in the uppermost wiring layer during wiring placement processing. Individual correspondence such as placement is taken.

In the case of the three-layer wiring structure, some consideration is given to the wiring length, but the limited signal wiring, which is expected to cause a significant wiring delay, is given priority to a predetermined wiring layer. The actual situation is that individual arrangements such as placement are taken.

Regarding the technique of a semiconductor integrated circuit device having a multi-layer wiring structure of three or more layers, for example, Japanese Patent Laid-Open No. 4-1
It is described in Japanese Patent No. 0624.

[0007]

However, in recent semiconductor integrated circuit devices, demands for large scale, high integration and high performance are increasing more and more, and accordingly, the size of the semiconductor chip is reduced and the operating frequency is increased. It is an important issue how to realize improvement of electric characteristics such as improvement of power consumption and reduction of power consumption. In particular, the influence of the wiring system on the electrical characteristics of the semiconductor integrated circuit device is increasing with the miniaturization of the wiring, and it is important how to arrange the wirings in the multilayer wiring structure.

An object of the present invention is to provide a technique capable of reducing the area of a semiconductor chip which constitutes a semiconductor integrated circuit device having a multilayer wiring structure.

Another object of the present invention is to provide a technique capable of improving the operation speed of a semiconductor integrated circuit device having a multilayer wiring structure.

Another object of the present invention is to provide a technique capable of reducing the power consumption of a semiconductor integrated circuit device having a multilayer wiring structure.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, in the wiring arranging step of the semiconductor integrated circuit device having four or more wiring layers on the semiconductor substrate, the wiring having a relatively long wiring length is formed. The method further includes the step of preferentially arranging the wiring in an upper wiring layer in the wiring layer and arranging a wiring having a relatively short wiring length in a lower wiring layer in the wiring layer.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the number of wiring layers used for arranging the wirings having the relatively long wiring length is set to the wiring arrangement having the relatively short wiring length. This is more than the number of wiring layers used for.

Further, in the method for manufacturing a semiconductor integrated circuit device of the present invention, the wiring layer having the wiring extending in the same extension direction as the wiring arranged in the upper wiring layer and having a relatively long wiring length is formed in the lower wiring as much as possible. It is arranged in layers.

The method of manufacturing a semiconductor integrated circuit device according to the present invention has the following steps.

(A) A step of forming the in-cell wiring and the cell terminal for forming cells of a plurality of circuit blocks by the first layer wiring.

(B) A step of changing the cell terminal to a different wiring layer depending on the formation condition of each of the plurality of circuit blocks, depending on a connection hole arranged immediately above or in the vicinity thereof.

(C) A step of forming the plurality of circuit blocks by electrically connecting the cell terminals.

Also, the method for manufacturing a semiconductor integrated circuit device of the present invention comprises a semiconductor substrate having a plurality of circuit blocks and external wiring regions arranged around the circuit blocks, and four or more wiring layers are provided on the semiconductor substrate. A method of manufacturing a semiconductor integrated circuit device having: a method of determining an extending direction of wiring in each wiring layer for each of the plurality of circuit blocks.

Also, the method for manufacturing a semiconductor integrated circuit device of the present invention comprises a plurality of circuit blocks on a semiconductor substrate and external wiring regions arranged around the circuit blocks, and four or more wiring layers are formed on the semiconductor substrate. A method of manufacturing a semiconductor integrated circuit device having a plurality of circuit blocks, wherein a predetermined wiring layer in a formation region of a predetermined circuit block is electrically connected between the plurality of circuit blocks. It is used as a wiring placement area.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings (note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments. , The repeated explanation is omitted).

(Embodiment 1) FIG. 1 is an overall plan view of a semiconductor chip constituting a semiconductor integrated circuit device of the present invention, and FIG.
1 is an enlarged plan view of an essential part of a circuit block in the semiconductor integrated circuit device of FIG. 1, FIGS. 3 and 4 are plan views of cells in the circuit block of FIG. 2, and FIGS. 5 to 7 are cells in cells of FIGS. 3 and 4. 8 is an explanatory view for explaining the structure of the terminal, FIG. 8 is a cross-sectional view of an essential part of the semiconductor integrated circuit device of FIG. 1, FIG. 9 is an explanatory view of a circuit block of the semiconductor integrated circuit device of FIG.
0 is an enlarged plan view of an essential part of the circuit block of FIG. 9, FIG. 11 is an explanatory view of the circuit block of the semiconductor integrated circuit device of FIG. 1, and FIG.
2 is an explanatory view of a problem that the circuit block area increases, FIG.
11 is an enlarged plan view of an essential part of the circuit block of FIG. 11, FIG. 14 is an enlarged plan view of an essential part of the semiconductor integrated circuit device of FIG. 1, FIG. 15 is an explanatory view of features of the semiconductor integrated circuit device of FIG. 1, and FIG. 1
17 is an enlarged plan view of an essential part of the semiconductor integrated circuit device of FIG.
FIG. 3 is an explanatory diagram of a wiring structure in an external wiring area of the semiconductor integrated circuit device of FIG.

In the first embodiment, the case where the present invention is applied to, for example, a microprocessor having a four-layer wiring structure will be described. A semiconductor chip in which this microprocessor is formed is shown in FIG. In FIG. 1, the horizontal direction of FIG. 1 is X and the vertical direction of FIG. 1 is Y.

The microprocessor formed on the semiconductor chip 1 is designed by, for example, a hierarchical arrangement method,
It is formed by a set of a plurality of circuit blocks 2a to 2e arranged on the main surface. Note that FIG. 1 shows representative circuit blocks 2a to 2e as an example. Further, a small square P0 filled in with black at the corner of each circuit block 2a to 2e indicates the origin of the block.

The circuit blocks 2a to 2e are arranged with an external wiring region 3 interposed therebetween. The external wiring area 3 is mainly divided into an inter-block wiring area and a block / external terminal wiring area.

The inter-block wiring area is an arrangement area of inter-block wiring that electrically connects the circuit blocks 2a to 2e. In addition, the wiring area between the block and the external terminal is
This is an arrangement area of wirings that electrically connect the circuit blocks 2a to 2e and the bonding pads BP near the outer periphery of the semiconductor chip 1.

The bonding pad BP is an external terminal of the microprocessor formed on the semiconductor chip 1, is electrically connected to a lead of the package through a bonding wire, and is electrically connected to an external device through this lead. It is like this.

The circuit block 2 arranged in the upper left portion of FIG.
For example, a cache controller is formed in a. The cache controller is a circuit that controls the operation of the cache memory. The circuit block 2a is formed in a rectangular shape extending along the lateral direction X in FIG.

A cache memory, for example, is formed in the circuit block 2b arranged at the left center of FIG.
The cache memory is a small-capacity high-speed memory,
It is interposed between a U (Central Processing Unit) and the main mass memory.

A circuit block 2 arranged at the lower left of FIG.
For example, a bus controller is formed in c. The bus controller, based on the information received from the CPU,
This is a circuit that decodes this and outputs a part of the system control signal instead of the CPU. The circuit block 2c is formed in a rectangular shape extending along the horizontal direction X in FIG.

The circuit block 2 arranged in the upper right part of FIG.
d1 and 2d2 are circuit blocks constituting the CPU,
Both are formed in a rectangular shape extending along the vertical direction Y of FIG.

An arithmetic control circuit for the CPU is formed in the circuit block 2d1. The arithmetic control circuit is mainly C
It is a circuit that controls the operation procedure of the arithmetic processing circuit of the PU.

Further, in the circuit block 2d2, an arithmetic processing circuit of the CPU is formed. The arithmetic processing circuit is a circuit that obtains a predetermined result mainly by performing four arithmetic operations or the like on input data.

Circuit block 2 arranged in the lower right part of FIG.
For example, a clock generator is formed in e. The clock generator is a circuit that generates a clock signal, and the entire microprocessor is synchronized by this clock signal. This circuit block 2e
Are formed in a rectangular shape extending in the vertical direction Y of FIG.

The division unit, the number of divisions, the position, the shape, etc. of each of the circuit blocks 2a to 2e are the cells prepared in advance.
It is determined by the contents of the library and the floor plan method. In this floorplan processing, for example, the overall configuration of the chip layout is determined so that the chip size is minimized and the timing of inter-block signals is optimized.

A plurality of cells required to realize each circuit function are arranged in each of the circuit blocks 2a to 2e, and each circuit block 2a to 2e has an intra-block wiring between the cells. It is formed by electrically connecting.

This cell is a minimum design unit when hierarchically designing a circuit block or the like, and usually corresponds to a minimum unit of logic design such as a NAND circuit, a NOR circuit or an inverter circuit. The intra-block wiring is a wiring that forms a circuit block having a predetermined circuit function by electrically connecting the cells.

Here, such circuit blocks 2a to 2
FIG. 2 shows the configuration of the circuit block 2c as a representative of e.
The other circuit blocks 2a, 2b, 2d1, 2d in FIG.
2, 2e basically have the same structure. However, the circuit blocks 2d1 and 2d2 are in a state in which FIG. 2 is rotated by 90 degrees. Further, the horizontal direction X and the vertical direction Y in FIG. 2 are described so as to match the horizontal direction X and the vertical direction Y in FIG.

In the circuit block 2c, the horizontal direction X in FIG.
A plurality of cell columns 4 extending along the vertical direction Y are arranged along the vertical direction Y in FIG. A plurality of cells 4a having different sizes are arranged adjacent to each other in each cell row 4 along the extending direction thereof. The internal wiring region 5 is a region for arranging the intra-block wiring ML that electrically connects the cells 4a.

Next, an example of this cell 4a is shown in FIGS. 3 and 4 are plan views of the same cell 4a, the plan views are shown at different stages for easy understanding of the drawings. That is, FIG. 3 shows a plan view at the stage of forming the gate electrode, and FIG. 4 shows a plan view at the stage of forming the first wiring layer.

The cell 4a includes an n-channel type MOS.
・ FET (Metal Oxide Semiconductor Field Effect T
A plurality of ransistors (hereinafter, simply referred to as nMOS) 6n and a plurality of p-channel type MOS • FETs (hereinafter, simply referred to as pMOS) 6p are arranged. These nMOS6n
And pMOS6p, for example, CMOS (Compli
mentary MOS) circuit is formed.

The semiconductor region 6nL forming the source / drain region of the nMOS 6n is formed by a rectangular region containing, for example, n-type impurity phosphorus or arsenic (As). Further, the semiconductor region 6pL forming the source / drain region of the pMOS 6p is formed by a rectangular region containing, for example, p-type impurity boron.

The gate electrodes 6ng and 6pg of the nMOS 6n and the pMOS 6p are formed, for example, in a rectangular shape extending in the vertical direction of FIGS. 3 and 4, and are integrally formed with each other to form a CMOS circuit. Connected to each other. In addition, the connection portion of the gate electrodes 6ng and 6pg is formed to be wide and serves as a gate lead electrode 6g.

The source, drain and gate electrodes of these nMOS 6n and pMOS 6p are the first layer wiring ML1.
A cell 4a having a predetermined basic circuit function is formed by being drawn out and electrically connected as appropriate. That is, the internal circuit of the cell 4a is formed by the first layer wiring ML1. The first layer wiring ML1 constitutes a part of the intra-block wiring.

Incidentally, in FIG. 4, the first layer wiring ML1 is hatched in order to make the drawing easy to see. Further, VDD indicates a power supply potential and VSS indicates a ground potential. Also, V
IA1 is the first layer wiring ML1 and nMOS 6n and pMO
The connection hole for electrically connecting with the electrode part of S6p is shown.

Next, the terminal structure for leading out the electrode of the cell 4a will be described with reference to FIGS.

As shown in FIG. 5, the cell terminal CT is arranged near a straight line that bisects the length of the cell 4a in the vertical direction Y. This is because the arrangement of the cell terminals CT has regularity to facilitate the wiring installation process.

The cell terminal CT is a portion which serves as an interface portion of the cell 4a when the cell 4a is referred to from a higher hierarchy in order to design a predetermined circuit block or the like.
For example, in the case of a 2-input NAND, two input signal terminals and one output signal terminal correspond to this cell terminal CT. In the first embodiment, this cell terminal C
T is formed by, for example, the first layer wiring ML1.

The connection between the cells 4a is made by electrically connecting the cell terminals CT. The wiring condition between the cells 4a varies depending on the number of wiring layers and the wiring structure adopted, but in the first embodiment, this cell terminal CT is unrelated to the circuit in the cell 4a at the stage of wiring layout design. The cell structure itself can be shared and the cell library can be integrated. Specifically, in the wiring process, connection holes for electrically connecting the cells 4a are provided immediately above or in the vicinity of the cell terminals CT, and the connection holes are connected.

For example, as shown in FIG. 6, the horizontal direction X in FIG.
When the first layer wiring ML1 and the fourth layer wiring ML4 are used as the wirings extending in the vertical direction and the second layer wiring ML2 and the third layer wiring ML3 are used as the wirings extending in the vertical direction Y in FIG. , A connection hole VIA21 that electrically connects the first layer wiring ML1 and the second layer wiring ML2 directly above the cell terminal CT.
And a connection hole VIA31 for electrically connecting the first layer wiring ML1 and the third layer wiring ML3.
The area where the cell terminal CT is not present is the second area as shown by the chain double-dashed line.
It becomes an arrangement region of the layer wiring ML2 or the third layer wiring ML3.

Although not shown in FIG. 6, the second layer wiring and the fourth layer wiring are used as the wirings extending in the horizontal direction X of FIG. 6, and the wirings extending in the vertical direction Y of FIG. 6 are used. When the third layer wiring is used, it is realized by arranging a connection hole for electrically connecting the first layer wiring and the third layer wiring directly above the cell terminal.

Although not shown in FIG. 6, the first layer wiring and the third layer wiring are used as the wirings extending in the horizontal direction X of FIG. 6, and the wirings extending in the vertical direction Y of FIG. 6 are used. When the second layer wiring is used, it is realized by arranging a connection hole that electrically connects the first layer wiring and the second layer wiring directly above the cell terminal.

In FIG. 6, the wirings of the respective layers other than the first layer wiring ML1 are hatched in order to make the drawing easy to see. The VIA 43 is connected to the fourth layer wiring ML4 and the third layer wiring ML4.
This is a connection hole for connecting to the layer wiring ML3.

A cross-sectional structure of such a connection hole is schematically shown in FIG. Each wiring layer is electrically connected by one connection hole VIA. For example, in order to change the cell terminal CT from the first layer wiring ML1 to the third layer wiring ML3, that is, to realize the connection hole VIA31 of FIG. 6, the first layer wiring ML1 and the second layer wiring ML2 are connected. Connection hole VIA2
This is realized by providing a connection hole VIA32 for connecting the second layer wiring ML2 and the third layer wiring ML3 on the first layer.

Further, for example, the cell terminal CT is connected to the first layer wiring M.
To change from L1 to the fourth layer wiring ML4, a connection hole VIA21 for connecting the first layer wiring ML1 and the second layer wiring ML2.
A connection hole VIA32 for connecting the second-layer wiring ML2 and the third-layer wiring ML3 is provided above the connection hole VIA43 for connecting the third-layer wiring ML3 and the fourth-layer wiring ML4.
It is realized by providing.

In this way, the cell terminal CT is connected to the first layer wiring M.
L1 to form a connection hole VIA in the cell terminal C during wiring processing.
By arranging just above T, it is not necessary to prepare a cell having a cell terminal layer suitable for each time the wiring style changes, and one cell library can support various wiring styles. Has become.

As can be seen from FIG. 7, the first layer wiring M
Connection hole V for electrically connecting L1 and the third layer wiring ML3
The wiring area of the fourth layer wiring ML4 can be used on the IA, and the wiring area of the third layer wiring ML3 can be used on the connection hole VIA that electrically connects the first layer wiring ML1 and the second layer wiring ML2. Can be used as.

Next, a semiconductor chip 1 including this cell 4a
FIG. 8 shows a cross-sectional view of the main part (see FIG. 1).

Semiconductor substrate 1s constituting the semiconductor chip 1
Consists of, for example, p-type silicon (Si) single crystal,
A field insulating film 7 for element isolation made of, for example, silicon dioxide (SiO ₂ ) is formed on the upper portion thereof.

A p-well PW is formed on the semiconductor substrate 1s.
And an n well NW are formed. This p-well P
For example, p-type impurity boron is introduced into W.
Further, for example, n-type impurity phosphorus or As is introduced into the n-well NW.

On the p well PW and the n well NW, nMOS 6n and pMOS 6 are respectively provided.
p is formed.

These nMOS 6n and pMOS 6p
Thus, a CMOS (Complimentary MOS) circuit is formed, and cells having a predetermined circuit function are formed.

The nMOS 6n includes a pair of semiconductor regions 6nL formed above the p well PW and separated from each other, a gate insulating film 6ni formed on the semiconductor substrate 1s, and a gate electrode 6ng formed thereon. have.

The semiconductor region 6nL is a region for forming source / drain regions of the nMOS 6n, has a low impurity concentration region 6nL1 and a high impurity concentration region 6nL2, and contains, for example, n-type impurity phosphorus or As. Formed. In addition, between the semiconductor region 6 nL, nM
A channel region of OS6n is formed.

The gate insulating film 6ni is made of, for example, SiO ₂ . The gate electrode 6ng is made of, for example, low resistance polysilicon. However, the gate electrode 6ng is not limited to be formed of a single film of low resistance polysilicon, and may be formed of, for example, a laminated film in which a silicide film is deposited on the low resistance polysilicon film.

On the upper surface of the gate electrode 6ng, for example, Si
A cap insulating film 8 made of O ₂ is formed. A protective film 9 made of, for example, silicon nitride is formed on the surfaces of the gate electrode 6ng and the cap insulating film 8. The protective film 9 has a function of suppressing the characteristic variation of the nMOS 6n. Further, a sidewall 10 made of, for example, SiO ₂ is formed on the side surface of the protective film 9.

The pMOS 6p includes a pair of semiconductor regions 6pL formed above the n well NW and spaced from each other, a gate insulating film 6pi formed on the semiconductor substrate 1s, and a gate electrode 6pg formed thereon. have.

The semiconductor region 6pL is a region for forming source / drain regions of the pMOS 6p, has a low impurity concentration region 6pL1 and a high impurity concentration region 6pL2, and is formed by containing, for example, p-type impurity boron. Has been done. The pMOS 6p is provided between the semiconductor regions 6pL.
Is formed. In addition, the semiconductor region 11a existing under the low impurity concentration region 6pL1 is pMO.
This is a punch-through stopper for preventing punch-through in S6p.

The gate insulating film 6pi is made of, for example, SiO ₂ . The gate electrode 6pg is made of, for example, low resistance polysilicon. However, the gate electrode 6pg is not limited to being formed of a single film of low resistance polysilicon, and may be formed of, for example, a laminated film in which a silicide film is deposited on the low resistance polysilicon film.

On the upper surface of the gate electrode 6pg, for example, Si
A cap insulating film 8 made of O ₂ is formed. A protective film 9 made of, for example, silicon nitride is formed on the surfaces of the gate electrode 6pg and the cap insulating film 8. The protective film 9 has a function of suppressing the characteristic variation of the pMOS 6p. Further, a sidewall 10 made of, for example, SiO ₂ is formed on the side surface of the protective film 9.

On such a semiconductor substrate 1s, an interlayer insulating film 12a made of, for example, SiO ₂ is deposited,
As a result, the nMOS 6n and the pMOS 6p are covered.

The thickness of the interlayer insulating film 12a is, for example, 0.
It is about 60 μm. The upper surface of the interlayer insulating film 12a is
For example, it is planarized by a CMP (Chemical Mechanical Polishing) process, an etch back process, a reflow planarization process, or the like, and the upper surface of the first layer wiring ML1 made of, for example, an aluminum (Al) -Si-copper (Cu) alloy. Are formed.

The first-layer wiring ML1 is a part of the above-mentioned intra-block wiring, and the nMOS 6n is formed through the conductor film ML1a in the connection hole VIA formed in the interlayer insulating film 12a.
And the semiconductor region 6nL of the pMOS 6p are electrically connected. The conductor film ML1a is made of, for example, tungsten or the like, and is formed by a metal film burying technique such as a selective CVD method. The thickness of the first layer wiring ML1 is, for example, about 0.61 μm.

The first layer wiring ML1 as described above is covered with the interlayer insulating film 12b. Interlayer insulating film 12b
Is made of, for example, SiO ₂ , and its thickness is, for example, 1.3.
It is about 1.4 μm.

The upper surface of the interlayer insulating film 12b is, for example, C
It is flattened by MP treatment, etch back treatment, reflow flattening treatment, or the like.
A second layer wiring ML2 made of --Si--Cu alloy is formed. The thickness of the second layer wiring ML2 is, for example, 0.61 μm.
It is a degree.

The second-layer wiring ML2 is a part of the above-mentioned intra-block wiring, and the first-layer wiring M is formed through the conductor film ML2a in the connection hole VIA formed in the interlayer insulating film 12b.
It is electrically connected to L1. The conductor film ML2 a is made of, for example, tungsten or the like, and is formed by a metal film burying technique such as a selective CVD method.

The second layer wiring ML2 is covered with an interlayer insulating film 12c. The interlayer insulating film 12c is made of, for example, SiO ₂ , and its thickness is, for example, 1.3 to 1.4 μm.
m.

The upper surface of the interlayer insulating film 12c is, for example, C
It is flattened by MP treatment, etch back treatment, reflow flattening treatment, or the like.
A third layer wiring ML3 made of --Si--Cu alloy is formed. The thickness of the third layer wiring ML3 is, for example, 1.06 μm.
It is a degree.

The third-layer wiring ML3 is a part of the above-mentioned intra-block wiring, and the second-layer wiring M is formed through the conductor film ML3a in the connection hole VIA formed in the interlayer insulating film 12c.
It is electrically connected to L2. The conductor film ML3a is made of, for example, tungsten or the like, and is formed by a metal film burying technique such as a selective CVD method.

The third layer wiring ML3 is covered with an interlayer insulating film 12d. The interlayer insulating film 12d is made of, for example, SiO ₂ . The upper surface of the interlayer insulating film 12d is
For example, it is flattened by CMP treatment, etch back treatment, reflow flattening treatment, or the like, and a fourth layer wiring ML4 made of, for example, an Al—Si—Cu alloy is formed on the upper surface thereof.

The fourth-layer wiring ML4 is a part of the above-mentioned intra-block wiring, and the third-layer wiring M is formed through the conductor film ML4a in the connection hole VIA formed in the interlayer insulating film 12d.
It is electrically connected to L3. The conductor film ML4a is made of, for example, tungsten or the like, and is formed by a metal film burying technique such as a selective CVD method.

SiO ₂ is formed on the interlayer insulating film 12d.
The surface protection film 13 is formed of an insulating film formed by depositing a silicon nitride film on the SiO ₂ film, an insulating film formed by further depositing a polyimide resin film thereon, and the like. The four-layer wiring ML4 is covered. An opening is formed in a part of the surface protective film 13 so that the bonding pad BP portion of the fourth layer wiring ML4 is exposed.

By the way, in the first embodiment, the wiring forming the microprocessor is, for example, the following first wiring.
~ Arrange according to the fourth condition.

The first condition is that each of the circuit blocks 2a to 2e.
In FIG. 1, among the intra-block wirings, wirings having a long wiring length are arranged in the upper wiring layer as much as possible, and wirings having a short wiring length are arranged in the lower wiring layer as much as possible.

The length of this wiring is relative, and is determined by where the wiring belongs to in the wiring length distribution. For example, long wiring means that the wirings in the blocks after the placement processing are ordered and arranged based on the wiring length, and then 50% from the longer wiring length in all the wirings ML in the block.
The short wiring can be said to be a wiring within 50% of the wiring having the shorter wiring length among the wirings ML in all the blocks. However, this 50% is merely an example, and can be appropriately changed depending on conditions such as design conditions and device conditions.

This is because the wiring capacitance of the upper wiring layer can be made smaller and the problem of wiring delay due to the wiring capacitance can be solved. That is,
By arranging a long wire, which tends to have a large wiring capacity, in the upper wiring layer and a short wire, which has a relatively small wiring capacity, in the lower wiring layer, the overall wiring capacity in the circuit blocks 2a to 2e can be improved. Therefore, it is possible to improve the signal transmission speed in the intra-block wiring in the circuit blocks 2a to 2e, and the circuit block 2a can be reduced.
This is because it is possible to reduce the power consumption within 2e.

The second condition is that each of the circuit blocks 2a to 2e.
The way of arranging the intra-block wiring in each block is changed according to the congestion state of the intra-block wiring in each of the circuit blocks 2a to 2e.

This is mainly the circuit blocks 2a to 2e.
The purpose is to reduce the area occupied by. That is,
In some cases, the congestion status of the intra-block wiring in each of the circuit blocks 2a to 2e may differ depending on the geometrical elements of each of the circuit blocks 2a to 2e. In that case, the wiring arrangement method is uniform throughout the semiconductor chip 1. Instead of setting each of the circuit blocks 2a to 2e,
This is because it is possible to reduce the occupied area of a to 2e.

Here, such first condition and second condition
A specific example of the intra-block wiring formed under the condition of will be described with reference to FIGS. 1 and 9 to 13. In FIGS. 10, 12 and 13, in order to make the drawings easy to see, the second layer wirings forming the intra-block wirings are dot-shaped hatching, the third layer wirings are right-hatched linear hatching, and the fourth layer wirings are The layer wiring is hatched in a left slanting line shape, and the first wiring layer forming the inter-block wiring is not hatched.

For example, the circuit block 2c that is long in the horizontal direction X in FIG. 1 and the circuit block 2e that is slightly long in the vertical direction Y in FIG.

That is, as shown in FIG. 9, in the case of the circuit block 2c long in the horizontal direction X (YL / XL <1; YL is the length in the vertical direction Y in the circuit block 2c, XL is the horizontal direction in the circuit block 2c). (Length of X), the degree of congestion of the wiring extending along the vertical direction Y of FIG.
The degree of congestion of the wiring extending along the line is large.

Therefore, if the normal wiring arrangement method is adopted, the width of the wiring area in the block (length in the vertical direction Y) must be increased, and the area of the circuit block 2c increases.

Therefore, in the first embodiment, after taking the above-mentioned first condition into consideration, for example, as shown in FIG. That is, as the wiring extending in the direction (vertical direction Y) orthogonal to the extending direction of the cell row 4, the third layer wiring ML.
3 is used as the wiring extending in the direction parallel to the extending direction of the cell row 4 (lateral direction X), the second layer wiring ML2 and the fourth layer wiring ML2.
The layer wiring ML4 is used. The first layer wiring ML1
Is mainly used as a wiring in the cell 4a.

As a result, since two wiring layers can be used in the horizontal direction X, the internal wiring area 5 (see FIG. 9) can be used.
Can be reduced in width (length in the vertical direction Y). For example, if four wiring channels are required in the internal wiring area 5,
In order to form this with only one wiring layer, an area for arranging four wirings side by side is required, whereas
In the case of the first embodiment, two wiring layers can be used,
Since the two wirings can be arranged so as to overlap each other, it is sufficient if there is an area for arranging the two wirings side by side. Therefore, the length of the circuit block 2c (see FIG. 1) in the vertical direction Y can be reduced, and the area of the circuit block 2c can be reduced.

The wiring having a long wiring length is the fourth layer wiring M.
The wiring formed of L4 and the third layer wiring ML3 and having a short wiring length is formed of the second layer wiring ML2 and the third layer wiring ML3. As a result, in addition to shortening the wiring length of the intra-block wiring by reducing the area of the circuit block 2c, the wiring capacitance of the intra-block wiring of the circuit block 2c can also be reduced, so that the operating speed of the circuit block 2c is improved. It is possible to reduce power consumption.

Also, the cell terminal C formed by the first layer wiring
T is pulled up to the third layer wiring ML3 by the connection hole VIA31 formed by the wiring process to change the cell terminal CT. Therefore, even if the wiring arrangement of the circuit block 2c is different from that of the other circuit blocks, it can be dealt with by the wiring process, and the cell 4a itself (cell terminal CT) does not need to be changed at the time of wiring layout design. The cells 4a can be shared when designing the wiring layout.

On the other hand, as shown in FIG. 11, in the case of the circuit block 2e slightly longer in the vertical direction Y (YL / XL ≧ 1), the degree of congestion of the wirings extending along the horizontal direction X in FIG. 11 is small. The degree of congestion of the wirings extending along the vertical direction Y is large.

For this reason, if a normal wiring arrangement method is adopted, it becomes necessary to form an empty area for the wiring channel in the cell row 4, and as a result, the extending direction of the cell row 4 becomes long and the circuit block 2e. Area will increase. This will be described with reference to FIG.

In FIG. 12, the second layer wiring ML2 is used as the wiring extending in the direction (vertical direction Y) orthogonal to the extending direction of the cell row 4, and the second layer wiring ML2 is used in the direction parallel to the extending direction of the cell row 4 (horizontal direction). The third layer wiring ML3 is used as the wiring extending in the direction X). The first layer wiring ML1 is mainly used for the cell 4a.
It is used as the wiring inside.

In this case, a region without the cell terminals CT is a wiring arrangement region in the direction (vertical direction Y) orthogonal to the cell row 4. However, if the degree of congestion of the wirings in the orthogonal direction increases, the number of wiring arrangement areas without the cell terminals CT becomes insufficient with respect to the number of wirings in the orthogonal direction. Therefore, an empty area A for arranging the wiring in the orthogonal direction is required between the cells 4a. In this empty area A, the first layer wiring ML1 for power supply between the cells 4a is arranged, but the transistor and the wiring pattern constituting it are not formed. Therefore, the increase in the empty area A increases the area of the circuit block.

Therefore, in the first embodiment, the above-mentioned first condition is taken into consideration, for example, as shown in FIG. That is, the in-block wiring extending in the direction (vertical direction Y) orthogonal to the extending direction of the cell row 4 is formed by the second layer wiring ML2 and the third layer wiring ML3, and the direction parallel to the extending direction of the cell row 4 is formed. The intra-block wiring extending in the (horizontal direction X) is formed by the first layer wiring ML1 and the fourth layer wiring ML4. However, the third layer wiring ML3 and the fourth layer wiring M
The layout of L4 may be reversed. The first layer wiring M
L1 is mainly used as a wiring in the cell 4a.

As a result, it is possible to use two wiring layers in the vertical direction Y where the intra-block wiring has a large congestion degree.
In addition, the direction Y where the degree of congestion is large also immediately above the connection hole VIA21 between the second layer wiring ML2 and the cell terminal CT of the first layer wiring ML1.
It can be used as an arrangement area for wiring in the block. As a result, it becomes less necessary to provide the empty area A in the cell row 4. Therefore, since the length of the cell row 4 in the extending direction can be reduced, the length of the circuit block 2e in the lateral direction X can be reduced, and the area of the circuit block 2e can be reduced. .

The wiring having a long wiring length is the fourth layer wiring M.
L4 and the third layer wiring ML3 are formed, and the wiring having a short wiring length is formed by the first layer wiring ML1 and the second layer wiring ML2. As a result, in addition to shortening the wiring length of the intra-block wiring by reducing the area of the circuit block 2e, the wiring capacitance of the intra-block wiring of the circuit block 2e can also be reduced, so that the operating speed of the circuit block 2e is improved. It is possible to reduce power consumption.

In the intra-block wiring in the circuit block 2e, the wiring extending in parallel with the fourth wiring ML4 having a long wiring length is constituted by the first wiring ML1.
Since the distance between the wiring layers can be increased, the coupling capacitance between them can be reduced.

Further, the cell terminals CT formed by the first layer wiring are connected to the connection holes VIA31, VIA formed by the wiring process.
By 21 the cell terminal CT is changed by pulling it up to the third layer wiring ML3 or the second layer wiring ML2. Thus, even if the wiring arrangement in the circuit block 2e is different from that of the other circuit blocks, it can be dealt with by the wiring processing, and the cell 4a itself (cell terminal CT) does not need to be changed at the time of wiring layout design. The cells 4a can be shared when designing the wiring layout.

Next, the third condition is that, when forming a predetermined circuit block, not using all the wiring layers but using a predetermined wiring layer as an arrangement area for inter-block wiring. This is, for example, the following case.

For example, this is a case where the wiring congestion of the circuit block is low. In addition, in the case of forming a predetermined circuit block, the area of the circuit block is not reduced even if the entire wiring layer is used as an arrangement area of the wiring in the block. However, in this case, if the use of all the wiring layers contributes to the reduction of the area of the circuit block, all the wiring layers are used as the use area of the wiring in the block.

The fourth condition is that among the inter-block wirings connecting the circuit blocks 2a to 2e of FIG. 1, the wiring having the long wiring length is arranged in the upper wiring layer as much as possible, and the wiring length is short. Wiring should be placed in the lower wiring layer as much as possible.

The definition of the length of this wiring is the same as that explained in the above-mentioned wiring in the block. The reason for doing this is also the same as that explained for the intra-block wiring.
That is, by arranging a long wire, which tends to have a large wiring capacity, in the upper wiring layer and a short wire, which requires a relatively small wiring capacity, in the lower wiring layer, the wiring capacity of the entire inter-block wiring is reduced. This is because it is possible to improve the signal transmission speed in the inter-block wiring, and it is possible to reduce the power consumption of the microprocessor.

Here, such a third condition and a fourth condition
A specific example of the inter-block wiring formed under the condition of will be described with reference to FIGS. 1 and 14 to 17.

In FIGS. 14 and 16, in order to make the drawings easier to see, the second block for forming the inter-block wiring is formed.
The layer wirings have dot-like hatching, the third layer wirings have right slanting line hatching, and the fourth layer wirings have left slanting line hatching. In addition, the first that constitutes the wiring between blocks
The wiring layers are not hatched.

As an example according to the third condition, for example, FIG.
The circuit block 2b is formed by a three-layer wiring structure without using all four wiring layers. That is,
No intra-block wiring is arranged in the fourth wiring layer in the formation region of the circuit block 2b. Therefore, the fourth wiring layer in the formation region of the circuit block 2b is used as an arrangement region of the inter-block wiring MLB4 connecting the circuit blocks 2a and 2c, as shown in FIG.

As a result, for example, the circuit blocks 2a, 2
Since the wiring length of the inter-block wiring can be shortened when connecting between c as compared with the case where the circuit block 2b is bypassed and connected, the wiring capacitance and the wiring resistance can be reduced, and the inter-block wiring can be reduced. It is possible to improve the signal transmission speed of.

Further, in connecting the circuit blocks 2a and 2c, the number of connection holes can be reduced as compared with the case where the circuit block 2b is bypassed and connected, so that the connection between the circuit blocks 2a and 2c can be reduced. It is possible to improve reliability.

An example of wiring arrangement under the above first to third conditions is collectively shown in FIG. In FIG. 15,
The method of arranging the wiring in the block (wiring direction, wiring length) according to the wiring condition in each of the circuit blocks 2a to 2e and the characteristics in each case are described.

On the other hand, in the external wiring region 3 connecting between the circuit blocks 2a to 2e of FIG. 1, in order to satisfy the above-mentioned fourth condition, the wiring between the blocks is changed according to the shape of each external wiring region 3. The way of arrangement is changed.

That is, the inter-block wiring extending along the extending direction (longitudinal direction) of the external wiring region 3 is arranged in the upper wiring layer as much as possible, for example, the third wiring layer or the fourth wiring layer. This is because the wiring extending along the extending direction of the external wiring region 3 is a relatively long wiring. Figure 1
4, FIG. 16 and FIG.

14 and 16 show the shapes of the external wiring regions 3a to 3f. External wiring area 3a,
3d and 3f have a rectangular shape extending in the vertical direction Y of FIG. 14 or FIG. 16, and are external wiring regions 3b, 3c, 3
e has a rectangular shape extending in the lateral direction X of FIG. 14 or 16.

In any of the external wiring regions 3a to 3f, the inter-block wiring along the extending direction is formed by the first layer wiring MLB1 and the fourth layer wiring MLB4,
The inter-block wiring along the short direction of the external wiring regions 3a to 3f is formed by the second layer wiring MLB2 and the third layer wiring MLB3.

Among the inter-block wirings, the wiring having a long wiring distance is preferentially formed by the combination of the third layer wiring MLB3 and the fourth layer wiring MLB4, and the wiring having a short wiring distance is the first layer wiring MLB1. It is preferentially formed in combination with the second layer wiring MLB2.

Further, in the area where the external wiring areas 3a to 3f intersect, the change of the wiring layer is minimized. For example, when the fourth layer wiring MLB4 in the external wiring region 3f shown in FIG. 16 extends to the external wiring region 3e as it is, the following procedure is performed. The subsequent processing is the same for the first layer wiring MLB1.

Fourth layer wiring MLB in the external wiring region 3f
When 4 is an obstacle to the fourth layer wiring MLB4 extending in the lateral direction (direction X) in the external wiring area 3e, the fourth layer wiring M extending from the external wiring area 3f to the external wiring area 3e.
LB4 is once pulled down to the third layer wiring MLB3 by the connection hole VIA in the intersecting region of the external wiring regions 3e and 3f.

However, if the fourth layer wiring MLB4 extending from the external wiring region 3f to the external wiring region 3e does not obstruct the fourth layer wiring MLB4 extending in the lateral direction X in the external wiring region 3e, The wiring is extended without switching the wiring layer.

As described above, among the inter-block wirings in the external wiring region 3, the wiring having a longer wiring length is formed by the fourth layer wiring MLB4 having a smaller wiring capacity than the other wiring layers. It is possible to reduce the wiring capacitance of the wiring MLB4. In addition, the fourth layer wiring ML
By using the first layer wiring MLB1 as the wiring extending in parallel with B4, the distance between the wirings can be increased, so that the coupling capacitance between them can be reduced. .

As a result, the wiring capacity of the inter-block wiring in the entire external wiring area 3 can be reduced, so that the signal transmission speed in the inter-block wiring can be improved and the power consumption of the microprocessor can be reduced. It becomes possible.

Further, in the region where the external wiring region 3 intersects, the connection holes can be arranged so as to overlap the upper and lower wiring layers, and the area thereof can be reduced, so that the width of the external wiring region 3 can be reduced. be able to. Therefore, the area of the semiconductor chip 1 can be reduced. Further, since the wiring length of the inter-block wiring can be shortened by reducing the area of the semiconductor chip 1, it is possible to further improve the signal transmission speed in the inter-block wiring.

An example of the wiring layout under the above fourth condition is collectively shown in FIG. FIG. 17 shows how the inter-block wiring is arranged (wiring direction, wiring length) according to the geometrical elements of the external wiring area.

As described above, according to the first embodiment, the following effects can be obtained.

(1). In the intra-block wirings ML configuring the circuit blocks 2a to 2e, long wirings that tend to have large wiring capacitances are arranged in the upper wiring layer, and short wirings that require relatively small wiring capacitances are formed in the lower wiring layer. It is possible to reduce the overall wiring capacitance in the circuit blocks 2a to 2e by arranging the wiring layers in the wiring layer.

(2). In the intra-block wiring in the circuit block 2e, the wiring extending in parallel with the fourth wiring ML4 having a long wiring length is constituted by the first-layer wiring ML1. Since the interval can be increased,
It is possible to reduce the coupling capacity between them.

(3). At the wiring designing stage, how to arrange the wirings of the circuit blocks 2a to 2e is as follows.
By adopting a method suitable for each 2e, it becomes possible to reduce the occupied area of each circuit block 2a to 2e.

(4) Since the wiring length of the intra-block wiring can be shortened by the above (3), the wiring capacitance and wiring resistance of the intra-block wiring can be reduced.

(5). According to the above (1) and (4), the circuit block 2
Since it is possible to improve the signal transmission speed in the intra-block wirings in a to 2e, it is possible to improve the operating speed of the circuit blocks 2a to 2e.

(6). According to the above (1) and (4), the circuit block 2
It is possible to reduce the power consumption within a to 2e.

(7). In the inter-block wiring for electrically connecting the circuit blocks 2a to 2e, a long wiring whose wiring capacitance is likely to be large is arranged in the upper wiring layer, and the wiring capacitance is relatively small. By arranging the wiring in the lower wiring layer, it becomes possible to reduce the overall wiring capacitance of the inter-block wiring.

(8) In the inter-block wiring, the wiring extending in parallel with the fourth wiring layer MLB4 having a long wiring length is constituted by the first layer wiring MLB1 to increase the distance between the wiring layers. Therefore, it is possible to reduce the coupling capacity between them.

(9). By forming the internal circuit of the circuit block 2b with a three-layer wiring structure and using the fourth wiring layer as an arrangement area for the inter-block wiring, it is not necessary to bypass the inter-block wiring. Since the area for disposing the bypass wiring is not necessary, the area of the semiconductor chip 1 can be reduced accordingly.

(10). By forming the internal circuit of the circuit block 2b with a three-layer wiring structure and using the fourth wiring layer as the inter-block wiring arrangement area, the circuit blocks 2a and 2c can be connected to each other. Since the wiring length of the inter-block wiring can be shortened as compared with the case where the circuit block 2b is bypassed and connected, the wiring capacitance and wiring resistance of the inter-block wiring can be reduced.

(11). By forming the internal circuit of the circuit block 2b with a three-layer wiring structure and using the fourth wiring layer as the inter-block wiring arrangement area, the circuit blocks 2a and 2c can be connected to each other. Since it is possible to reduce the number of the connection holes VIA as compared with the case where the circuit block 2b is bypassed and connected, it is possible to improve the reliability of the connection between the circuit blocks 2a and 2c.

(12). In the area where the external wiring area 3 intersects, the connection hole VIA can be arranged so as to overlap the upper and lower wiring layers, and the area thereof can be reduced. Therefore, the width of the external wiring area 3 can be reduced. Can be reduced.

(13) Since the wiring length of the inter-block wiring can be shortened by the above (12), the wiring capacitance and wiring resistance in the inter-block wiring can be reduced.

(14). By the above (7), (8), (10), (13), it is possible to improve the signal transmission speed in the inter-block wiring that electrically connects the circuit blocks 2a to 2e. Becomes

(15). Due to the above (3) and (14), the operating speed of the entire microprocessor can be improved.

(16). Due to the above (3), (9) and (12), it is possible to significantly reduce the entire area of the semiconductor chip 1.

(17). The power consumption of the microprocessor can be reduced by the above (6) to (8), (10) and (13).

(18). By arranging the wiring along the longitudinal direction of the external wiring region 3 preferentially in the fourth wiring layer when arranging the inter-block wiring for electrically connecting the circuit blocks 2a to 2e. It becomes possible to arrange long wiring in the upper wiring layer.

(19). Cell terminal C formed by the first layer wiring
By raising T to a predetermined wiring layer by the connection hole VIA formed by the wiring process and changing the wiring layer in which the cell terminal CT is arranged, the cell 4a can be shared during the wiring layout design. Therefore, even if the wiring arrangement is different for each of the circuit blocks 2a to 2e, it is possible to deal with it with one cell library. Therefore, it is possible to significantly reduce the design period of the method for manufacturing a semiconductor integrated circuit device.

(Second Embodiment) FIG. 18 is an enlarged plan view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the second embodiment, the case where the present invention is applied to, for example, a microprocessor having a five-layer wiring structure will be described. The other points are the same as those in the first embodiment.

In the second embodiment, for example, FIG.
As shown in, the third layer wiring ML3 and the fourth layer wiring ML4 are used in a direction (longitudinal direction Y) orthogonal to the extending direction of the cell row 4 and a direction parallel to the extending direction of the cell row 4 (horizontal direction). Direction X)
The second layer wiring ML2 and the fifth layer wiring ML5 are used. As a result, the two upper wiring layers of the cell 4a can be used in both the horizontal direction X and the vertical direction Y, which is very effective in reducing the area of the circuit block.

The wiring having a long wiring length is the fifth layer wiring M.
L5 and the fourth layer wiring ML4 are used, and the wiring having a short wiring length uses the third layer wiring ML3 and the second layer wiring ML2.

That is, the long wiring is arranged in the upper wiring layer having a relatively small wiring capacitance, and the wiring extending in parallel with the long wiring is arranged in the lower layer separated from the two layers of the interlayer insulating film to form a multilayer structure. By reducing the wiring capacitance formed between the wirings, it is possible to reduce the wiring capacitance of the wiring in the block.

The cell terminal C formed of the first layer wiring
T denotes a connection hole VIA31, VIA41 formed by a wiring process.
Thus, the wiring layer position of the cell terminal CT is changed by pulling up to the third layer wiring ML3 or the fourth layer wiring ML4.
The portion immediately above the portion where the cell terminal CT is changed to the third layer wiring ML3 can be used as a placement area for the fourth layer wiring. Similarly, a portion having no cell terminal can be used as a passage area for the third layer wiring and the fourth layer wiring.

As described above, according to the second embodiment, it is possible to obtain the same effect as that obtained in the first embodiment.

However, according to the second embodiment, since the five-layer wiring is used, it is possible to reduce the area of the semiconductor chip 1 as compared with the case of the first embodiment.

Further, in any of the circuit blocks 2a to 2e, the wirings extending in parallel with the long wirings can be arranged in the lower layer separated by the two layers of the interlayer insulating films.
It is possible to reduce the wiring capacitance of the intra-block wiring as compared with the case of the first embodiment.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned Embodiments 1 and 2 and is within a range not departing from the gist thereof. It goes without saying that various changes can be made.

For example, in the second embodiment, the case where the number of wiring layers used for arranging long wirings and the number of wiring layers used for arranging short wirings are the same has been described, but the present invention is not limited to this. The number of wiring layers used for arranging long wirings is three, and the number of wiring layers used for arranging short wirings is two. May be larger than the number of wiring layers used for arranging short wirings. As a result, the size of each wiring region in the short direction can be reduced, so that the area of the semiconductor chip can be reduced.

Further, in the first and second embodiments,
The case where the present invention is applied to a semiconductor integrated circuit device having a hierarchical structure has been described, but the present invention is not limited to this, and is applicable to, for example, realizing a gate array having no hierarchical structure.

Further, in the first and second embodiments,
The case where the present invention is applied to the semiconductor integrated circuit device adopting the wire bonding method has been described. However, the present invention is not limited to this. For example, the semiconductor integrated circuit adopting a flip chip method using a bump electrode or a tape carrier bonding method. It is also applicable to devices.

In the first and second embodiments,
The case where the present invention is applied to the semiconductor integrated circuit device in which the MOS.FET is formed has been described, but the present invention is not limited to this. For example, the semiconductor integrated circuit device in which the bipolar transistor is formed or the bipolar transistor and the MOS.FET. It is also applicable to a semiconductor integrated circuit device in which and are formed on the same semiconductor substrate.

In the above description, the case where the invention made by the present inventor is mainly applied to a microprocessor which is a field of application which is the background of the invention has been described, but the invention is not limited thereto and various applications are possible. The present invention can be applied to a semiconductor integrated circuit device technology having a semiconductor memory circuit such as DRAM or SRAM or another logic circuit. The present invention can be applied to a semiconductor integrated circuit device having a multilayer wiring structure.

[0164]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, in the wiring arranging step of the semiconductor integrated circuit device having four or more wiring layers on the semiconductor substrate, the wiring length is relatively long. By preferentially arranging the wiring to be formed in an upper wiring layer of the wiring layer having a smaller wiring capacity, and arranging the wiring having a relatively shorter wiring length in the lower wiring layer of the wiring layer. It is possible to reduce the overall wiring capacity of the wirings forming the circuit device. As a result, the signal transmission speed of the wiring in the entire semiconductor integrated circuit device can be improved, so that the operating speed of the semiconductor integrated circuit device can be improved. Also,
It is possible to reduce the power consumption of the semiconductor integrated circuit device.

(2) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, the number of wiring layers used for arranging the wirings whose wiring length is relatively long is set to be relatively short. By increasing the number of wiring layers used for arranging the wirings, the size of the wiring region in the short direction can be reduced, so that the area of the semiconductor chip can be reduced.

(3) According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a wiring layer having a wiring extending in the same extension direction as a wiring arranged in an upper wiring layer and having a longer wiring length is formed in a wiring layer as low as possible. By arranging them in layers, the distance between the wiring layers can be increased, so that the coupling capacitance between them can be reduced. As a result, the signal transmission speed of the wiring in the entire semiconductor integrated circuit device can be improved, so that the operating speed of the semiconductor integrated circuit device can be improved. Further, it becomes possible to reduce the power consumption of the semiconductor integrated circuit device.

(4). According to the method for manufacturing a semiconductor integrated circuit device of the present invention, after forming the in-cell wiring and the cell terminal forming the cells of the plurality of circuit blocks by the first layer wiring, the cell terminal is In accordance with the formation conditions of each of the plurality of circuit blocks, by changing the wiring layer to a different wiring layer depending on the connection hole arranged immediately above or in the vicinity thereof, it is possible to make the cells common when designing the wiring layout. Therefore, even if the wiring layout is different for each circuit block,
It is possible to deal with it with one cell library. Therefore, it is possible to significantly reduce the design period of the semiconductor integrated circuit device.

(5). A method of manufacturing a semiconductor integrated circuit device according to the present invention comprises a semiconductor substrate having a plurality of circuit blocks and an external wiring region arranged around the circuit blocks, and four or more layers are formed on the semiconductor substrate. A method of manufacturing a semiconductor integrated circuit device having a wiring layer, wherein each of the circuit blocks 2a to 2e is determined for each of the plurality of circuit blocks by determining the extending direction of the wiring in each wiring layer according to the congestion state of the wiring. Since the area occupied by the semiconductor chip can be reduced, the area of the semiconductor chip can be reduced.

(6) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, among a plurality of circuit blocks, a predetermined wiring layer in a formation region of a predetermined circuit block is electrically connected between the plurality of circuit blocks. By using it as the arrangement area of the inter-block wiring that is connected to each other, it is not necessary to bypass the inter-block wiring, and the arrangement area of the detour wiring is not necessary. Therefore, the area of the semiconductor chip can be reduced accordingly. It will be possible. Further, in connecting the circuit blocks, the wiring length of the inter-block wiring can be shortened as compared with the case of connecting by bypassing a predetermined circuit block, thereby reducing the wiring capacitance and wiring resistance of the inter-block wiring. It becomes possible to do. Furthermore, since the number of connection holes can be reduced compared to a case where a predetermined circuit block is bypassed to connect the circuit blocks, it is possible to improve the reliability of the connection between the circuit blocks. Become.

[Brief description of the drawings]

FIG. 1 is an overall plan view of a semiconductor chip that constitutes a semiconductor integrated circuit device of the present invention.

FIG. 2 is an enlarged plan view of an essential part of a circuit block in the semiconductor integrated circuit device of FIG.

FIG. 3 is a plan view of a cell in the circuit block shown in FIG.

FIG. 4 is a plan view of a cell in the circuit block of FIG.

5 is an explanatory diagram for explaining the structure of cell terminals in the cells of FIGS. 3 and 4. FIG.

6 is an explanatory diagram for explaining the structure of cell terminals in the cells of FIGS. 3 and 4. FIG.

FIG. 7 is an explanatory diagram for explaining the structure of cell terminals in the cells of FIGS. 3 and 4;

8 is a cross-sectional view of essential parts of the semiconductor integrated circuit device of FIG.

9 is an explanatory diagram of a circuit block of the semiconductor integrated circuit device of FIG.

10 is an enlarged plan view of an essential part of the circuit block shown in FIG. 9.

11 is an explanatory diagram of a circuit block of the semiconductor integrated circuit device of FIG.

FIG. 12 is an explanatory diagram of a problem that the circuit block area increases.

13 is an enlarged plan view of an essential part of the circuit block shown in FIG.

14 is an enlarged plan view of a main part of the semiconductor integrated circuit device of FIG.

FIG. 15 is an explanatory diagram of characteristics of the semiconductor integrated circuit device of FIG. 1.

16 is an enlarged plan view of an essential part of the semiconductor integrated circuit device of FIG.

17 is an explanatory diagram of a wiring structure in an external wiring region of the semiconductor integrated circuit device of FIG.

FIG. 18 is an enlarged plan view of an essential part of a circuit block of a semiconductor integrated circuit device according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 semiconductor chip 2a to 2e circuit block 3, 3a to 3f external wiring region 4 cell column 4a cell 5 internal wiring region 6n n-channel type MOS / FET 6nL semiconductor region 6n1 low impurity semiconductor region 6n2 high impurity semiconductor region 6ni gate insulating film 6ng gate electrode 6g gate extraction electrode 6p p channel type MOS • FET 6pL semiconductor region 6p1 low impurity semiconductor region 6p2 high impurity semiconductor region 6pi gate insulating film 6pg gate electrode 7 field insulating film 8 cap insulating film 9 protective film 10 sidewall 11a Semiconductor regions 12a to 12d Interlayer insulating film 13 Surface protection film BP Bonding pad PW p well NW n well CT Cell terminal VIA connection hole VIA1 connection hole ML In-block wiring ML1 First layer wiring ML1 a Conductor film ML2 Second layer Wiring ML2 a Conductor film ML3 Third layer wiring ML3 a Conductor film ML4 Fourth layer wiring ML4 a Conductor film ML5 Fifth layer wiring MLB1 First layer wiring MLB2 Second layer wiring MLB3 Third layer wiring MLB4 Fourth layer wiring VDD Power supply Potential VSS Ground potential

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yujiro Miyairi 5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd.

Claims (20)

[Claims] 1. In a wiring arranging step of a semiconductor integrated circuit device having four or more wiring layers on a semiconductor substrate, a wiring having a relatively long wiring length is preferentially given to an upper wiring layer in the wiring layer. A method of manufacturing a semiconductor integrated circuit device, comprising: arranging and arranging a wiring having a relatively short wiring length in a lower wiring layer of the wiring layer. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the number of wiring layers used for arranging the wirings having the relatively long wiring length is set so that the wiring length is relatively short. The method for manufacturing a semiconductor integrated circuit device is characterized in that the number of wiring layers used for the arrangement is larger. 3. A method of manufacturing a semiconductor integrated circuit device comprising a plurality of circuit blocks on a semiconductor substrate and an external wiring region arranged around the circuit block, and having four or more wiring layers on the semiconductor substrate. (A) When arranging the intra-block wiring forming the plurality of circuit blocks, the wiring having a relatively long wiring length is preferentially arranged in an upper wiring layer in the wiring layer, and the wiring length is In the step of arranging relatively short wiring in a lower wiring layer of the wiring layer, and (b) arranging inter-block wiring for electrically connecting the plurality of circuit blocks, the wiring length is relatively long. A wiring that is relatively long is preferentially arranged in an upper wiring layer in the wiring layer, and a wiring whose wiring length is relatively short is arranged in a lower wiring layer in the wiring layer. Characteristic semiconductor Manufacturing method of integrated circuit device. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising: a wiring layer having a wiring extending in the same direction as a wiring arranged in the upper wiring layer and having a relatively long wiring length. A method for manufacturing a semiconductor integrated circuit device, wherein the wiring layer is arranged in a wiring layer as low as possible. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein after dividing the external wiring region into a plurality of regions,
A method of manufacturing a semiconductor integrated circuit device, characterized in that the extending direction of wiring in each wiring layer is determined according to the shape of each of the external wiring regions. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein in each of the external wiring regions, the wiring extending along the longitudinal direction is prioritized over the uppermost wiring layer in the wiring layer. A method for manufacturing a semiconductor integrated circuit device, which is characterized in that the semiconductor integrated circuit device is arranged in a pattern. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein long wirings are arranged in the same wiring layer in each of the external wiring areas, and short wirings are arranged in the same wiring layer in each of the external wiring areas. A method for manufacturing a semiconductor integrated circuit device, which comprises arranging wiring. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein the extending direction of the wiring in each wiring layer is determined for each of the plurality of circuit blocks. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein: (a) a step of forming an inner cell wiring and a cell terminal which form cells of the plurality of circuit blocks with a first layer wiring; b) a step of changing the cell terminal to a different wiring layer depending on a forming condition of each of the plurality of circuit blocks by a connection hole arranged immediately above or in the vicinity thereof; and (c) electrically connecting between the cell terminals. And a step of forming the plurality of circuit blocks by connecting to the semiconductor integrated circuit device. 10. The method for manufacturing a semiconductor integrated circuit device according to claim 3, wherein among the plurality of circuit blocks, a predetermined wiring layer in a formation region of a predetermined circuit block is used as an arrangement region of inter-block wiring. A method for manufacturing a semiconductor integrated circuit device, comprising: 11. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein: (a) a wiring layer having a wiring extending in the same extension direction as a wiring arranged in the upper wiring layer and having a relatively long wiring length. Is arranged in a wiring layer as low as possible in the wiring layer, and (b) after dividing the external wiring area into a plurality of wiring layers,
In the case where the extending direction of the wiring in each wiring layer is determined according to the shape of each of the external wiring areas, the wiring extending in the longitudinal direction of each of the external wiring areas is defined by the wiring layer. (C) In each of the external wiring regions, the number of wiring layers used for arranging the wirings extending along the longitudinal direction of the wiring layer is preferentially arranged in the uppermost wiring layer of A method of manufacturing a semiconductor integrated circuit device, characterized in that the number of wiring layers used for arranging wirings extending along the short direction is larger than that of wiring layers. 12. A semiconductor substrate having a plurality of circuit blocks,
A method of manufacturing a semiconductor integrated circuit device, comprising: an external wiring region arranged in the periphery of the semiconductor substrate; and a semiconductor integrated circuit device having four or more wiring layers on the semiconductor substrate.
A method of manufacturing a semiconductor integrated circuit device, comprising: determining a wiring extending direction in each wiring layer. 13. The method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein the wiring layer has four layers,
(A) In a predetermined circuit block of the plurality of circuit blocks, wirings extending in the same direction as the extending direction of the cell rows forming the circuit block are first layer wirings and fourth wirings.
A step of forming a wiring formed by layer wiring and extending in a direction intersecting the extending direction of the cell row by the second layer wiring and the third layer wiring; and (b) another circuit of the plurality of circuit blocks. In the block, the wirings extending in the same direction as the extending direction of the cell columns forming the circuit block are formed by the second layer wiring and the fourth layer wiring, and the wirings extending in the direction intersecting the extending direction of the cell columns are formed. A method of manufacturing a semiconductor integrated circuit device, comprising the step of forming a third layer wiring. 14. The method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein when the wiring layer has five layers,
(A) In a predetermined circuit block of the plurality of circuit blocks, wirings extending in the same direction as the extending direction of the cell columns forming the circuit block are second-layer wirings and fifth wirings.
A method of manufacturing a semiconductor integrated circuit device, comprising the step of forming a wiring formed by layer wiring and extending in a direction intersecting the extending direction of the cell row with a third layer wiring and a fourth layer wiring. 15. The method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein: (a) a step of forming an inner cell wiring and a cell terminal for forming cells of the plurality of circuit blocks with a first layer wiring; b) a step of changing the cell terminal to a different wiring layer depending on a forming condition of each of the plurality of circuit blocks by a connection hole arranged immediately above or in the vicinity thereof; and (c) electrically connecting between the cell terminals. And a step of forming the plurality of circuit blocks by connecting to the semiconductor integrated circuit device. 16. The method for manufacturing a semiconductor integrated circuit device according to claim 12, wherein among the plurality of circuit blocks,
A method of manufacturing a semiconductor integrated circuit device, wherein a predetermined wiring layer in a formation region of a predetermined circuit block is used as an arrangement region of inter-block wiring that electrically connects the plurality of circuit blocks. 17. A plurality of circuit blocks on a semiconductor substrate,
A method for manufacturing a semiconductor integrated circuit device, comprising: an external wiring region arranged in the periphery of the circuit board; and a method of manufacturing a semiconductor integrated circuit device having four or more wiring layers on the semiconductor substrate, the method comprising: A method of manufacturing a semiconductor integrated circuit device, wherein a predetermined wiring layer in the formation region is used as an arrangement region of inter-block wiring that electrically connects the plurality of circuit blocks. 18. A semiconductor integrated circuit device having four or more wiring layers on a semiconductor substrate, wherein wiring having a relatively long wiring length is arranged in an upper wiring layer of the wiring layer, A semiconductor integrated circuit device characterized in that wiring having a relatively short wiring length is arranged in a lower wiring layer. 19. A semiconductor substrate having a plurality of circuit blocks,
A semiconductor integrated circuit device having an external wiring region arranged in the periphery thereof and having four or more wiring layers on the semiconductor substrate, comprising: (a) intra-block wiring forming each of the plurality of circuit blocks. And a wiring having a relatively long wiring length arranged in an upper wiring layer in the wiring layer,
(B) In-block wiring forming each of the plurality of circuit blocks, the wiring having a relatively short wiring length arranged in a lower wiring layer of the wiring layer; and (c) the plurality of circuit blocks. An inter-block wiring for electrically connecting between the plurality of circuit blocks and a wiring having a relatively long wiring length arranged in an upper wiring layer in the wiring layer, and (d) electrically connecting between the plurality of circuit blocks. And a wiring having a relatively short wiring length arranged in a lower wiring layer in the wiring layer. 20. A plurality of circuit blocks on a semiconductor substrate,
A semiconductor integrated circuit device having an external wiring region arranged in the periphery thereof and having four or more wiring layers on the semiconductor substrate, wherein wiring within the circuit block is provided for each of the plurality of circuit blocks. A semiconductor integrated circuit device, wherein the extending direction of the wiring in each wiring layer is changed according to the congestion degree of the wiring.