JPH09172068A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce inter-writing parasitic capacitance by a method wherein an organic resinous film is formed on a face of a first insulation film coated selectively with wiring, an organic film is thinned to expose the wiring face, after a sparse second insulation film is deposited on the entire face, a dense third insulation film is deposited, a space is provided between wirings with respect to each other. SOLUTION: After transistors, etc., are formed on a substrate, a silicon oxide film 1 is formed, and after a contact hole is formed, an Al film wiring 2 of a first layer is formed. After a resist film 3 of an organic resinous film is formed, the resist film 3 is etched until the Al wiring 2 is exposed. Continuously, an organic SOG film 4 is formed, so-called ashing is performed by O2 plasma process, and the infer-wiring resist film 3 is removed to form a space 5. A dense silicon oxide system insulation film 6 low in a coefficient of contraction is formed. Carbon in the organic SOG film 4 is removed by the O2 plasma process to make a sparse film, and O2 plasma is invaded therethrough to perform ashing to the resist film 3, so that a space 5 can be formed and inter- wiring parasitic capacitance can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a space between wirings in the same layer.

[0002]

2. Description of the Related Art In recent years, in semiconductor devices, multilayer wiring and miniaturization have been advanced for higher performance. For a semiconductor device having a minimum processing dimension of 0.3 μm or less, an increase in parasitic capacitance of wiring is a serious problem for speeding up. There is a serious problem that the capacitance between wirings in the same layer increases with miniaturization.

In order to reduce the parasitic capacitance between the wirings, there is a space between the wirings as disclosed in, for example, JP-A-63-313896 and JP-A-7-45701. Semiconductor devices have been proposed.

First, with reference to FIG. 5 and FIG.
A conventional method for manufacturing a semiconductor device having a space between wirings (prior art 1) described in Japanese Patent Application Laid-Open No. 3-313896 will be described.

First, a silicon oxide film as an interlayer insulating film is formed on a silicon substrate 16, and a first-layer wiring support member 17 is patterned at a predetermined position using a usual lithography technique and etching technique (FIG. 5A). )reference). Next, as a first interlayer insulating film 18, a photosensitive polyimide organic insulating film is applied and prebaked, and then the first layer through hole 19 between wiring layers and the upper portion of the first layer wiring support member 17 are developed and removed, and then postbaked. (See FIG. 5B). Then, after forming a copper thin film on the entire surface of the first layer interlayer insulating film 18 by electroless copper plating, a first layer wiring 20 is formed by electrolytic copper plating using a photoresist as a mask (FIG. 5).
(C)). Similarly to the step of forming the first layer wiring support member 17, the second layer wiring support member 21 made of an inorganic insulating material is formed at a predetermined position and shape on the first layer wiring 20 (FIG. 5D). reference). 5B, a second-layer interlayer insulating film 22 is formed on the first-layer wiring 20, and the second-layer through-holes 23 and the upper part of the second-layer wiring supporting member 21 are removed by etching. FIG. 5E). Then, a second layer wiring 24 is formed on the second layer interlayer insulating film 22 (see FIG. 5F). By repeating these steps, the third layer wiring 2
7 to a fourth layer wiring 30 are formed (see FIG. 6G).
Finally, the interlayer insulating layers 18, 22, 26, and 29 are removed by a plasma etching method or a chemical etching method using an etchant such as hydrazine to form an air gap wiring using the air gap 31 (FIG. 6).
(H)).

Next, referring to FIG. 7, Japanese Patent Laid-Open No. 7-457.
A conventional method for manufacturing a semiconductor device having a space between wirings (Prior Art 2) described in Japanese Patent Application Publication No. 01-001,001 will be described.

First, a silicon oxide film 1 as an interlayer insulating film is formed on a silicon substrate (not shown), and a contact hole (not shown) is formed by using a usual lithography technique and etching technique. Then, as shown in FIG. 7A, a first-layer Al wiring 2 is formed by using a sputtering technique.

Next, a solid film such as an ice film 32 is formed while cooling the semiconductor substrate using, for example, a spin coating apparatus (see FIG. 7B). Next, until the Al wiring 2 of the first layer is exposed by the chemical mechanical polishing (CMP) method.
The solid film is polished (see FIG. 7C). Next, a sparse silicon oxide film 34 having a large film shrinkage at a low temperature is formed by using a cooling plasma CVD method.

Thereafter, the solid film between the wirings is heated to 100 to 300 ° C. and passed through a sparse silicon oxide insulating film 34.
Evaporate (see FIG. 7D).

Then, using a normal plasma CVD method, a dense silicon oxide insulating film 6 with less film shrinkage due to heat treatment is formed from the sparse silicon oxide insulating film 34. Next, an Al film is formed by a sputtering method, and a second-layer Al film wiring 7 is formed by using a normal photolithography technique and a plasma etching technique (see FIG. 7E).

As described above, the space 5 can be formed between the wirings.

[0012]

The conventional method for manufacturing a semiconductor device has the following problems.

First, in the case of the prior art 1 described in Japanese Patent Application Laid-Open No. 63-313896, although the space between the wirings is made of air and the capacity between the wirings can be reduced, there is only the wiring and a part of the wiring support material. The mechanical strength is weak, and the wires fall down in a later process, causing problems such as disconnection of the wires and generation of particles. Further, as shown in FIG. 6 (h), since the interlayer film is removed by a chemical etching method using an etching solution or a dry etching method, after forming the air gap, water or air is formed until the subsequent passivation film is formed. , The interlayer film of the silicon oxide-based insulating film below the wiring absorbs moisture, causing problems such as deterioration of the reliability of the wiring.
Further, as shown in FIGS. 5 and 6, there is also a problem that the number of steps increases and the process becomes complicated because an insulating wiring support is used.

In the case of the prior art 2 described in JP-A-7-45701, a sparse insulating film and a dense insulating film are provided between the first wiring layer and the second wiring layer. Because there is
It also has mechanical strength, and the exposure of the wiring layer directly to the air after forming the space does not degrade the reliability of the wiring. However, it is necessary to perform a low-temperature process such as using a cooled plasma CVD method, and there are problems that the apparatus becomes complicated, the processing capacity is small due to the decrease in the film formation rate, and the handling of the wafer is difficult, resulting in productivity. Has the drawback of being bad.

[0015]

A method of manufacturing a semiconductor device according to the present invention comprises a step of selectively covering the surface of a predetermined first insulating film of a semiconductor substrate to form a plurality of wirings in the same layer. Forming an organic resin film on the surface of the first insulating film selectively covered with the wiring, exposing the surface of the wiring by thinning the organic resin film, and sparse second insulating film A space is also provided between the wirings by a step of depositing the entire surface, a step of removing the organic resin film, and a step of depositing a dense third insulating film.

The semiconductor device manufacturing method of the present invention is
A step of selectively covering a surface of a predetermined first insulating film of a semiconductor substrate to form a plurality of wirings in the same layer; a step of forming a protective film that covers at least a surface and a side surface of the wiring; Forming an organic resin film on the surface of the first insulating film selectively covered with a film, exposing the surface of the wiring by thinning the organic resin film, and forming a sparse second insulating film. A space is also provided between the wirings by the step of depositing on the entire surface, the step of removing the organic resin film, and the step of depositing the dense third insulating film.

An organic SOG film is suitable as the second insulating film.

Further, it is preferable to perform the steps from the step of removing the organic resin film to the step of depositing the third insulating film in the same manufacturing apparatus.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A to 1E are step-by-step cross-sectional views for describing a first embodiment of the present invention along manufacturing steps.

First, as shown in FIG. 1A, by using a normal method, after forming various parts necessary for forming a semiconductor device, such as a transistor, on a silicon substrate (not shown), The silicon oxide film 1 (first
Of about 200 to 800 nm. Next, a contact hole (not shown) is formed using a normal photolithography technique or the like. Then, the first layer Al film wiring 2 is formed by using the sputtering technique.

Next, for example, using a spin coating apparatus, FIG.
As shown in (b), an organic resin film, for example, a resist film 3 of a novolak resin often used for a positive resist is formed in a thickness of about 0.5 to 2 μm. As the organic resin film, an isoprene rubber-based resist used for a negative resist may be used, or another organic resin film may be used. Then, using a normal parallel plate type RIE apparatus, the resist film 3 is etched back with a gas system of CF ₄ and O ₂ or Cl ₂ + O ₂ until the Al wiring 2 is exposed (see FIG. 1C). ).

Subsequently, a normal organic SOG film (second insulating film) 4 is formed to a thickness of 200 to 500 n using a spin coating apparatus.
m to form a film. Thereafter, if necessary, the solvent is evaporated by heating in the same manner as in the ordinary formation of an organic SOG film. The organic SOG film may be a commonly used organic SOG film.

Then, as shown in FIG. 1D, so-called ashing is performed by O ₂ plasma processing to remove the novolak resin resist film 3 between the wirings. At this time, by performing the O ₂ plasma treatment, carbon in the organic SOG film 4 is removed and the film is changed to a sparse film. As a result, the O ₂ plasma passes through the organic SOG film 4 and the resist film 3 can be removed. It is.

Then, for example, a dense silicon oxide-based insulating film 6 (third insulating film) having a small film shrinkage is formed to a thickness of 200 to 1000 nm as shown in FIG. As a film formation method, there is a plasma CVD method using silane and nitrous oxide or tetraethoxysilane and oxygen. The silicon oxide-based insulating film 6 formed in this manner is a dense film having a film quality with a shrinkage ratio of 3% or less when treated in a nitrogen atmosphere at 900 ° C. Next, the Al film was formed to a thickness of 0.
A 3 to 1 μm film is formed, and the second layer Al film wiring 7 is formed by using a normal photolithography technique and a dry etching technique.
To form

As described above, according to the present invention, the O ₂ plasma treatment removes carbon from the organic SOG film 4 to form a sparse film, and the O ₂ plasma penetrates through the sparse organic SOG film 4. The resist film 3 is ashed to form a space 5 between the wirings. Since there is no solid in the space, the relative dielectric constant is about 1, which is reduced to about 1/4 compared to about 4 of the silicon oxide based film.

Further, since the present invention does not use the wiring supporting material of the insulating film unlike the prior art 1, there is also an effect that the number of steps can be reduced such that the step of forming the wiring supporting material becomes unnecessary. Further, there is no need to use a low-temperature process unlike the prior art 2, and there is an effect that mass productivity is good.

As described above, the present invention can reduce the parasitic capacitance between wirings even if the wiring is multilayered, has sufficient mechanical strength, and can cope with fine wirings and multilayer wirings as compared with the prior art.

Next, a second embodiment will be described.
FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention. This embodiment has a structure in which the aluminum film wirings 2 and 7 are surrounded by aluminum nitrides 9a and 9b, respectively. By surrounding the Al film wiring with an aluminum nitride film (protective film), the resistance to electromigration and the like when a large current flows through the Al film wiring is increased, and the reliability of the wiring is increased by the first factor.
It is a further improvement over the embodiment of FIG.

In this embodiment, the first layer and the second layer A
After forming the l-film wirings 2 and 7, the Al film wirings 2 and 7 are subjected to plasma treatment of nitrogen or ammonia (so-called plasma nitriding).
7 is nitrided, and the aluminum nitride films 9a and 9b are
It is the same as the first embodiment except that it is formed to a thickness of 50 nm. The plasma processing conditions are, for example, 350-450 ° C. at 13.56 MHz. Further, using a lamp anneal or the like, in a nitrogen or ammonia atmosphere, 300 to 45
By heating to 0 ° C., aluminum nitride may be formed. Further, as the protective film, an aluminum oxide film may be formed by heating in an oxygen atmosphere instead of the above-described aluminum nitride film.

Next, a third embodiment will be described.
FIG. 3 is a sectional view of a semiconductor device according to a third embodiment of the present invention. This embodiment has a structure in which the periphery of the Al film wirings 2 and 7 is surrounded by silicon oxide based insulating films 10a and 10b (protective films), respectively. Plasma CVD using silane and nitrous oxide or tetraethoxysilane and oxygen
By forming the silicon oxide-based insulating films 10a and 10b by 50 to 200 nm each by the method, the reliability of the Al film wiring is improved. Since the space 5 between the wirings is filled with the silicon oxide insulating film, the effect of reducing the parasitic capacitance between the wirings is reduced. Depending on the semiconductor device, the second or third
It may be freely determined whether to use the embodiment.

The type of protective film surrounding the periphery of the Al film wiring may be changed for each layer, such as an aluminum nitride film for the first layer and a silicon oxide-based insulating film for the second layer.

Next, a semiconductor manufacturing apparatus for carrying out the present invention will be described with reference to the drawings. FIG. 4 is a schematic view of a semiconductor manufacturing apparatus used to carry out the present invention. This semiconductor manufacturing apparatus is, for example, according to the first embodiment,
The process from the O ₂ plasma process to the process of forming a dense insulating film can be performed in the same apparatus.

This apparatus comprises an interlock chamber 11 for loading and unloading wafers, an O ₂ plasma processing chamber 13, a CVD chamber 14 for forming a dense insulating film, a transfer chamber 12 having a transfer robot, and valves 15-1 to 15-. 4.

A method for practicing the present invention using the present apparatus will be described below. First, after forming an organic SOG film as a second insulating film, the wafer is put into the interlock chamber 11, and then into the O ₂ plasma processing chamber 13 via the transfer chamber 12. As described in the first embodiment, the resist film 3 of the organic resin film is removed through the organic SOG film 4 by performing O ₂ plasma processing. Next, the wafer is transferred to the CVD chamber 14 via the transfer chamber 12, and the dense silicon oxide insulating film 6 of the third insulating film is formed.

As described above, by performing a series of steps in the same manufacturing apparatus, after the resist is removed by the O ₂ plasma treatment, it is possible to prevent the air, moisture, and the like from adsorbing to the surface of the first Al film wiring 2. Thus, a highly reliable semiconductor device with good reproducibility can be realized.

As described above, the embodiment of the present invention has been described. As the wiring material, in addition to Al, Al-Cu-Si,
Needless to say, Al-Cu-based Al-based alloys,
Even if a metal such as o or Cu or a material such as silicide is used, the effect of the present invention does not change. Also, for example, Ti and T
The effect of the present invention does not change even in the case of a wiring composed of a plurality of wiring materials such as iN and Al.

In the embodiment, a silicon oxide-based insulating film has been described as a dense insulating film, but another insulating film such as a silicon nitride film or a silicon oxynitride film may be used.

Although the embodiment of the present invention has been described with the two-layer wiring structure, the present invention may be applied to a one-layer structure or a structure having two or more layers.

Further, in order to increase the mechanical strength of the multilayer wiring according to the present invention, a dummy wiring may be freely provided between wirings in the same layer.

[0040]

As described above, according to the present invention, by forming a space between wirings in the same layer next to each other, even in the case of multi-layered wiring, wiring collapse occurs due to weak mechanical strength conventionally observed. This has the effect that the problem can be solved.
In addition, there is no need to form an insulating wiring support member as in the related art, and the number of steps can be reduced. Further, unlike the conventional case, after the air gap is formed, the air gap is not exposed to the air or moisture, the problem such as disconnection of the wiring is eliminated, and the reliability of the multilayer wiring is also improved.

Further, the use of the organic resin film and the organic SOG film has a problem that the process margin for keeping the temperature at 0 ° C. or lower as in the prior art is small, and the price of the semiconductor device manufacturing equipment is high. Is also effective.

[Brief description of the drawings]

FIG. 1A is a diagram for explaining a first embodiment of the present invention.
It is process sectional drawing divided and shown to (e).

FIG. 2 is a cross-sectional view of a semiconductor device for describing a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor device for describing a third embodiment of the present invention.

FIG. 4 is a schematic diagram of an apparatus for manufacturing a semiconductor device for explaining a fourth embodiment of the present invention.

FIGS. 5A to 5F are cross-sectional process views illustrating the related art 1 in (a) to (f).

FIGS. 6A to 6H are cross-sectional process views separately illustrating FIGS.

FIGS. 7A to 7E are cross-sectional process views illustrating the related art 2 in (a) to (e).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon oxide film 2 Al film wiring 3 Resist film 4 Organic SOG film 4a Organic SOG film 4b Organic SOG film 5 Space 6 Dense silicon oxide film 7 Al film wiring 8 Passivation film 9a Aluminum nitride 9b Aluminum nitride 10a Silicon oxide insulating film 10b of silicon oxide-based insulating film 11 interlock chamber 12 transfer chamber 13 O ₂ plasma treatment chamber 14 CVD chamber 16 a silicon substrate 17 first layer wiring support member 18 the first layer the first layer interlayer insulating film 19 through hole 20 first Layer wiring 21 Second layer wiring supporting member 22 Second layer interlayer insulating film 23 Second layer through hole 24 Second layer wiring 25 Third layer wiring supporting member 26 Third layer insulating film 27 Third layer wiring 28 Fourth layer Wiring support member 29 Fourth layer interlayer insulating film 30 Fourth layer wiring 31 Air gap 32 Ice film 33 Water vapor 34 Sparse silicon oxide film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/90 P

Claims (4)

[Claims] 1. A step of selectively covering a surface of a predetermined first insulating film of a semiconductor substrate to form a plurality of wirings in the same layer, and a first insulating film selectively covered with the wirings. Forming an organic resin film on the surface, thinning the organic resin film to expose the surface of the wiring, depositing a sparse second insulating film on the entire surface, and removing the organic resin film And a step of depositing a dense third insulating film, a space is also provided between the wirings. 2. A step of selectively covering the surface of a predetermined first insulating film of a semiconductor substrate to form a plurality of wirings in the same layer, and a protective film which covers at least the surface and the side surface of the wiring. A step of forming an organic resin film on the surface of the first insulating film selectively covered with the protective film; a step of thinning the organic resin film to expose the surface of the wiring; The semiconductor device is characterized in that a space is also provided between the wirings by the step of depositing the second insulating film on the entire surface, the step of removing the organic resin film, and the step of depositing the dense third insulating film. Manufacturing method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is an organic SOG film. 4. The process of removing the organic resin film to the process of depositing the third insulating film are performed in the same manufacturing apparatus, according to any one of claims 1 to 3. A method for manufacturing a semiconductor device as described above.