JPH09167984A - Power line communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a communication system with high reliability at a low cost by providing a means protecting a means applying a digital signal to an AC power line against a damage so as to use the existing AC power line for the communication by the digital signal. SOLUTION: A signal from a peripheral unit 46 is given to a logic control circuit 44, in which the signal is formed into digital pule trains 82, 84 for a broad band, they are fed to tri-state buffers 86, 88, and they fed to a differential amplifier 90. The resulting AC signal from the differential amplifier 90 is fed to a filter 92, in which undesired frequency components are eliminated and the resulting signal is fed to a negative feedback power amplifier 98 via a gain amplifier 96 and the amplified signal is fed to a power line. After a time response of a feedback voltage 101 from the power line is adjusted in a signal decision means 114 by using a control signal 108 from a computer and the resulting signal is fed to resistors 30, 31 via a transmission voltage control circuit 112 to adjust the signal level to be a prescribed power level thereby protecting a digital signal application means. At a receiver side receives a signal at a secondary winding of a coupling transformer through a surge protector for the power line and conducts prescribed decoding processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a digital communication system, and more particularly to a power line for transmitting and receiving high speed information signals in binary form such as computer data to a noisy line medium such as alternating current (AC) power line. Regarding a communication device.

[0002]

Digital information, such as computer data, is known to be capable of being transmitted on current AC power lines. An important advantage of such data communication is recognizable and flexible enough to be interconnected with office electronic products, data terminals, remotely operated printers, personal computers, and the like. The formation of the data path is achieved simply by plugging the distribution terminal (socket) into the AC socket of the power line. Any type of device operated by the central computer can be connected to the central computer through a power cord already provided with the device. The central computer can be used to control various process equipment including heating, lighting and air conditioning.

The presently common setting in the majority of users requiring digital communication lines is the use of hard wires to interconnect various terminals. This hardwire is expensive, inflexible, and typically produces data rates higher than those required by the average user. The AC power line extends over most of the area where data communication is required, if not all, so high-reliability high-speed digital communication via this power line saves considerable cost and system flexibility. Will form with sex.

Broadly provided communication medium or AC in the frequency range of about 100 to 500 kilohertz (kHz).
Power lines usually exhibit unpredictable transmission characteristics such as extreme attenuation at specific frequencies, phase changes along paths, branches and breaks. Usually, three modes of noise are common: low voltage Gaussian noise, low voltage pulse interference and very high voltage spikes. In these modes, low voltage pulse interference tends to be the dominant source of data transmission error, that is, data communication can be reliably achieved even in the presence of Gaussian noise. With respect to high voltage spikes, it is less frequent and invariably induces data errors, and error detection / retransmission (ACK / NACK) is usually accepted as the best way to recover lost information. Furthermore, these characteristics change significantly as the load conditions of the power line, for example various other loads, with and without connection to the current supply line, change. Such loads include industrial machines, various electric motors of numerous appliances, heaters and chargers.

[0005]

Past proposals to solve these problems have included various single or multi-channel narrow bandwidth transmission techniques. However, this narrow bandwidth limits the data transmission capacity to be connected. Furthermore, AC
The noise-changing environment on the power line has significantly impaired the reliability of any damaged technology when a transmission channel of a certain width is disturbed or lost. For these and other reasons, AC power line communication has not been considered in the past as either fast or reliable.

Although multi-channel digital coding technology has shrewdly improved high reliability and high speed power line communication systems, the cost of the improvements has been bulky, resulting in complex and expensive signal processing equipment. Therefore, a solid position for power line data transmission could not be achieved, and it was far from practical use. For example, a data transmission that can tolerate a significant error is 10 kilobits per second (k
bps) Limited to the doctor's data transfer rate. Even in such an improved system, the reliability is almost doubtful, because some or a large number of predetermined narrow bandwidths are suddenly disabled without warning due to unexpected fluctuations in the power line transmission characteristics.

In recent years, data transmission on the power line is
It has become very difficult due to the distortion of the AC waveform.
With the widespread use of personal computers and remote printers, the FCC (Federal Communications Commission) has issued regulations that regulate digital radio waves radiated from computer equipment onto power lines. To meet this requirement, computer manufacturers must oblige to add high capacity filters with values on the order of 0.1 μF that appear as low impedance to the power line side. This affects the distortion encountered at wide bandwidths, while at the same time causing severe attenuation of the narrow bandwidth signal.

Many common forms of carrier signal modulation have attempted to interface with power line communication systems. In each of these schemes, digital information was modulated on a carrier, which was then fed to the AC power line. The receiver received the carrier and then demodulated the received signal to recover the digital data information. Two of the more common types are amplitude shift keying (ASK) and frequency shift keying (FSK).
It is. Both of these techniques have been considered as susceptible to electromagnetic interference (EMI) and radio frequency interference (RFI). Of course, the third principle modulation technique, Phase Shift Keying (PSK), is usually quite susceptible to the effects of noise interference, which results in a large variation of the carrier signal attenuation,
Considered inappropriate.

In view of the above-mentioned difficulties, the power line communication is based on LA
Pre-arranged data transmission where the natural extension of the N (Near Field Communication) system reaches each office in the building, each home in the vicinity or any place where AC power line or two other conductors are laid Despite acting as a medium, it was not considered as the main short-range communication network. LAN instead of this
Is an expensive hard-wired device that typically provides excess data transfer capacity than required by most users (nodes) in a communications network.

A main object of the present invention is to provide a power line communication system capable of transmitting almost error-free data at both high and low data transmission rates by using a supplied existence line such as an AC AC power line unevenly distributed for data transmission. Is to provide.
Another object of the present invention is to provide an inexpensive and highly reliable AC power line communication system capable of transmitting data at a higher speed than currently known systems.

It is an object of the present invention to eliminate the need for expensive, inflexible data communication line hardwires for other portable data processing devices. Another object is to provide a highly flexible power line communication link that requires minimal equipment with small volume that is portable and easy to reconfigure. It is an additional object of the present invention to provide a digital data transmission system with improved error detection / error correction capabilities to increase the data transmission rate.

Another further object is to provide a power line communication system that is fairly resistant to constantly changing power line data transmission characteristics, especially robustness under pulse noise conditions. Still another object of the present invention is a power line having sufficient robustness of an internal protocol capable of communicating between data transmission reliability and a large number of devices that participate in a short-range communication network, even while the other is talking. To provide a communication system.

[0013]

In accordance with the present invention, a novel circuit forms noisy power line data communications. The circuit includes a transmitter and a receiver capable of bidirectional communication with similar circuits located on the power line. Intelligent control of these transmission and reception characteristics has resulted in improved reception and transmission results under constant changes, adverse noise conditions, distortion and attenuation.

The data-modulated carrier is formed using a wide band technique that forms a waveform that has a power that is almost uniform over the bandwidth used during each period. Therefore, the signal frequency spectrum is much wider than the pulsed noise signal, and wide enough to effectively reduce the frequency dependent attenuation phenomenon, so that noise,
The sensitivity to distortion and damping is reduced.

The receiver includes means for receiving a noisy, distorted, modulated carrier signal carried on a power line signal, such as an AC line voltage of 60 Hz, and can of course be received from a non-powered power line. This power line signal, if present, is removed by the optimal filtering means, leaving only the noisy, distorted, modulated carrier signal. Selectively controlled low-pass and high-pass filters act on the modulated carrier signal in response to a control signal generated by a microcomputer means with predetermined specifications. Especially,
The filter may be controlled to search the filter array so that the distortion due to transmission over the AC line is equalized as much as possible.

This filtered carrier signal is
Means are provided for converting or demodulating into a digital signal or pulse train representing individual information bits. The resulting digital signal contains the desired "intelligence" to be recovered and, of course, is provided as a drive signal to control various adaptive circuit means, including the filters described above. The logic circuit examines the data pattern to be verified from the received digital signal and establishes a receiver synchronization that almost steps with the highest energy content part of each new information bit. This logic circuit is combined with a new adaptive filter control, signal correlation means, and of course, using a special error detection / correction means, such as a receiver / transmitter or a personal computer to which the device of the present invention is connected. May examine, track, verify and lock the transmission preamble of valid data which is further processed by the host device.

The transmitter of the present invention is arranged to generate a preferably modulated carrier signal which is coded with the information to be transmitted. The transmitted signal is a broadband signal with energy components that are almost spread across the useful frequency spectrum of the transmission medium. According to the intention of the invention,
The wideband transmitter is singly negatively feedback controlled to optimally control the transmitted signal strength in response to impedance changes on the transmission line.

According to another particularly advantageous intention of the invention, the microcomputer means select various network crossing modes including "master / slave", "token bus / token path" and other data transmission control arrangements. Are arranged so as to form a pattern. The present invention may be selectively operated with synchronous or asynchronous communication protocols over the RS-232-C standard for interfacing with host devices. These features form a PLC device useful for LAN applications, especially like the other features described below, and at low cost achieves speed, high reliability, flexibility and operability that the present invention has not yet achieved. it can.

[0019]

Other objects, features and advantages of the present invention described in the above items are explained below based on the embodiments with reference to the drawings. FIG. 1 shows a portion of a power line communication (PLC) circuit 10 that receives data signals directly over a power line 20 that supplies AC power to a peripheral unit 46, such as a remote printer, personal computer, or the like. The separated data line is removed from this circuit.
The circuit 10 may be selectively coupled to "hot wires" and neutral conductors, or ground and neutral conductors not shown. In one embodiment, one set of conductors of AC lines that can be connected has two available sets with good signal transmission characteristics at a given moment, such as low distortion and better signal-to-noise ratio per data carrier signal. Automatically selected depending on.

A line surge protector 22, such as a gas line surge voltage absorber, may be provided across the signal line. The hot and neutral selected conductors of this embodiment are connected to the primary winding of the coupling transformer 24 and the transformer is connected to the AC power line 2
The 60 Hz AC voltage formed by 0 is removed. The line signals VH and VL are derived from the terminals of the secondary winding of the coupling transformer 24, the impedance of these signals being described below in connection with the negative feedback control of the transmitter of the present invention.

Transient voltage suppressor 26 may be connected between each secondary terminal of the transformer and ground. A first-order low-pass filter (LPF) 28 and a first-order high-pass filter (HPF) 30 use known filters to pass the received signal. In accordance with the present invention, the modulated carrier used to carry the data is a wideband phase shift keying (PSK) signal with significant energy over a fairly useful frequency range of about 100-500 kHz. 10
Below 0 kHz, high power noise spikes interfere with this range, making reliable transmission difficult. 500k
Transmission at frequencies above Hz radiates energy into the AM frequency band of the broadcast band to which the FCC rules apply. Therefore, the low-pass and high-pass filters 28, 30 almost limit the signal frequency to the desired bandwidth. In environments other than AC power lines, it is understood that the useful frequency spectrum defined is different, in which case the wideband data signal contains energy over a particular bandwidth.

The filtered signal is the differential amplifier 3
2. Form a modulated carrier signal 33 that is fed to the input of, for example, a JFET (junction field effect transistor) input type op amp to reduce common mode noise. This signal 33
Contains considerable noise components, despite considerable distortion and signal filtering. Therefore, the second low pass and high pass filters 34, 38 are used to further filter and equalize the modulated carrier signal 33, allowing further signal processing including reliable demodulation. A highly advantageous method uses a selectively controllable equalization component value, a second order Salen key filter. A digital switch control 36 is formed in the low pass filter 34 to adaptively adjust both the cutoff frequency and the damping (factor). Similarly, the high pass filter 38
A digital control 40 is applied to adjust the cutoff frequency and damping as described later.
The second-order low-pass filter 34 and the second-order high-pass filter 38 are specifically adaptive filters configured as shown in FIG. 2, and the correlation processing based on the interval division shown in FIG. The adjustment as described above is performed in accordance with the filter controls 36 and 40 generated by performing as shown in FIG. Details of the configuration shown in FIG. 2 and the correlation processing shown in the transition diagram of FIG. 10 will be described later.

After adaptive equalization, the signal is converted into a suitable means (AD
The converter 42 converts the analog modulated carrier wave into a digital pulse signal 43. In one simple and inexpensive embodiment, the conversion is achieved by a two-stage clipped amplification of the carrier signal 41, after which the output of the second amplifier is applied to the fast comparator of the circuit with hysteresis. A digital pulse signal 43 is formed at the output of this comparator. In other embodiments, longer bit length AD converters are used to improve processing gain as is known.

The digital pulse 43 is applied to a logical control circuit 44 for synchronization, detection and demodulation (decoding),
As described below in connection with various intended logic processing circuits,
The data buried in the pulse train is being recovered. When this information is in the form of decoded data 45, this data 45 is passed by the PLC device of the present invention to the peripheral device 46 connected to the AC power line 20, and thus for both power supply and data communication. To achieve the intended purpose of using AC power line 20.

Referring briefly to FIG. 2, details of an advantageous selectively controllable equalization component value, second order Sallen-Key filter section are shown. Although various circuit element selection criteria are known, it is understood that the arrangement of Figure 2 allows for rapid adjustment of the filter section cutoff frequency and damping effect. Referring first to the low pass section, resistors R2 and R5 and resistors R3 and R6 are switches 54 and 5 which are each CMOS analog switches.
2 is selectively interrupted to change the cutoff frequency of the filter. Therefore, the six resistors R1
~ R6 forms four cutoff frequencies depending on the switch position. Capacitors C1 and C2 are typically connected. Amplifier 5 including JFET input OP amplifier
The negative feedback gain of 0 is controlled by the resistors R7 to R10.
Selective connection of both and either of resistors R8 and R9 by switches 56 and 58, respectively, controls the damping characteristics of the low pass. After that, output 3 of the OP amplifier
7 passes through capacitors C3 and C4 and is connected to the non-inverting input of the OP amplifier 60 in the high pass section.
For this non-inverting input, the resistor R1
1 to R16 are connected to form various high pass cutoff frequencies depending on the selective chopping of switches 66 and 68. The damping characteristic is also similar to that of the low pass section, through the switches 62 and 64 to the resistance R
The negative feedback gain formed by 17 to R20 is changed and connected. This description is for descriptive purposes only, and many different ways of equalizing and filtering severely distorted signals are possible. Of course, the number of possible filter setting combinations can be increased by increasing the intermittent resistance of the switch.

The adaptive control of the filter characteristics for scanning and maintaining the highly equalized ratio is arranged by the logic control circuit 44 as follows. Referring to FIG. 3, the coded control signals that switch the various resistors of FIG. 2 are shown and this format is understood to be descriptive only. In a control data byte 70 with 8 bits, each bit is a CMO
S analog switches 52, 54, 56, 58, 62, 6
It corresponds to one of 4, 66 and 68. If the bit is a logical 0 value, the corresponding switch is closed, and if the bit is a logical 1 value, the corresponding switch is open. Thus, when the PLC device fails to achieve synchronization, as indicated by the high bit error rate, or under other special conditions, and does not receive the preferably filtered data, the filter characteristics are logic 1 and 0. In the form of different consecutive bits (other bytes) of a new filter "command" or setting. In one array, each one of the 256 possible instructions is 5-10 ms until satisfactory data reception is achieved, as evidenced by synchronization locks, low bit errors or other performance criteria.
It is tried every predetermined period of time.

Returning to the transmit section of the present invention, leaving the logic and microprocessor circuitry off the present, reference is made to FIG.
Usually, transmitters are arranged to form a desired waveform from a digital pulse train formed by a logic processing circuit. This transmitter has the advantageous feature of being able to satisfactorily transmit a waveform with a power spread across a very wide frequency spectrum, for example 100-500 kHz, with little attenuation of the signal in any intermediate bandwidth. .
In addition, the transmitter is particularly adapted to apply the optimum voltage to the transmission medium without taking into account the dominant impedance of the medium, even if the impedance changes.

With reference to FIG. 4, a peripheral unit 46, such as a personal computer, may form the data signal 80 which is transmitted to the logic control circuit 44 for encoding.
In the described-only embodiment of the present invention, the logic control circuit 44 provides two digital pulse trains 82, 84 that roughly correspond to the positive and negative portions of the extreme transmitted waveform. This voltage waveform is provided to the terminals of the secondary winding of coupling transformer 24 for transmission over power line 20, as shown in FIG.

These digital pulse trains 82 and 84 are designed to create positive or negative or zero values at various points in the time domain.
It may be applied to control the operation of the state buffers 86,88. These tri-state buffers 86, 88 are arranged to operate in a very low impedance path through the two modes, bi-impedance block and ground. For example, when the digital signal 82 had a positive pulse value + V, the buffer 86 acted as a high impedance block, placing the voltage signal on conductor 91 related to the control voltage level of conductor 89 through resistor R30. The importance of the conductor 89 will be described later. Similarly,
The voltage signal may be placed from conductor 89 to conductor 93 across resistor R31 when digital pulse signal 84 maintains buffer 88 in a high impedance state. When the digital pulse signals 82, 84 are at zero value, each buffer 86, 88 causes the voltage on conductors 91 and 93 to drop to zero, much like a low impedance conducting state. Therefore, since conductors 91 and 93 are applied to the differential amplifier 90 including the known JFET input OP amplifier, the waveform is generated on the conductor 95 that changes between the same positive and negative voltage levels such as a sine wave at the zero voltage boundary. To be done.

The generated waveform according to the present invention has a wide band power which almost covers the entire useful spectrum. Therefore, it is necessary to generate a desired waveform for each single transport period. The information bit interval may actually be one or more transport period lengths, depending on the complexity of the synchronization circuit used. A small number of carrier periods per bit interval forms a wider signal bandwidth, with the widest bandwidth being obtained when one carrier period is used for each bit interval. However, the complexity of the synchronization is reduced substantially as long as two transport periods per bit are used than optimal.

A single period of carrier wave may be mapped to the frequency spectrum using known Fourier analysis techniques. However, in order to synchronize the actual waveforms, the carrier period can be divided into a plurality of discrete sub-intervals, for example 16 sub-intervals, each of which can be assumed to be an individual value such as 3 voltages. Further, an asymmetric waveform may exhibit better transmission characteristics than a symmetric waveform.

If 16 subspacings are used for the asymmetrical waveform and a pattern with 3 levels is desired, then
The power spectrum is a function of an 8-component vector with each component selected from a ternary set. This results in a variable number of possible waveforms with different power spectra to be investigated. Waveforms from these groups may be selected by a variety of specific criteria, including relevant FCC rules, power distribution across the intended bandwidth, and available circuit performance. One particular waveform found to be satisfactory is shown in Figure 9 (a) where the associated power spectrum is shown in Figure 9 (b).

Referring briefly to FIG. 9 (a), a useful waveform 200 is shown, which waveform has an asymmetric pattern of 16 pulses. However, this waveform 200 is one of the possible waveforms described above. Each pulse is (+) 202,
It has (-) 206 or zero 204. In a particular embodiment of the invention, each pulse interval is about 250 nanoseconds long. This waveform is generated by controlling tri-state buffers 86 and 88 as described above.

FIG. 9 (b) shows the power spectrum of the waveform 200 of FIG. 9 (a). The waveform 200 is mapped to the power / frequency spectrum using commonly known Fourier analysis. As shown, a significant amount of power spreads approximately uniformly above the useful frequency bandwidth, ie, 100 kHz and below the AM frequency band. In this power spectrum, the digital power transmitted in the AM band of the regulation is equal to or less than the regulation value of FCC. This waveform is understood to be a description only, but other waveforms may meet the desired usage criteria.

Prior to power amplification, the signal must be filtered to ensure that the power does not radiate outside the intended frequency bandwidth. Such extraneous transmissions may be carried out at a radiated transmission frequency, in violation of FCC regulations, requiring power to be consumed well elsewhere. Accordingly, the waveform of conductor 95 is applied to the first order low pass and high pass filters 92 and the filtered signal is applied to the next gain control 94. The particular technique used is customary. Of course, a second order low pass filter 96, such as a unity gain, Sallen-Key second order low pass filter, may be used. Then, the buffers 86, 88, the differential amplifier 90, the first-order low-pass filter and the high-pass filter 92 distribute the power of the "binary bit temporal input stream" almost uniformly over a predetermined frequency bandwidth. Means for converting into a transmission broadband signal having It should be noted that this conversion means may include the gain control 94 and the secondary low-pass filter 96 as necessary.

Finally, a power amplifier 98 is formed, which is a voltage controlled voltage source (VCVS), usually in the form of a negative feedback amplifier, with the advantageous properties of reduced noise, low frequency distortion and low phase distortion. Good. Such a power amplifier 9
8 constitutes "application means for applying the transmission wideband signal having the first power level to the line". FIG.
In a particular embodiment of the transmit power amplifier section, the output of the op amp 130 is a common emitter array of Darlington connected transistors 132, 1 as shown in FIG.
It is used to provide signals to 34 bases.
The negative feedback control of the amplifier is formed through the resistor R51 connected in parallel with the capacitor C10, and through the series resistor R50,
It is applied to the inverting input of the OP amplifier 130 of the JFET device. The output of this OP amplifier passes through the resistor R52, and the low speed rectifying diodes D3 to D such as IN4001.
6 points, in this case along 5 points.
These slow diodes D3 to D6 help eliminate crossover distortion, and the Darlington transistor 13
It allows less bias current for 2,134. These diode connections are biased by resistors R53 and R54.

The collector-base voltage drop of the transistor 132 is formed by directly applying the voltage -V3 of -15V to the collector. As shown, the collector is grounded via capacitor C12. Similarly, transistor 134 is powered by voltage + V3 applied directly to its collector, which also has capacitor C13.
Is grounded via.

The emitter voltages of the transistors 132 and 134 pass through resistors R55 and R56, respectively, and then to a resistor R58.
Is applied to the output VH of the amplifier. An analog switch (not shown) turns on when the transmitter does not operate.
It may be used to bypass the P-amplifier 130 and isolate the transistor base from the supply voltage +/- V3. In this setting, the line voltage appearing at VH goes through series resistors R57, 58 and then capacitor C14.
And C15 to be capacitively connected to the respective bases of the transistors 132 and 134. This arrangement advantageously floats the base voltage of the transistors at VH, ensuring that transistors 132 and 134 are off and quiet.

As already mentioned, the transistors are arranged to place the desired voltage level on the power line 20 despite the varying impedance of the line.
This will be explained with reference to the unexplained part of the description circuit shown in FIG. The modulation waveform at VH is applied to one terminal of the secondary winding of the coupling transformer 24. VL is connected to the other terminal of the secondary winding as shown in FIG. Of course, VL is a resistor R3
2 is connected in parallel to a capacitor C8.
The voltage 101 on the lower side of the resistor R32 is connected to the ground resistor R33. Therefore, the voltage drop 101 across resistor R33 is related to the voltage placed on the power line by the transmitter at VH. The sense voltage 101 is used to control the original signal level formed by the tri-state buffers 86 and 88, as a particular voltage range is optimally considered as the transmitted signal.

One arrangement that achieves this negative feedback control is shown in FIG. High-pass filter 1 where voltage 101 is first order
02 to remove the unwanted signal in the undesired frequency band. Means 114 are provided for determining a control signal related to the average transmit power. The control signal determining means 114 constitutes "a detecting means for detecting the impedance of the line". The detection means may include the primary high-pass filter 102, if necessary. For simplicity, half-wave rectifier 1
04 is used to remove the negative signal portion which acts to ignore the sense power altogether. Therefore, it is understood that the detection signal is related to half of the total transmission power. This rectified signal has a time constant circuit 10 with a microcomputer control 108 that adjusts the time response of the negative feedback loop, which response is fast at the beginning of the transmission and slows down as the transmission continues.
6 is applied. In this way, a configuration is realized in which "the adjusting means responds to the time constant for controlling the adjusting speed of the applying means by the adjusting means". This prevents operating the amplifier at an undesirable level every extended period. The average power level is then formed in the first order low pass filter 110 using known filters. This sensed average power is measured by resistors R30 and R3.
1 is applied to a transmission voltage control circuit 112 which forms an unamplified signal voltage level on conductors 91 and 93 respectively. The transmission voltage control circuit 112 constitutes "adjusting means for adjusting the first power level to the second power level in response to the detecting means to protect the applying means from damage".

The transmit voltage control circuit 112 can be any array in which a power output is formed as a function of voltage input.
One such arrangement is shown in FIG. 6 for descriptive purposes only, and the curve 126 of the output voltage V _out of the control circuit 112 is a function of the average transmit voltage. For average power above a certain level 132, the output voltage is held at the first level V _min .
For some other sensed average power below level 130,
The output voltage is V _max . Two levels 130 and 13
In the range between the two, the output voltage decreases linearly from V _max to V _min . Such a function is formed by the control circuit 112 shown in FIG. JFET input OP amplifier 12
Negative feedback amplifier including resistors 0 and 122 and resistors R40 to R44
Are usually connected in series, and the output of the first OP amplifier 120 is applied to the inverting input of the second OP amplifier 122. At the point between the OP amplifiers 120 and 122, the voltage is clipped by the switching diodes D1 and D2. That is, one end of the diode D1 is grounded and one end of the other diode D2 is connected to the voltage V1. For convenience, this voltage V1 is applied to the first O through the resistor R40.
It may be equal to the voltage applied to the inverting input of P-amp 120. The voltage V1 is 3.3 volts, for example. Second O
For the non-inverting input of P-amp 122, equal to V _min ,
An applied voltage V2 of, for example, 2.76 volts is applied. Therefore, V _out increases as the inverting input voltage of op amp 122 transitions from zero to negative. In this way, the transmit power is negatively feedback controlled in response to changes in the sense voltage 119.

According to another intention of this control, C8, R3
The component values of 3 and R58 are specifically chosen to allow favorable transmission operation in series with the inductance of the peripheral unit's line cord when the transmission medium impedance is low enough to approximate a short circuit. . Of course, the impedance may be a capacitive, resistive, inductive or a combination of these loads. The lowest impedances encountered are resistances in the range of 1-2 ohms, capacities of about 0.2 microfarads (capacities on the line side due to the FCC demand filter of personal computers) and a rough 1
It is estimated to be due to an inductive load of ~ 2 microHenry.

The following is a list of component values for one embodiment of the invention described above, where the unit of resistance is ohms and capacitance is picofarad unless otherwise noted. Resistance / Capacity R1, R4 1.10k C1 720 R2, R3, R5, R6 5.76k C2 180 R7, R8, R9, R10 5.76k C3, C4 330 R11, R13 2.43k C6 180 R12 3. 74k C8 0.5μF R14, R16 9.76k C10 100 R15 15.0k C12, C13 10μF R17, R18 9.76k C14, C15 10nF R19, R20 9.76k R30, R31 887 R32 10 R33 2.7 R40 34. 8k R41 40.2k R42 2k R43 52.3k R44 34.8k R50 150 R52 620 R53, R54 15.0k R55, R56 1.2 R57 2k R58 2.7

In order to preferably receive and demodulate data communications, the receiving section examines the phase of the carrier signal,
The synchronization with this phase must be locked. Means are provided for comparing the received signal with a known predetermined signal to identify information bits as compared to noise. Normal,
The received signal is competitively compared with a known reference signal until some level of correlation is found to exist between the two patterns. It is noted that between all transmitters and receivers, transmission and reception at a fairly similar rate must be maintained in order to preferably check the correlation. In one embodiment of the invention, a quartz oscillator is formed in each circuit as a pulse time reference. Quartz with an accuracy of 100 ppm can be easily used, for example 4.3008 mega H
The use of a crystal with a frequency of z completely eliminates the previous need to track the data signal frequency.

The receiver may be idle when not transmitting or receiving data. However, the receiver monitors the signal coming down the power line when the data transmission is initialized. A special sequence of information bits may be formed so that the signal can be captured and verified at the receiver. In the phase shift keyed carrier, logic 1 and logic 0 are equal, but the waveform is inverted. Thus, a particular column is partially identified by suddenly changing the sign of a sufficiently high correlation coefficient.

A survey / verification scheme is described in connection with FIGS. Referring briefly to FIG. 8, details of the survey scheme are described. In the embodiment of the invention, the data bit period 402 equals two continuous carrier periods 404, shown here as a completely undistorted sine wave. It can be seen that the actual waveform is highly distorted, with the highest energy portion clearly being the indicated waveform segment. It can be seen that if the transport period 404 is divided into 16 intervals, an 8-interval segment 408 can be created over the waveform interval with the highest energy content. This portion of the signal is a rough approximation of the stepped waveform 410 over an 8-interval section, which is used as the basis for correlation according to the present invention. The result of the 8-interval correlation is -8 to +8.
, The latter shows a perfect correlation, and the former shows a perfect but inverted waveform.

Referring to FIG. 10, a transition diagram of a power line communication synchronization scheme is shown. This transition diagram may be implemented in logic circuits, including classical state machines, using known techniques. When the signal appears on the transmission medium, the signal is correlated with a known reference signal interval. In this embodiment, the user's data message is preceded by a bit sequence, eg 00000001, then 0000000 possible.
A signature byte that is uncorrelated with either 1 or 11111110 follows.

Correlation counts are obtained in initialization state 301.
If a perfect correlation (C = + 8) is found, then 00
It is possible to set the start of a sequence of 00000 and move control to the next state 303 to begin the process of verification. A new correlation count is obtained at a time-shifted point from the previous correlation count to check the next expected signal for the presence of the reference interval. This shift corresponds to skipping an eight-interval segment of the waveform that would be expected to correlate with the opposite sign. If no full correlation is found (C less than +8), another count is performed at state 301. According to the invention, this step is monitored by a microcomputer. If multiple correlation counts are performed without success, the system issues a new instruction byte 70 to adaptively change the receive filter, as described with reference to FIGS. This normal pattern is described later.

In the second stage 303, a sufficient correlation count transfers control to the next state 305. From this point, the correlation sufficiency may represent a count equal to or greater than +6. It is clear that this is just a particular embodiment of the synchronization scheme and that many other methods are possible. If the count in state 303 is insufficient (C is less than +6 or-sign), control is in the first step 301.
Return to The preferred code must be determined beforehand at the start of the process. This pattern similarly continues through the next two states 305, 307 until state 309 is reached. Achieving state 309 asserts that 4 consecutive correlations have occurred, and at this point is proof that 00000001 consecutives have actually been received.

State 309 is maintained as long as continuous correlation is obtained. The system is waiting for a sufficiently high count that the time state 311 has reached the opposite sign. If an insufficient count is obtained for this waiting period (C is less than +6), another intermediate waiting state 315 is achieved. At the time of the next continuous correlation count, the control is in the standby state 3
091, or two bad counts indicating that the bit sequence was in fact buried in noise were subsequently generated conservatively, leading to a less reliable wait state 317. From state 317 or 315, a good level raises the confidence level to return to the wait state 309. State 317
Insufficient counting (C is less than +6) starts operation 301
To start again. Three consecutive bad counts strongly indicate noise reception.

From states 309, 315 and 317, sufficiently high correlation counts with opposite signs are obtained in states 311 and 31.
Increase to any of the three. If the next successive correlation count is insufficient in either of these states, the operation returns to level 305 or 303, respectively, and attempts to retake the special bit sequence. If the count is state 3
If 11 or 313 o'clock was enough (repetition of C equal to or greater than 4 and opposite sign), then a very high confidence state 321 is reached. At this point, the final correlation count is
It is processed over 6 direct continuous intervals, i.e. 1 total transport period. If 4-bit counting is used, the value is +8
It is clear that there is more, not less than -8.
For such a port, the actual −10 can be read as −8 due to the bit limit of the up / down counter, so a better overall correlation count than −8, covering 3/4 of the possibilities, can be used for logical control. Let the microcomputer start discounting. Count is -8 (any of -8 to -16)
In one rare example, the entire process is aborted and then restarted from state 301.

It is noted that the receiver synchronization may shift almost simultaneously from the actual start time of the transmission bit interval. This is possible by correctly selecting both the transmission waveform and the demodulation reference waveform. This contributes to the important advantage that the PLC system according to the invention is continuously synchronized in the presence of miscellaneous line characteristics.

When it is certain that the data bits have been received, the network access control is moved to the microcomputer as described above. The particular data concatenation protocols used in short-range networks (LANs) are known, but these protocols are usually not robust enough to allow accurate communication of data over highly error-prone media. For example, data may be transmitted in packets, each packet containing a large number of bytes. Error checking such as CRC may be added at the end of the packet.
However, the potential for errors during transmission over the power line is so high that the value of such known error checking methods decreases. Therefore, it is advantageous to reassemble the packet into smaller frames, as the probability of error-like frame reception is lower than error-like byte reception in the packet.

Another advantage of using smaller frames is that
Together with error detection techniques, it has become possible to use various error correction techniques to form extremely reliable data connections. In particular, it is preferable to form a correction for all single-bit errors in the transmitted bytes, of course two-bit burst errors. An error correction code / error detection code that almost achieves the final purpose may be formed.

As an embodiment, a hypothetical transmission of bytes with 8 bits is preferred. To form the error correction,
The 8/4 code encodes half a byte at a time, mapping 4 bits into 16 possible 8-bit codewords. This codeword is transmitted and then 256 bytes long (2 ⁸ )
It is decoded by looking at the decoding table of. Any code word that contains an error has 16 "truth =
It is assumed to have its origin as one of the "1" codewords. That is, some correspondences are 16 true code words ~ 240
It may be predetermined with a number of spurious code words.

Very serious errors, such that the disturbed codeword bytes are similar to other true codewords during reception and demodulation, may be handled with the addition of error detection codes. The original data byte is mapped to the corresponding edc byte of 8 bits. The edc byte is then divided and each 4 bits are mapped into a codeword byte using an error detection table and transmitted. Therefore, the particular embodiment described is quite inefficient, with each data byte being 4 bytes.
Transmission error correction code bytes, ie for the first 4 bits of the data byte, for the last 4 bits of the data byte, e
It is clear that for the first 4 bits of the dc byte, the last 4 bits of the edc byte are required. When the edc bytes are reconstructed, if everything is transmitted successfully, it is mapped back to something that is the original data byte. If not, a serious error is made,
Retransmission is required. These are only some of the many features that PLC systems deal with in porting data connection protocols.

[0057]

As described above, the new power line communication system is formed with a higher data transmission rate and much improved reliability than known PLC systems. As will be apparent to those skilled in the art, the vast majority of variations,
Improvements and additions do not depart from the scope or spirit of the present invention,
Detailed descriptions can be made to the disclosed detailed embodiments only.
For example, as digital technology advances, much of the filtering and equalization can be economically formed with purely digital devices instead of the familiar resistor-capacitor network described. Of course,
Corrugation can be economically accomplished with digital devices in several respects.

However, at the present time, the disclosed invention has a price difference of one digit or more than other known systems, and can be manufactured at low cost at low cost and can be put on the market. The present invention is particularly suitable for communication / control master / slave, distributed master or token bus / token path modes for internal protocols capable of forming fast, reliable communication line access, short-range forming control over transmission media. It is most suitable for use in a communication network (LAN).

[Brief description of the drawings]

FIG. 1 is a partial block diagram of a circuit for receiving a broadband data signal.

FIG. 2 is a schematic circuit diagram of an adaptive filter circuit in which a filter is controlled in response to a change in state of a power line.

FIG. 3 is a diagram showing a representative code of a filter control signal.

FIG. 4 is a schematic circuit diagram for transmitting a modulated, wideband carrier signal having coded digital data whose signal power is adaptively controlled in response to impedance changes of the transmission medium.

5 is a schematic diagram of a transmission voltage control block of FIG.

6 is a schematic diagram of a voltage supply mechanism formed by the transmission voltage control circuit of FIG.

FIG. 7 is a schematic diagram of the transmitter power amplification block of FIG.

FIG. 8 is a time diagram of data bits according to the invention of a detailed view of the particular waveform characteristics used in the synchronization scheme.

FIG. 9 is a useful waveform diagram (a) of a broadband power line communication signal and a power spectrum diagram (b) of the waveform of the waveform diagram.
It is.

FIG. 10 is a state diagram showing an investigation method and a verification method of data signal reception.

[Explanation of symbols]

 86, 88 buffer 90 differential amplifier 92 first order low pass and high pass filter 94 gain control 96 second order low pass filter 98 power amplifier 102 first order high pass filter 106 time constant circuit 108 microcomputer control 112 transmission voltage control circuit 114 control signal decision means

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor David El Prop Canada, M6B, 1K2, ONTARIO, Toronto, Riedel Avenue, 377

Claims (2)

[Claims] 1. A data communication system for communicating a data signal between a first position and a second position over a line having at least a first conductor and a second conductor. Converting means for converting a series of input streams into a transmit wideband signal having power distributed almost uniformly over a predetermined frequency bandwidth, and applying the transmit wideband signal having a first power level to the line Applying means for detecting the impedance of the line, and a second means for responsive to the detecting means for detecting the impedance of the line.
A data communication system comprising: adjusting means for adjusting the power level to protect the applying means from damage. 2. The data communication system according to claim 1, wherein the adjusting means responds to a time constant for controlling the adjusting speed of the applying means by the adjusting means.