JPH0916646A - Design rule check method and system - Google Patents

Abstract

(57) [Abstract] [Purpose] To significantly reduce the pseudo error generated by checking the design rule in the semiconductor integrated circuit device. [Structure] The pattern data of the basic cell is inputted from the figure input section 2, the design rule is checked by the figure calculation section 3, and output to the error figure output section 4, and the circuit figure is displayed on the display section 5 for designing. The person extracts the pseudo error by the pseudo error selecting unit 6 and stores it in the extracted pseudo error storage unit. The pattern data of the entire semiconductor chip is input from the graphic input unit 2, the design rule is checked by the graphic calculation unit 3, and the pseudo error data stored in the pseudo error storage unit 7 is converted by the SUB calculation unit 8 into S
The UB calculation is performed, the pseudo error stored in the pseudo error storage unit 7 is removed, and the circuit graphic is displayed on the display unit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a design rule checking method and system, and more particularly to a technique effective when applied to reducing false errors in design rule checking.

[0002]

2. Description of the Related Art According to a study made by the present inventor, for example, in pattern design in a semiconductor integrated circuit device, pattern widths and intervals of layers and interlayer patterns due to the limit of fine processing in the manufacturing process and the accuracy limit of mask alignment. There is a design rule that defines the minimum value of the interval, etc., and whether the design rule is satisfied is checked by a design rule check (hereinafter referred to as DRC) system.

Further, the DRC system can check various kinds of design rules and prepares a basic figure calculation function and a dimension check function so as to cope with changes in the design rule, and checks them by combining them. The method is adopted.

An example of a detailed description of this type of DRC system is Nikkan Kogyo Shimbun, Showa 62.
Published on September 29, 2013 "CMOS Device Handbook"
CMOS Device Handbook Editorial Committee (ed.), P
171 to P183, and this document describes a layout design verification technique in a semiconductor integrated circuit device.

[0005]

However, the present inventor has found that the design rule check by the DRC system as described above has the following problems.

In other words, due to the lack of capability of the DRC system, a portion that is not actually an error, for example, when the dimensions of the design rule are different between the contacts at the same potential and different potentials, or when the minimum dimension differs depending on the type of signal line Since it can be checked only uniformly, it is treated as an error, so-called pseudo error occurs.

The detection of this pseudo error must be performed manually by visual inspection, and with the recent increase in the integration density of semiconductor integrated circuit devices, the detection of pseudo error becomes large and the number of man-hours is greatly increased. I have a problem to do.

It is an object of the present invention to provide a DRC system capable of significantly reducing the pseudo error generated by checking the design rule in a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the design rule checking method of the present invention includes a step of checking the design rule of the first layout design data which is the layout design data in each basic cell which is a unit of pattern data, and the design rule is checked. A step of extracting a first error which is an arbitrary error in the first layout design data, a step of storing the data of the extracted first error, and a second step of a layout design data of the entire semiconductor chip. The process of checking the design rule in the layout design data, the stored first error and second
Logical operation is performed on the second error which is an error of the check result of the design rule in the layout design data of
The method includes a step of outputting a third error from which the first error has been removed, and a step of displaying a circuit graphic including the third error.

In the design rule check method of the present invention, the logical operation is an exclusive OR or subtraction (hereinafter referred to as SUB operation).

Furthermore, the design rule check method of the present invention is the first layout design data extracted from the first layout design data.
The error of is a pseudo error.

Further, the design rule check system of the present invention is inputted with the first pattern data which is the pattern data of the basic cell which is a unit of the pattern data and the second pattern data which is the layout design data of the entire semiconductor chip. Graphic input means, a graphic calculation means for calculating the first pattern data and the second pattern data inputted from the graphic input means, and an arbitrary pattern in the first pattern data processed by the graphic calculation means. Error selecting means for extracting the first error which is an error, storing means for storing the first error data extracted by the error selecting means, and first error data and a graphic stored in the storing means Logic is obtained by comparing with a second error which is an error in the second pattern data processed by the arithmetic means. And a graphic operation means for performing arithmetic operation and outputting a third error after removing the first error, and a circuit graphic and graphic operation composed of second pattern data including the third error logically operated by the graphic operation means. And a display unit for displaying a circuit graphic in the second pattern data processed by the unit.

[0015]

According to the above-described design rule checking technique of the present invention, the first pattern data which is the pattern data of the basic cell and the second pattern data which is the layout design data of the entire semiconductor chip, inputted from the figure input means. Among them, the first pattern data is calculated by the graphic calculation means, the design rule is checked,
From there, the error selecting means extracts the first error, which is an arbitrary error, stores the data of the first error in the storing means, and the graphic calculating means checks the design rule in the second pattern data. The graphic operation means compares the data of the first error stored in the storage means with the second error which is an error in the second pattern data processed by the graphic operation means, and performs an exclusive OR or SUB operation. By performing a logical operation according to the above, a third error obtained by removing the first error is output, and the display means can display the circuit figure composed of the second pattern data including the third error. When checking the design rule of the second pattern data, which is the layout design data of the entire semiconductor chip, a simple circuit configuration can be used in a short time. It is possible to display only circuit shape removing the principal any errors.

Further, according to the design rule check technique of the present invention described above, the first error extracted from the first layout design data is treated as a pseudo error to check the design rule of the second pattern data. The work of detecting a pseudo error in is significantly reduced, and the work man-hour and time can be significantly reduced.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of a main part of a DRC system according to an embodiment of the present invention, FIG. 2 is a flow chart of a DRC system according to an embodiment of the present invention, and FIG. 3 is a view of an embodiment of the present invention. It is a schematic diagram which shows the processing flow of the pattern data in a DRC system.

In the first embodiment, the DRC system 1 for checking the design rule in the mask pattern data in the semiconductor integrated circuit device uses the pattern data (first pattern data) of the basic cell which is a unit of pattern data forming the chip pattern. ) And pattern data (second pattern data), which is layout design data for the entire semiconductor chip or each functional block, and the like are provided.

Further, the DRC system 1 is provided with a figure calculation section (figure calculation means) 3 for calculating the pattern data input from the figure input section 2, and in the subsequent stage of this figure calculation section 3, It is connected to the error graphic output unit 4 that outputs an error (second error) as a result of checking the design rule.

Further, the DRC system 1 is, for example,
A display unit (display means) 5 such as a printer or a monitor is provided, and the error graphic output from the error graphic output unit 4 and the pattern data output from the graphic input unit 2 are displayed.

Further, the DRC system 1 has a pseudo error selecting section (error selecting means) 6 for selecting and removing only a pseudo error (first error) from the pattern data output from the error graphic output section 4. A pseudo error storage unit (storage means) 7 for storing the data of the pseudo error selected by the pseudo error selection unit 6 is provided at the subsequent stage.

Further, the DRC system 1 is provided with a SUB calculation unit (graphic calculation unit) 8 and a pseudo error storage unit 7
SUB operation is performed between the data stored in the memory and the error in the pattern data of the entire semiconductor chip output from the error graphic output unit 4.

The SUB calculation unit 8 is also connected to the display unit 5, and the error graphic obtained by the SUB calculation is displayed.

Next, the operation of this embodiment will be described with reference to FIG.

First, the pattern data of the basic cell is input from the figure input section 2, the figure operation section 3 performs an operation on the pattern data, that is, the design rule is checked, and is output to the error figure output section 4 (step 10).
1).

Then, the error graphic output unit 4 has a display unit 5
The pattern data of the circuit graphic displayed in is displayed, the circuit graphic is displayed on the display unit 5, and the designer extracts the pseudo error based on the circuit graphic displayed on the display unit 5 by the pseudo error selection unit 6. Is performed (step 102).

Next, the data of the extracted pseudo error is
It is stored in the pseudo error storage unit (step 103). Then, when the extraction of the pseudo error in all the basic cells is completed (step S104), the pattern data of the entire semiconductor chip is input again from the figure input section 2 and the figure calculation section 3 checks the design rule (step S105). ).

The error in the pattern data of the entire semiconductor chip calculated by the figure calculation unit 3 and the data stored in the pseudo error storage unit 7 are SUB.
It is output to the arithmetic unit 8 and the SUB arithmetic unit 8 outputs SU.
The B operation, that is, only the pseudo error stored in the pseudo error storage unit 7 is removed (step S106).

The error (third error) from which only the pseudo error is removed is displayed on the display unit 5 as an error graphic.

The flow of these processes will be described with reference to FIG. 3. Of the basic cell pattern data input to the file f1 and the pattern data which is the layout design data of the entire semiconductor chip, the basic cells s1 to sn are respectively. The pseudo errors E1 to En in
The pseudo-errors E1 to En are stored in the error graphic database D.
B.

Further, the design rule of the data CD which is the pattern data of the entire semiconductor chip stored in the file f1 is checked, and the data DD which is the check result of the design rule of the data CD and the error graphic database DB are stored. Pseudo error E
By performing a SUB operation on 1 to En, the pseudo error E
The circuit figure PF in the pattern data of the entire semiconductor chip from which only 1 to En are removed is output.

As a result, in this embodiment, when the design rule is checked in the pattern data of the entire semiconductor chip, the graphic in which the pseudo error in each basic cell has already been removed is displayed by the SUB operation unit 8. It is possible to reduce the number of man-hours required for visually detecting the pseudo error, and to significantly improve the design rule check efficiency.

Further, in this embodiment, the SUB calculator 8
In the same manner, the SUB calculation is performed, but even if a calculation unit (not shown) that performs the EOR calculation is used instead of the SUB calculation unit 8, only the pseudo error can be satisfactorily removed.

As mentioned above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof. Needless to say.

For example, in the above-described embodiment, only the pseudo error is extracted and removed by the pseudo error selecting section, but the selection by the pseudo error selecting section is arbitrarily made by the designer, and all the pseudo errors are eliminated. Other than extraction, any pseudo error may not be extracted, or any true error that is not a pseudo error may be extracted and removed at the same time.

Accordingly, it is possible to make it easier to confirm the circuit graphic displayed on the display unit by displaying only the error in the wiring between the cells without displaying the error in each cell.

[0038]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, it is possible to display the circuit figure from which any error in the first pattern data has been removed, so that the second pattern data can be more easily confirmed.

(2) Further, in the present invention, the pseudo error in the first pattern data is removed and the graphic is displayed, so that the pseudo error can be detected by visually observing the circuit graphic in which the second design rule is checked. The work man-hours involved can be reduced.

(3) Further, in the present embodiment, the work efficiency in the design rule check can be greatly improved by the above (1) and (2).

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part of a DRC system according to an exemplary embodiment of the present invention.

FIG. 2 is a flowchart diagram of a DRC system according to an embodiment of the present invention.

FIG. 3 is a schematic diagram showing a processing flow of pattern data in a DRC system according to an embodiment of the present invention.

[Explanation of symbols]

 1 Design Rule Check System (DRC) 2 Graphic Input Unit (Graphic Input Means) 3 Graphic Calculation Unit (Graphic Calculation Means) 4 Error Graphic Output Unit 5 Display Unit (Display Means) 6 Pseudo Error Selection Unit (Error Selection Means) 7 Pseudo Error storage unit (storage unit) 8 SUB calculation unit (graphic calculation unit) f1 file s1 to sn basic cells E1 to En pseudo error DB error graphic database CD data DD data PF circuit graphic

Claims (4)

[Claims] 1. A design rule check method for checking a design rule in a layout design of a semiconductor integrated circuit device, the design of first layout design data which is layout design data in each basic cell as a unit of pattern data. Checking a rule, extracting a first error that is an arbitrary error in the first layout design data for which a design rule is checked, and storing the extracted data of the first error And a step of checking the design rule in the second layout design data, which is the layout design data of the entire semiconductor chip, the stored first error and the error of the design rule check result in the second layout design data. And the second error is A design rule checking method comprising: a step of calculating and outputting a third error obtained by removing the first error; and a step of displaying a circuit graphic including the third error. 2. The design rule checking method according to claim 1, wherein the logical operation is an exclusive OR or subtraction. 3. The design rule checking method according to claim 1 or 2, wherein the first error is a pseudo error. 4. A figure input means for inputting first pattern data, which is pattern data of a basic cell which is a unit of pattern data, and second pattern data, which is layout design data of the entire semiconductor chip, and the figure input. Graphic operation means for calculating the first pattern data and the second pattern data input from the means, and a first error that is an arbitrary error in the first pattern data processed by the graphic operation means. Error selection means for extracting an error, storage means for storing the data of the first error extracted by the error selection means, data of the first error stored in the storage means, and the graphic operation means Is compared with the second error which is an error in the second pattern data processed by The graphic operation means for outputting a third error after removing the first error, and the second error including the third error logically operated by the graphic operation means.
A design check rule system comprising: a circuit figure composed of the pattern data and display means for displaying the circuit figure in the second pattern data processed by the figure calculation unit.