JPH09162706A - Controllable input buffer, integrated circuit including it, and method for adjusting both setup and hold time of logicaldevice - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system which can simultaneously and independently control the set-up and hold time of a logical device. SOLUTION: A controllable signal filter 30 which controls the signal amplitude is applied to a logical device when the set-up and hold time are controlled for a controllable input buffer 32 and the logical device. Then the filter 30 receives a control signal to control in terms of response the characteristic that shapes the amplitude of the filter 30, so that the sum total of the set-up and hold time of the logical device is controlled. Furthermore, the filter 30 includes plural CMOS inverters which are controllably activated to actually offer various types of inverters effectively. The P-N ratio of the filter 30 is controlled when the PMOS and NMOS transistors of different numbers are activated in the invertes. Then the shaping characteristic of the filter 30 is controlled.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to the field of logic devices, and more particularly to controllable adjustment of logic device setup and hold times.

[0002]

2. Description of the Related Art Many digital logic devices use the same general devices for receiving and holding input data. In this device, a clocking signal input line connected to a logic device is provided with a periodic latching pulse, and the rising or falling edge of the latching pulse triggers a latching circuit inside the logic device. Used for. When triggered, the latching circuit captures and holds whatever logical data level is then at the data signal input line connected to the logic device.

Due to the non-zero switching speed of the parasitic line capacitances common to all logic devices and the semiconductor components commonly used in logic devices, valid data is exactly what triggers the corresponding latching circuit. It cannot be applied to the data input line at the same time. Instead, in order for the data to be properly latched, a valid transition on the input must occur on the data input line some minimum time interval prior to the occurrence of the latching pulse on the clock input line.
This shortest time interval, which is typically different for all logic devices, is known as the shortest required "setup time" of the logic device.

Similarly, valid data cannot be removed from the data input line immediately after the corresponding latching circuit is triggered without causing the latching circuit to fail. In particular, at the shortest time interval after a latching pulse occurs on the clock input line, an invalid transition on the input can occur on the data input line. This shortest time is known as the shortest required "hold time" of the logic device and is typically different for all logic devices.

Even the most basic logic designs typically require many logic devices to be driven by a common clock signal while operating on a common data input signal. It is desirable to be able to controllably adjust the setup and hold times of a given logic device so that the setup and hold times can be matched between. Prior art attempts to adjust the setup and hold times shift the data input signal in time with respect to the clock signal so that the valid setup and hold times of the logic receiving the signal are adjusted. Using a delay element for

For example, US Pat. No. 5,107,153 to Osaki et al. Discloses a delay circuit that includes a parallel connection of switchable capacitors. By changing the number of active capacitors in the circuit,
The data input signal can be controllably time-shifted with respect to the clock signal, such that both valid input transitions and non-valid input transitions of the data input signal are delayed relative to the latching pulse of the clock signal. Will be shifted. In this way, the valid setup and hold times of the logic device receiving the delayed data input signal and the clock signal are adjusted. Other controllable delay circuits may be applied to achieve the same result in such situations. For example, Woo US Pat. No. 5,
220,216 discloses a CMOS gate with programmable drive power characteristics and variable propagation delay.

However, such a system only delays the data input signal uniformly so that the effective setup time and effective hold time cannot be adjusted independently of each other. As an example, consider a data input signal that is time delayed relative to a clock signal by the amount Δ. In such a case, the valid transitions on the input of the data input signal that occur prior to the corresponding latching pulse of the clock signal will be delayed by the amount Δ, so that they are close in time to the latching pulse. Occur. Moreover, the inactive transitions of the input of the data input signal, which occur after the corresponding latching pulse of the clock signal, will be delayed by the same amount Δ, so that they occur temporally away from the latching pulse. Therefore, the effective hold time of the logic device receiving the delayed data input signal and the clock signal is reduced by the amount Δ, but at the expense of increasing the effective setup time of the logic device by the same amount Δ. It is done. This concept is expressed simply with the explanation that the sum of setup and hold times, defined as the sum of valid setup and hold times, remains constant regardless of the value chosen for Δ. Be done. Such limitations are a significant issue as designers' flexibility in choosing and mixing logical components is paramount as logical designs become more complex.

[0008]

SUMMARY OF THE INVENTION There is a need for a system that allows simultaneous but independent adjustments of logic device setup and hold times. This need and other needs are met by the present invention, which provides a controllable input buffer for driving a logic device having setup and hold time characteristics. The controllable input buffer includes a controllable signal filter that receives the input signal and shapes the amplitude of the input signal to provide the amplitude shaped input signal to the logic device. The controllable signal filter includes at least one control signal input that receives the control signal and responsively controls the amplitude shaping characteristics of the signal filter to adjust the total setup and hold time of the logic device. . Therefore, the valid setup time and valid hold time of the logic device can be adjusted independently.

The present invention further provides an integrated circuit having setup and hold time characteristics. The integrated circuit includes a logic circuit for performing a predetermined function and a controllable input buffer. The controllable input buffer is
A controllable signal filter is included to receive the input signal and shape the amplitude of the input signal to provide the logic circuit with the amplitude shaped input signal. The controllable signal filter includes at least one control signal input that receives the control signal and responsively controls the amplitude shaping characteristics of the signal filter to adjust the total setup and hold time of the integrated circuit. Therefore, the effective setup time and effective hold time of the integrated circuit can be adjusted independently.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the invention when read in conjunction with the accompanying drawings.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG.
3 illustrates a prior art system used to adjust the effective setup time and effective hold time associated with the. The shortest required setup time ST of the logic device 10 is defined as the shortest allowed time interval between the arrival of a valid input signal on the input line 14 and the occurrence of a latching pulse on the clock line 12. It If the time between a valid transition of the input on line 14 and the corresponding latching pulse on line 12 is greater than or equal to the shortest required setup time ST, the valid input. The signal is a logic unit 10
Will be properly latched by the internal latching circuitry of the logic device 10 and the logic device 10 will function as intended. However, if the time interval between a valid transition of the input on line 14 and the latching pulse on line 12 is less than the shortest required setup time ST, the valid input signal is properly latched. No, logic device 10 will not work well.

Conversely, the shortest required hold time HT of the logic device 10 depends on the occurrence of the latching pulse on the clock line 12 and the input line 1 of the valid input signal.
It is defined as the shortest allowed time interval between removal from 4 and. If the time between the latching pulse on line 12 and the inactive transition of the corresponding input on line 14 is greater than or equal to the shortest hold time HT required, then the valid input. The signal will be properly latched and the logic device 10 will function as intended. However, if the time interval between the latching pulse on line 12 and the invalid transition of the input on line 14 is less than the shortest hold time HT required, then the valid input signal will be properly latched. No, logic device 10 will not work well.

Effective setup time ST of the logic device 10
To allow adjustment of _eff and the effective hold time HT _{ef f} , a delay element 16 is provided so that the signal induced on the input line 14 is a delayed replica of the input signal reaching the input line 18. It The adjustment of the effective setup time and hold time is achieved by changing the amount of delay introduced by the delay element 16. To illustrate this, FIG. 2 shows the relative timing between the input signal arriving at input line 18, the delayed input signal induced at input line 14, and the clock signal carried at clock line 12. .

As shown, the delayed input signal on line 14
The signal is temporally relative to the input signal on line 18 by the amount Δ.
Valid transitions 26 of the shifted and delayed inputs are
The time when a valid transition 22 on the input occurs on line 18.
Occurs on line 14 after Δ. Interval t_sIs the input
A valid transition 22 and the clock latch occurring on line 12
Between the pulsing pulse 20. Furthermore, the interval t
_s'Is the valid transition 26 and clock signal of the delayed input.
It is defined between the etching pulse 20 and the pulse. By definition,
t_sAnd t_sThe relation with ′ is t_s′ = T_s−Δ. Up
As mentioned above, t _s′ Indicates that the logic device 10 functions properly
In order to have the shortest set-up time ST
Must be greater than or equal to. I
Therefore, t_sIs greater than or equal to ST + Δ or
Have to go. Therefore, this amount is
Device effective setup time ST_effIt is. ST_eff
Is a valid transition of the input on input line 18 and line 1
Shortest allowance between clock latching pulse at 2
Configure the time interval.

Similarly, an invalid transition 28 of a delayed input has a corresponding invalid transition 24 of the input on line 1.
It occurs on line 14 after the time Δ that occurred on 8. Two intervals t _h and t _h 'is, t _h' is defined to be a = t _h + Δ. Again, as described above, t _h ′
Must be greater than or equal to the minimum required hold time HT for the logic device 10 to function properly. Therefore, t _h is the amount HT
-Δ, that is, the effective hold time HT of the device of FIG.
Must be greater than or equal to _eff .

By changing the amount of delay Δ, the effective cell
Up and hold time ST _effAnd HT_eff
Can be controllably adjusted. But a valid transition of the input
Both 22 and the invalid transitions 24 of the input are respectively
By the same amount Δ to yield the delayed transitions 26 and 28
Effective setup and hold due to each delay
Time ST_effAnd HT_effIs not adjusted independently
It has ST_eff+ HT_eff= (ST + Δ) + (H
T-Δ), the setup and
Total time A_{s & h}Is constant regardless of the delay amount Δ.
is there. Therefore, effective setup time ST_effIs
Effective hold time HT_effBy the same amount
Increased or decreased only at the cost of adding
And vice versa.

FIG. 3 illustrates a system for adjusting the setup and hold times of logic devices, constructed in accordance with an embodiment of the present invention. The controllable input buffer 32 includes a controllable signal filter 30 and one or more control signal inputs 34. The controllable signal filter 30 receives the input signal on the input line 18 and outputs the amplitude-shaped input signal on the input line 14 to the logic unit 1.
Send to 0. At the same time, the control signal input 34 receives a corresponding control signal, for example from a microprocessor, to controllably adjust the amplitude shaping characteristics of the controllable signal filter 30. Therefore, the amplitude shaped input signal received by the logic device 10 is controllably adjusted, which results in a valid setup time ST of the logic device 10.
_eff and effective hold time HT _eff are adjusted to have predetermined values.

Advantageously, the embodiment of FIG. 3 allows for independent adjustment of the effective setup time ST _{ef f} and the effective hold time HT _eff of the logic device 10. To illustrate this, FIG. 4 provides a schematic diagram of a controllable signal filter 30 constructed in accordance with an embodiment of the invention.
In FIG. 4, CMOS inverters INV1 to INVN
Are connected in parallel between the input line 14 and the input line 18. Each of the CMOS inverters INV1 to INVN includes two MOS type transistors which are independently controlled.

For example, the inverter INV1 has a PMO
It includes an S transistor P1 and an NMOS transistor N1. The PMOS transistor P1 is controlled by the control signal CP1 via a control circuit having an enable transistor EP1 and a control line 34 _p1 . NMOS
The transistor N1 is controlled by a control signal CN1 via a control circuit including an enable transistor EN1 and a control line 34 _N1 .

When the control signal CP1 is a logic 0, the enable transistor EP1 is set to the "on" state,
Therefore, the PMOS transistor P1 is activated and active in the circuit. However, when the control signal CP1 is a logic one, EP1 is "off" and P1 is disabled and effectively removed from the circuit. Similarly, the control signal C
When N1 is a logic 1, enable transistor EN
1 is "on", the NMOS transistor N1 is activated and active in the circuit. When CN1 is a logic 0, EN1 is "off" and N1 is disabled and inactive.

Thus, the control signals CP1 to CPN are
PMOS transistors P1 to PN activated in the circuit
Can be used to adjust the number of control signals CN1
~ CNN can be used to adjust the number of NMOS transistors N1-NN activated in the circuit.
In this way, the P-N ratio of the controllable signal filter 30, defined as the ratio of activated PMOS transistors to activated NMOS transistors, can be tightly controlled. As described next, the P-N ratio is
It may be modified to adjust the amplitude shaping characteristics of the controllable signal filter 30 and independently adjust the effective setup and hold times of the logic device receiving the amplitude shaped input signal on input line 14. .

The input signal on the input line 18 is a logic level 0.
, The NMOS transistors N1-NN activated in the circuit are "off", causing no change in the amplitude-shaped input signal on line 14. However, the PMOS transistors P1 to P1 activated in the circuit
PN turns "on" and brings the amplitude shaped input signal on line 14 to a logic level 1 ( _Vcc ). Conversely,
When the input signal on line 18 goes to logic level 1,
Enable PMOS transistors P1-PN are "off"
, The enable NMOS transistors N1 to NN are turned “on” without causing a change in the amplitude-shaped input signal, and the amplitude-shaped input signal is set to the logic level 0.
Set to (GND).

Thus, a valid transition of the input from logic level 0 to logic level 1 is a line 18 to a line 1
On passing up to 4, it is filtered differently from the invalid transitions of the input from logic level 1 to logic level 0. The manner in which a valid transition at the input passes from line 18 to line 14 is largely determined by the number of NMOS transistors activated in the circuit, and generally, the enable N
The greater the number of MOS transistors, the faster the valid transitions of the input traveling on line 14. Conversely, the manner in which an invalid transition on the input propagates from line 18 to line 14 is primarily determined by the number of enable PMOS transistors. Again, in general, the higher the number of transistors in the enable PMOS, the faster the ineffective transitions of the input traveling on line 14. Note that the signal traveling on line 14 is actually the inverted version of the signal arriving on line 18. This is usually not a problem because many logic devices use inverting latching circuits to sample and hold the input signal. But,
If the logic device of interest does not use an inverting latching circuit, an inverter can be introduced on line 14 to restore the signal to its original direction.

The controllable signal filter 30 can be controlled to differentially filter or shape the valid and non-valid transitions of the input, so the embodiment of FIG. It can be used to adjust the hold time independently. To further illustrate this point, FIG. 5 illustrates an input signal arriving at input line 18, an amplitude shaped input signal induced on input line 14, and a clock signal transmitted on clock line 12. The relative timing between them is shown.

As shown, the amplitude shaped input signal on line 14 has a valid, valid input transition 50 corresponding to the valid input on the input signal on line 18. The transition 22 is shaped to occur on line 14 at time δ ₁ after it occurs on line 18.
The interval t _s is defined between a valid transition 22 on the input and the clock latching pulse 20 occurring on line 12. Further, the interval t _s ″ is defined between the valid, valid input transition 50 and the clock latching pulse 20. By definition, the relationship between t _s and t _s ″ is
t _s ″ = t _s −δ _1. As stated with respect to FIG. 1, t _s ″ is greater than the shortest set-up time ST required for the logic device 10 to function properly, or Must be equal to this. Therefore, t _s must be greater than or equal to the quantity ST + δ ₁ , the effective set-up time ST _eff of the device of FIG. ST _eff is input line 1
It constitutes the shortest allowable time interval between a valid transition on the eight inputs and the clock latching pulse on line 12.

Similarly, a valid, non-valid transition 5 of the input.
2 indicates that the corresponding invalid transition 24 of the input is line 1
It occurs on line 14 after a time δ _{2 of} 8 onwards.
The two intervals t _h and t _h ″ are defined such that t _h ″ is equal to t _h + δ ₂ . Again, as described with respect to FIG. 1, t _h ″ needs to be greater than or equal to the shortest hold time HT required for the logic device 10 to function properly. . Thus, t _h is the amount HT-[delta] _2, i.e. greater than the effective hold time HT _eff of the device of FIG. 3, or required to be equal to this.

By changing the value of δ ₁ , the effective setup time ST _eff can be controllably adjusted. Moreover, the effective hold time HT _eff can be controllably adjusted by changing the value of δ ₂ . δ ₁ and δ ₂
Can be adjusted independently, so that by changing the number of enable NMOS and PMOS transistors in the controlled signal filter 30 as described with respect to FIG. 4, for example, the effective setup and hold time S
T _eff and HT _eff can be adjusted independently. Similarly, the total is ST _eff + HT _eff = (ST + δ ₁ ) + (H
The sum of the setup and hold times A _{s & h} , defined as T-δ ₂ ) can be controllably adjusted.

FIG. 6 is a block diagram of an alternative embodiment of the present invention. In this embodiment, the integrated circuit 60 is
It includes a controllable input buffer 32 and a logic circuit 62. The controllable input buffer 32 includes a controllable signal filter 30 and one or more control signal inputs 34.
And Further, the logic circuit 62 includes a latching circuit 64.
And additional circuitry 66. The configuration of additional circuitry 66 is arbitrary and may be configured to perform all desired logic functions. Therefore, the integrated circuit 60
May be used as a component in any circuit design of interest. In addition, controllable input buffer 32 independently controls the effective setup and hold times of integrated circuit 60 to match the setup and hold times of other components in the circuit design, as described below. It may be used to adjust.

In the embodiment of FIG. 6, controllable signal filter 30 receives the input signal on input line 18,
The amplitude-shaped input signal is sent to the logic circuit 62 on the input line 14. At the same time, the control signal input 34 receives a corresponding control signal, for example from a microprocessor, and controllably adjusts the amplitude shaping characteristic of the controllable signal filter 30. Controllable signal filter 30
Is controllably adjusted to the amplitude shaped input signal received by logic circuit 62 and the effective setup time ST _eff and effective hold time HT _{eff of} integrated circuit 60 are, for example, as shown in FIG. It may be configured to be independently adjusted to have a predetermined value. Similarly, the total setup and hold time A _{s & h of} integrated circuit 60, which is defined as the sum ST _eff + HT _eff , is controllably adjusted.

It should be noted that the detailed embodiments described above are provided for illustration only and are not intended to limit the scope of the invention. For example, FIG.
Of the controllable signal filter 30 embodiment depicted in FIG.
Other alternatives can be considered. In one such embodiment, some of the NMOS transistors N1 to NN and some of the PMOS transistors P1 to PN are uncontrollable and remain permanently activated. Further, it is possible to envisage an embodiment in which a pair of NMOS and PMOS transistors are activated in series so that the inverters INV1 to INVN are selectively activated or deactivated as discrete units. It is also possible to envisage embodiments in which only NMOS transistors or only PMOS transistors are activated and deactivated in order to adjust the P-N ratio of the controllable signal filter. With respect to controllable signal filter 30 as used in the integrated circuit of FIG. 6, controllable signal filter 30 is not used to shape the input data signal, but instead of the clock signal or integrated circuit 60. It can also be considered as an embodiment used for shaping other signals inside. In short, the present invention has been described and illustrated in detail, but is not to be construed as limiting by, and only by way of example and example, the spirit and scope of the invention being limited only by the appended claims. Is clearly understood.

[Brief description of the drawings]

FIG. 1 is a block diagram of a prior art system for adjusting the setup and hold times of logic devices.

2 is a timing analysis diagram of the prior art system of FIG.

FIG. 3 is a block diagram of a system for adjusting the setup and hold times of logic devices, constructed in accordance with an embodiment of the present invention.

4 is a schematic diagram of a controllable input buffer constructed in accordance with an embodiment of the present invention and constituting one component of the system of FIG.

5 is a diagram of a timing analysis of the system of FIG.

FIG. 6 is a block diagram of a system used to adjust the setup and hold times of logic devices, constructed in accordance with another embodiment of the present invention.

[Explanation of symbols]

 30 controllable signal filter 32 controllable input buffer

Claims (12)

[Claims] 1. A controllable input buffer for driving a logic device having setup and hold time characteristics, the input buffer receiving an input signal and shaping the amplitude of the input signal to form an amplitude shaped input. A controllable signal filter for providing a signal to the logic device, the signal filter receiving a control signal and responsively controlling an amplitude shaping characteristic of the signal filter,
A controllable input buffer for driving a logic device including at least one control signal input for enabling adjustment of the sum of setup and hold times of the logic device to have a predetermined value. 2. A plurality of control signal inputs each receiving a plurality of control signals, said controllable signal filter comprising a plurality of CMOS inverters, at least one of said inverters having a corresponding activation. The controllable input buffer according to claim 1, wherein the controllable input buffer receives a control signal for controlling a shaping characteristic of the signal filter according to the number of activated inverters. 3. At least one of the CMOS inverters includes a PMOS transistor and an NMOS transistor, the PMOS and NMOS transistors receiving respective control signals for activation, the P-N ratio of the signal filter. 3. The controllable input buffer of claim 2, which produces a controlled shaping characteristic according to. 4. The controllable signal filter includes a plurality of control signal inputs each receiving a plurality of control signals, the controllable signal filter including a CMOS inverter and a plurality of PMOS transistors, at least one of the transistors being a plurality of PMOS transistors. 2. The controllable input buffer of claim 1, receiving a corresponding activation control signal to control shaping characteristics of the signal filter according to the number of activated transistors. 5. A controllable signal filter comprising a plurality of control signal inputs each receiving a plurality of control signals, the controllable signal filter comprising a CMOS inverter and a plurality of NMOS transistors, at least one of the transistors being 2. The controllable input buffer of claim 1, receiving a corresponding activation control signal to control shaping characteristics of the signal filter according to the number of activated transistors. 6. The controllable signal filter provides an amplitude shaped input signal to a plurality of logic devices, thereby adjusting the sum of the setup and hold times of each logic device to have a predetermined value. A controllable input buffer according to claim 1. 7. An integrated circuit having setup and hold time characteristics, comprising: a logic circuit for performing a predetermined function; and a controllable input buffer, wherein the controllable input buffer receives an input signal. A controllable signal filter for receiving and shaping the amplitude of the input signal to provide an amplitude shaped input signal to the logic circuit, the signal filter receiving a control signal and of the signal filter, A setup and hold time including at least one control signal input for responsively controlling the amplitude shaping characteristic so that the total setup and hold time of the integrated circuit can be adjusted to have a predetermined value. Integrated circuit having the characteristics of. 8. A controllable input buffer for driving a logic device having setup and hold time characteristics, the controllable input buffer receiving at least one of a data signal and a clock signal and timed the received signal. A controllable signal filter that shifts the control signal to provide the logic device with a time-shifted input signal, each signal filter receiving a plurality of control signals and the time of the signal filter. , A plurality of control signal inputs, a CMOS inverter, and a plurality of PMOSs, which control response characteristics of the shift circuit to adjust a setup time and a hold time of the logic device to have a predetermined value. And an NMOS transistor, at least one of said transistors correspondingly activating Receiving a control signal because, according to the number of activated transistors, said signal filter, for controlling the shifting characteristics, controllable input buffer for driving the logic device. 9. A method for adjusting the setup and hold time of a logic device, wherein the amplitude of an input signal of the device is shaped to have a predetermined value to obtain a total setup and hold time of the logic device. A method for adjusting the setup and hold time of a logical device, including the step of adjusting. 10. Shaping the amplitude of the input signal,
10. The method of claim 9, further comprising controlling the amplitude shaping characteristic of the controllable signal filter. 11. The method of controlling the amplitude shaping characteristic of a controllable signal filter comprises selectively activating a plurality of CMOS inverters forming the signal filter. the method of. 12. Controlling the amplitude shaping characteristics of a controllable signal filter comprises a plurality of PMOSs and Ns forming said signal filter.
The method of claim 10 including the step of selectively activating MOS transistors.