JPH09160774A - Information processing device with easy instruction expansion - Google Patents

Abstract

(57) Abstract: An information processing apparatus capable of easily expanding an instruction without expanding an instruction width or using a variable instruction or a status register is provided. An instruction extension is performed by selecting an instruction system using one or more bits of an address where an instruction is located. In a system that uses one or more bits of the process ID instead of the address where the instruction is located and the TLB to perform the address conversion, the equivalent function is realized by having the instruction extension bit as the information of the TLB.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus capable of easily expanding instructions in a microprocessor or a system using the same.

[0002]

2. Description of the Related Art In RISC processors that use a fixed-width instruction length as a method for extending the number of instructions, a method of extending the instruction length and a method of switching the instruction system by changing the status register have been used. Currently, some RISC processors support variable length instructions.

[0003]

In the method of expanding the instruction length, it is necessary to create a complicated logic in order to guarantee the compatibility with the conventional instruction code. Furthermore, as the instruction code becomes larger, the code efficiency of the program becomes worse.

Further, in the method of using the status register, the status change process must be performed every time the instruction system is changed, which causes an overhead.

Further, when variable length instructions are supported, there is a drawback that the pipeline configuration and instruction decoding become complicated.

The present invention has been made for the purpose of solving the above problems.

[0007]

When a processor fetches an instruction from memory, the address at which the instruction is located is output to the memory. In the present invention, the instruction system can be switched using the address of this instruction. A processor is built in a circuit capable of dividing an instruction space by using one or more bits of an instruction address and selecting which instruction system to use for each divided space.

[0008] For that enables the decoding of several bits Isolating the instruction code, when the instruction code is read from the memory may determine to use which instruction set in advance. Therefore, the switching of the instruction system does not become the critical path.

Besides using the arbitrary bits of the address of the above-mentioned instruction, the same function can be realized by the method of using the process number currently being executed.

Further, when the processor has a built-in TLB and an instruction is fetched using the TLB, a new instruction extension bit is provided in each entry of the TLB, so that the instruction system can be set in page units for address translation. It is possible to switch.

In the processor capable of changing the instruction system by using the instruction address as described above, the determination of the register conflict becomes complicated before and after the instruction system is switched. Therefore, it is necessary to have a register conflict determination circuit between instruction systems. However, when the instruction system is changed, it is not necessary to have a register conflict determination circuit between the instruction systems by providing a restriction that a branch instruction is used.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an embodiment in which an instruction can be expanded by selecting the type of an instruction system by using one or more bits at an arbitrary position of an instruction address.

The CPU outputs the instruction fetch address 101 to the memory through the ALU or the like. The address decoder receives only the bits necessary for distinguishing the command system in the address of this command, and generates the signal 102 for distinguishing the command system. At the same time, the instruction code 103 designated by this address is transmitted from the memory to the CPU. The CPU starts decoding the received instruction code by the decoder 104 for each instruction system, and after decoding, MU
The selection is performed using the signal 102 at X105. The decoded instruction is held in the latch 106 or the like, and the register conflict determination circuit 107 is used to check the conflict with the next instruction. Since the instruction system set by the address decoder is faster than reading the data from the memory, the signal 102 is predetermined when the decoder 104 decodes it. Therefore, it is possible to stop the processing at the time of decoding without using the MUX 105.

By making the address entering the address decoder of FIG. 1 the process ID, one or a plurality of bits at an arbitrary position of the currently executed process number is used in place of the instruction extension bit to select the type of instruction system. You can also do it.

In FIG. 2, each TLB entry has one or a plurality of instruction extension bits, and the instruction extension bit is read at the time of instruction fetch to select the type of instruction system before instruction decoding. 1 shows an information processing device capable of instruction expansion. The difference between FIG. 1 and FIG. 2 is that the instruction extension bit (EX bit) of TLB is used in FIG. 2 instead of the address decoder of FIG. C
The address 201 is input to the TLB from the PU. Information on the TLB of the corresponding index is read by the index portion 203. This and the address 2
The TAG unit 202 of 01 is compared by the comparator 204, and the valid bit (V) read out is ANDed by the AND circuit 205.
Is taken, and it becomes the TLB hit judgment signal 206, and the CPU
Output to TL hit by the judgment of this TLB
At the same time that the B information 207 is sent to the CPU, the EX bit 209 for selecting the instruction system is also sent to the CPU. Access to memory is physical address PPN converted by TLB
(208) is used, and the instruction code 210 read therefrom is sent to the CPU. The decoding process in the CPU is the same as in FIG.

[0016]

According to the present invention, it becomes possible to increase the instruction length or expand the number of instructions without introducing variable length instructions. Further, it is possible to hide the overhead required for changing the status, as compared with the method of changing the instruction system by using the status register.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing apparatus that switches an instruction system according to an instruction address according to an embodiment of the present invention.

FIG. 2 is a block diagram of an information processing apparatus that has a TLB instruction extension bit according to an embodiment of the present invention and switches the instruction system.

[Explanation of symbols]

101, 201 ... Address for instruction fetch from CPU, 102 ... Signal indicating instruction system type as a result of decoding address, 103, 210 ... Instruction code read from memory, 104, 211 ... Instruction decoder for each instruction system, 105 , 212 ... Selector of instruction system, 106 ...
Latch that holds the decoding result of the selected instruction, 1
07 ... Register conflict determination circuit between instruction systems, 2
02 ... address TAG part, 203 ... address index part, 204 ... TLB address comparator, 205 ...
Address hit signal generation AND gate in TLB, 20
6 ... Address hit signal from TLB, 207 ... Address TLB information, 208 ... Physical address corresponding to logical address hit address, 209 ... Instruction extension bit corresponding to logical address hit address.

Continuation of the front page (72) Inventor Yasuhisa Shimazaki 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Division

Claims (5)

[Claims] 1. An information processing apparatus, wherein an instruction is expanded by selecting a type of an instruction system by using one or a plurality of bits at an arbitrary position of an instruction address. 2. An information processing apparatus, wherein an instruction is expanded by selecting a type of an instruction system by using one or more bits at an arbitrary position of a process number currently being executed. 3. A processor for fetching an instruction by using a TLB has one or a plurality of instruction extension bits for each entry of the TLB, and the instruction extension bit is read at the time of instruction fetching before instruction decoding. An information processing apparatus characterized by performing instruction expansion by selecting a type of instruction system. 4. An information processing apparatus having a circuit for determining a register conflict between instructions before and after an instruction causing a page crossing whose instruction system changes. 5. An information processing system characterized in that a branch instruction is always used for fetching an instruction when the instruction system is changed, and it is not necessary to detect a register conflict before and after the instruction system is changed. apparatus.