JPH09160768A - Program execution device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To replace the instruction to be carried out by an instruction execution means with another instruction with no interruption given from the instruction execution means during execution of a program. SOLUTION: A CPU 1 outputs an address signal D1 for execution of an instruction included in a ROM 2. When a judging means 8 judges that the address designated by the signal D1 is coincident with the address of a specific instruction to be replaced with another in the ROM 2, an address signal D3 showing the address of a RAM 3 is given to the RAM 3 from an address conversion means 16. At the same time, a RAM selection signal is given from an enabling signal generation means 9. Therefore, an instruction is outputted from the RAM 3 and executed by the CPU 1 in place of the specific instruction that should be originally outputted to the CPU 1 from the ROM 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit (hereinafter referred to as CPU), a read only memory (hereinafter referred to as RO).
M), random access memory (hereinafter referred to as RAM), and the like, which is preferably used in a computer including other configurations, among the instructions stored in the ROM, instructions that cannot be executed by the CPU. Alternatively, the present invention relates to a program execution device that executes an instruction that is not executed by replacing it with another executable instruction.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram showing a specific configuration of the first conventional technique. The first conventional technology is CPU, RO
It is provided in an electronic device such as a computer including M, RAM, and other circuits. Conventionally, predetermined processing to be performed by the CPU of an electronic device such as a computer is performed using a program stored in a read-only ROM.

Electronic devices such as computers have basically the same structure due to technological advances in recent years, but small-scale improvements are frequently made. In particular, improvements in the CPU and the like have been made to improve the overall processing speed of the apparatus.
However, when it is desired to improve the device only by replacing the CPU due to a problem such as cost, the predetermined process is performed by using an instruction that constitutes an unmodified program stored in the existing ROM. Because
In some cases, some of the instructions cannot be executed by the improved CPU. In addition, after the program is written in the ROM, a defect may be found in the program and it may be necessary to change the program. To avoid the increase in cost caused by replacing the ROM itself, such a problem may occur.
This is achieved by replacing some non-executable instructions or non-executable instructions stored in the OM with executable instructions.

The first prior art is provided in an electronic device such as a computer for the purpose of replacing an unexecutable instruction or an instruction not to be executed with another executable instruction. The first conventional technique includes registers r1 to rn, comparators s1 to sn, and an OR circuit 55. Each register r1 to rn stores each address of a plurality of specific instructions stored in the ROM. That is, 1
An address indicating one specific instruction is stored in one register. The specific instruction is an instruction stored in the ROM and is replaced with another instruction so as not to be executed by the CPU.

Each of the comparators s1 to sn has two input terminals and one
Output terminals, and the respective registers r1 to rn are connected to the respective one input terminals. In addition, each comparator s1
An address line 54 from the CPU is connected to each of the other input terminals of -sn. In addition, each comparator s1 to sn
Are all supplied to the OR circuit 55, and the OR circuit 5
The output of 5 is connected to the interrupt request terminal of the CPU.

In the ROM, a plurality of instructions forming a program executed by the CPU are stored in respective storage areas. The CPU outputs an address signal to the address line 54 to execute the instruction stored in the ROM. Each of the comparators s1 to sn sequentially compares the address indicated by the output address signal with each address stored in each of the registers r1 to rn, and detects whether they match. When each of the comparators s1 to sn detects a match, the OR
For example, a high-level match signal is output to the circuit 55.
The OR circuit 55 outputs a high-level detection signal to the interrupt request terminal of the CPU when a high-level match signal is given from any of the comparators s1 to sn. The CPU
When the detection signal is input to the interrupt request terminal, the interrupt process examines which address detected the match, and performs a process of replacing with another instruction according to the specific instruction indicated by the address. Therefore, when the specific instruction is replaced with another instruction, the CPU uses the interrupt processing, and therefore overhead processing that is processing other than the program execution processing is performed, resulting in a problem that the efficiency of the program execution processing deteriorates. . Also, CPU
The interrupt process of is used to replace another command that can be executed according to a specific command, so during that process,
There is also a problem of delaying another interrupt process.

Second disclosed in Japanese Laid-Open Patent Publication No. 2-135547
In the prior art, in an in-circuit emulator of an electronic device such as a computer, a relative branch instruction to its own address or a software interrupt instruction is used by using an instruction injection unit provided in a data line in which an instruction is input from a ROM to a CPU. The purpose is to inject and break the program execution without using the interrupt terminal.

Therefore, in the second prior art, an instruction can be injected, but in the process of replacing with another instruction that can be executed according to a specific instruction, an interrupt instruction is injected by software to generate an interrupt process. You can't do it without it. Therefore, overhead processing, which is processing other than the program execution processing, is performed, and the efficiency of the program execution processing deteriorates. Further, the case where the interrupt processing is generated by software has a more complicated structure than the case where the interrupt processing is performed using the interrupt request terminal of the first prior art.

[0009]

In the first and second prior arts, when the instruction executing means such as the CPU replaces the specific instruction with the executable instruction, the interrupt processing is performed during the execution of the program. However, the overhead processing other than the processing for executing the program is performed, which causes a problem that the efficiency of the program execution processing deteriorates.

An object of the present invention is to provide a program execution device which replaces an instruction executed by the instruction executing means with another instruction without the instruction executing means performing interrupt processing during execution of the program.

[0011]

According to the present invention, a plurality of instructions constituting a program to be executed are stored in advance,
A plurality of predetermined addresses are set in the storage area in which each instruction is stored, a read signal for instructing the reading of the instruction, an address signal for designating the storage area in which the instruction to be read is stored, and an instruction Read-only first storage means for outputting a designated instruction when a permission signal for permitting the reading of the data is given, and a specific instruction selected from a plurality of instructions constituting the program to be executed. Instead, an instruction to be executed is stored in advance, an address different from the address of the first storage means is set in the storage area in which the instruction is stored, and a read signal for instructing the read of the instruction and a read signal Second storage means for outputting the designated instruction when an address signal designating a storage area storing the instruction to be issued and a permission signal permitting the reading of the instruction are given. An instruction execution means for outputting the read signal and an address signal designating an address of the first storage means for reading the instruction, and executing the instruction read from the first or second storage means; and the instruction execution means. Determining means for determining whether or not the address designated by the address signal from the determining means matches the address of the storage area in which the specific instruction is stored, and in response to the output of the determining means, when the addresses match, the second In response to the address signal designating the address of the storage means and the address conversion means for giving the address signal from the instruction execution means to the first and second storage means when the addresses do not match, and the output of the determination means, the address Generating a permission signal that outputs a permission signal to the second storage means when the addresses match and outputs a permission signal to the first storage means when the addresses do not match. A program execution device which comprises a stage. According to the invention, the first storage means stores the instructions constituting the program to be executed, and the second storage means stores the specific instruction selected from the instructions stored in the first storage means. The instruction to be executed instead of is stored.
The instruction execution means outputs an address signal designating an address of the first storage means and a read signal in order to execute the program stored in the first storage means. The read signal is commonly applied to the first and second storage means. When the determining means determines that the address designated by the address signal from the instruction executing means does not match the address at which the specific instruction is stored, that is, the instruction executing means is about to execute an instruction other than the specific instruction. At this time, the address conversion means gives the address signal from the instruction execution means to the first and second storage means, and the permission signal generation means gives the permission signal to the first storage means. Therefore, the instruction at the designated address is output from the first storage means, and the instruction execution means executes the instruction. When the determining means determines that the address designated by the address signal from the instruction executing means matches the address at which the specific instruction is stored, the address converting means indicates the address of the second storage means. An address signal is given to the first and second storage means, and a permission signal is given to the second storage means from the permission signal generating means. Therefore, instead of the specific instruction that should originally be output from the first storage means, an instruction is output from the second storage means and executed by the instruction execution means. As a result, when executing the program stored in the first storage means, the instruction execution means does not perform any special processing, and the specific instruction in the instructions stored in the first storage means is stored in the second storage means. It becomes possible to execute by replacing the stored instruction. Therefore, as in the first and second prior arts, for example, when any of the instructions forming the program to be executed is replaced using the interrupt processing of the instruction executing means realized by the CPU. As a result, the overhead that is a process other than the program execution process in the instruction executing means can be reduced. Further, unlike the first conventional technique, since the interrupt processing of the instruction executing means realized by the CPU is not used, it is possible to prevent the interruption of another interrupt processing.

Further, according to the present invention, a plurality of instructions forming a program to be executed are stored in advance, and a plurality of predetermined first addresses are set in a storage area in which the respective instructions are stored. Read-only that outputs the specified instruction when a read signal that instructs the reading of the instruction, an address signal that specifies the storage area in which the instruction to be read is stored, and a permission signal that permits the reading of the instruction are given Data storage area having a plurality of second addresses different from the first address, and one or more third addresses selected from the second addresses. The area stores an instruction to be executed in place of a specific instruction selected from the instructions constituting the above-mentioned execution program, and indicates reading / writing of data. A read / write signal, an address signal for designating a data storage area for reading / writing data, and a read / write operation for outputting / inputting designated data when a permission signal for permitting reading / writing of data is given. / Writable second storage means, the read signal for reading an instruction and an address signal designating an address of the first storage means are output to the first storage means, the read instruction is executed, and the instruction is executed. Second when needed
An instruction execution means for outputting the read / write signal and an address signal for designating an address of the second storage means for reading / writing data from / to the storage means, and an address signal from the instruction execution means are designated. When the address of the determination means is affirmative, based on the output of the determination means and the determination means that determines whether the address matches the address of the storage area in which the specific command is stored,
An address converting means for outputting an address signal designating the third address to the second storage means, and outputting an address signal from the instruction executing means to the second storage means when the judgment of the judging means is negative; Based on the address signal from the instruction executing means and the output of the judging means, when the address designated by the address signal is the first address and the judgment of the judging means is affirmative, the permission signal is sent to the second storage means. Is output and the address designated by the address signal is the first address, and the determination by the determination means is negative, a permission signal is output to the first storage means and the address designated by the address signal is the first address. When it has two addresses, the program execution device is characterized by including a permission signal generating means for outputting a permission signal to the second storage means. According to the invention, the first storage means is read-only,
Instructions constituting a program to be executed are stored, the second storage means is readable / writable, and the first storage means is readable / writable.
The data storage area has a plurality of second addresses different from the first address of the storage means. Further, the second storage means is provided with one or more third storages existing in the second address.
In the data storage area indicated by the address, an instruction to be executed is stored instead of the specific instruction among the instructions stored in the first storage means. The instruction executing means outputs, to the first storage means, an address signal designating a first address of the first storage means and a read signal in order to execute the program stored in the first storage means. Further, the instruction executing means outputs a read / write signal and an address signal indicating the second address when reading / writing data from / to the second storage means as needed during the execution of the program. When the determination means determines that the first address does not match the address in which the specific instruction is stored when the address signal from the instruction execution means specifies the first address, the address conversion means determines The address signal from the instruction executing means is given to the second storage means, and the address signal from the instruction executing means is given to the first storage means. Further, the permission signal generating means gives a permission signal to the first storage means. Therefore, the instruction execution means reads and executes the instruction from the first storage means. Next, when the address signal from the instruction executing means specifies the first address and the determining means determines that the first address matches the address in which the specific instruction is stored, the address converting means. From the above, an address signal indicating the third address is given to the second storage means, and from the permission signal generating means, a permission signal is given to the second storage means. Therefore, the instruction execution means reads and executes the instruction from the second storage means. When the address signal from the instruction executing means specifies the second address, the address converting means gives the address signal from the instruction executing means to the second storage means, and the permit signal generating means outputs the second signal. A permission signal is given to the storage means. Further, either a read signal or a write signal is output to the second storage means depending on whether reading or writing is performed. Therefore, writing and reading of data are executed in the second storage means. As a result, when executing the program stored in the first storage means, the instruction execution means does not perform any special processing, and the specific instruction in the instructions stored in the first storage means is stored in the second storage means. It becomes possible to execute by replacing the stored instruction. Further, the second storage means can be realized by a RAM or the like used by the instruction execution means as a so-called work area as needed during the execution of the program. Therefore, a dedicated storage for storing an instruction to be executed instead of the specific instruction. It is not necessary to prepare the means, and the present invention can be realized by utilizing the existing means with a relatively simple structure. Therefore, as in the first and second prior arts, the interrupt processing of the instruction executing means is utilized to replace any of the instructions constituting the program to be executed by the instruction executing means. It is possible to reduce the overhead that is a process other than the program execution process. Further, unlike the first conventional technique, since the interrupt processing of the instruction executing means realized by the CPU is not used, it is possible to prevent the interruption of another interrupt processing.

According to the present invention, the judging means includes an address storing means for storing an address signal indicating an address of a storage area in which the specific instruction is stored, an address signal stored in the address storing means, and an instruction. And a detection means for detecting whether or not the address signal from the execution means matches. According to the invention, the address storage means stores in advance an address signal indicating an address designating a specific instruction among the instructions stored in the first storage means, and the detection means stores the address signal from the instruction execution means. When the address signal is input,
The address signal stored in the address storage means is compared to detect whether they match. Thereby, the judging means can detect whether or not the address signal output by the instruction executing means is an address signal indicating an address designating a specific instruction.

According to the present invention, the address storage means is
Comparing circuit which is one or more registers for storing an address signal composed of a plurality of bits, wherein the detecting means is provided corresponding to the register and compares the address signal from the register with the address signal from the instruction executing means. And an OR operation circuit to which the output from the comparison circuit is given. According to the present invention, the address storage means is one or more registers for storing an address signal composed of a plurality of bits, and each register specifies a specific instruction among the instructions stored in the first storage means. The address signal indicating the address is stored. When the address signal is input from the instruction execution means, the comparison circuit compares each address with the input address signal for each register, and the determination means uses the OR operation circuit to determine whether any one of the comparison circuits matches. When a certain signal is output, a signal whose determination is positive is output, and when all the comparison circuits output signals that do not match, a signal whose determination is negative is output.

According to the present invention, the address storage means is
The address signal consisting of multiple bits is divided into a predetermined number of upper bits and the remaining lower bits, and each address signal having the same upper bit is divided into groups, and the address signals are stored in group units. To 1
Of the upper bit register and the same number of lower bit registers as the number of address signals belonging to the group, and the detection means, for each group, the upper bit register signal and the upper bit of the address signal from the instruction execution means. And one or more lower bit comparison circuits for comparing the signal of each lower bit register and the lower bit of the address signal from the instruction execution means, which are provided in the same number as the lower bit register. , One or more AND circuits to which the output of each lower bit comparison circuit and the output of the upper bit comparison circuit are provided, and the output of each AND circuit are provided.
And a second OR circuit to which the output of the first OR circuit of each group is given. According to the present invention, the address storage means includes one high-order bit register for storing a predetermined number of high-order bits of the address signal and a plurality of low-order bit registers for storing the remaining low-order bits of which the high-order bits in the address signal are common. Address signals are stored in units of a plurality of groups. A predetermined number of high-order bits of an address signal indicating an address designating a specific instruction among the instructions stored in the first storage means are stored in a high-order bit register, and the high-order bits of the address signal are common to a plurality of low-order bits. Each bit is stored in the lower bit register. The detecting means compares each group when the address signal from the instruction executing means is input. Within each group, the upper bit of the address signal is compared with the bit value stored in the upper bit register, and the lower bit of the address signal is compared with the bit value stored in each lower bit register. When both the upper bit and the lower bit detect a match, the detecting means detects a match of the address signal. The determination means outputs a signal that the determination is affirmative when detecting a match of the address signals, and outputs a signal that the determination is negative when a match is not detected in all the groups. As a result, the number of registers can be reduced as compared with the case where the register is configured without dividing the register into the upper bit register and the lower bit register, and the register for one bit is composed of a plurality of gates. Therefore, the number of gates can be reduced.

According to the present invention, the permission signal generating means is
Decoding for outputting a first signal when the address designated by the address signal is the first address and outputting a second signal when the address designated by the address signal is the second address based on the address signal from the instruction executing means Means, a logical AND operation of the first signal and the inverted signal of the output of the judging means, and giving the operation result to the first storage means, an OR operation of the second signal and the output of the judging means. And an OR operation means for giving the operation result to the second storage means. According to the present invention, when the address signal from the instruction execution means is input to the permission signal generation means, if the address designated by the address signal indicates the first address of the first storage means, the decoding means For example, a high level signal is output as the first signal, and a low level signal is output as the second signal. When the output of the judging means is affirmative, the logical product calculating means inputs the first signal and a signal indicating affirmative of the judging means, for example, a signal obtained by inverting a high level signal, and outputs the result to the first storing means as the calculation result. , For example, it outputs a low-level permission signal indicating non-permission. on the other hand,
The logical sum calculation means inputs the second signal and a signal indicating affirmative of the determination means, for example, a high level signal, and outputs a high level permission signal indicating permission, for example, as a calculation result to the second storage means. . Therefore, the instruction execution means reads and executes the instruction from the second storage means. When the output of the judging means is negative, the logical product calculating means inputs the first signal and a signal indicating the negative of the judging means, for example, a signal obtained by inverting a low level signal, and calculates in the first storing means. As a result, for example, a high-level permission signal indicating permission is output. On the other hand, the logical sum operation means is the second
A signal and a signal indicating the negation of the determination means, for example, a low level signal, are input, and the second storage means outputs a calculation result.
For example, a low level permission signal indicating non-permission is output. Therefore, the instruction execution means reads and executes the instruction from the first storage means. When the address designated by the address signal indicates the second address of the second storage means, the decoding means outputs, for example, a low level signal as the first signal and outputs a high level signal as the second signal. To do. The logical product calculating means inputs the first signal and a signal indicating the result of the judging means, and outputs, for example, a permission signal indicating non-permission as the calculation result to the first storage means. On the other hand, the logical sum calculation means inputs the second signal and a signal indicating the result of the determination means, and outputs, for example, a permission signal indicating permission as the calculation result to the second storage means.

According to the present invention, the permission signal generating means is
The present invention is characterized by including delay means for delaying the output of the judging means for a predetermined period and giving it to the OR operation means. According to the invention, in the permission signal generating means, the logical sum calculating means receives the signal indicating the result of the judging means and the second signal and outputs the calculation result to the second storing means. The delay means inputs the signal indicating the result of the judging means before being input to the logical sum calculating means, delays the signal for a predetermined period, and outputs the signal to the logical sum calculating means. Therefore, since the converted address signal is supplied from the address conversion means and then the permission signal is supplied, the reading of the instruction to be replaced with the specific instruction is surely executed in the second storage means.

According to the present invention, the address conversion means is
Address signal generating means for generating an address signal for designating the third address, and in response to the output of the judging means,
Switching means for outputting the address signal from the address signal generating means when the judgment of the judging means is affirmative, and for outputting the address signal from the instruction executing means when the judgment of the judging means is negative. Is characterized by. According to the invention, the switching means in the address converting means outputs the address signal which is the output of the address signal generating means to the second storing means when the signal indicating the affirmative of the judgment is inputted from the judging means, and the judging means. When a signal indicating negative determination is input from, the address signal from the instruction executing means is output to the second storage means.

According to the present invention, the judging means compares the address storing means for storing a plurality of address signals, the address signal from the instruction executing means, and the address signal stored in the address storing means. The address signal generating means includes a high-order address memory for storing a predetermined number of high-order bit address signals, and a residual result based on the comparison result in the detecting means. And a lower address generating means for generating an address signal of lower bits. According to the present invention, the address storage means in the determination means stores in advance an address signal indicating an address designating a specific instruction among the instructions stored in the plurality of first storage means. A plurality of address signals are stored in the order of the address of the means. The predetermined number of high-order bits of the third address of the second storage means are stored in the high-order address memory of the address signal generating means. When the address signal from the instruction execution means is input to the determination means, the detection means in the determination means compares the address signals stored in the plurality of address storage means with each other to detect whether they match. The address signal generating means detects, based on the comparison result in the detecting means, which address signal matches, generates the remaining lower bits, and synthesizes the remaining lower bits to generate the address signal.
For example, when 16 address signals are sequentially stored in the address storage means and the eighth stored address signal matches the address signal from the instruction execution means, the remaining lower bits are: It is 4-bit “0100” indicating “8”. Therefore, since the third address is determined corresponding to each of the address signals indicating the addresses designating the plurality of specific instructions stored in the determination means, the instructions to be executed can be replaced accurately.

The present invention is also characterized in that the instruction executing means performs reading / writing on the upper address memory. According to the invention, the instruction execution means changes the value of the third address of the second storage means in which the instruction to be executed is stored instead of the specific instruction among the instructions stored in the first storage means. In this case, the bit value stored in the upper address memory in the address signal generating means is rewritten so as to be adapted to the changed third address value. Therefore, the versatility of the present device is improved because the range of selection is widened when designing the system of the present device, compared to the case where the upper address memory cannot be written.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION In an electronic device such as a computer including the program execution device of the present invention, predetermined processing to be performed by the device is performed using a program stored in a read-only ROM. . Electronic devices such as computers have the same basic configuration due to technological advances in recent years, but small-scale improvements are frequently made. In particular, improvements in the CPU and the like have been made to improve the overall processing speed of the apparatus. However, if the device is configured only by replacing the CPU due to cost or the like, the predetermined process is performed in the existing R
Because it is done with the instructions that make up the unmodified program stored in the OM, some of the instructions may not be executable in the improved CPU. In addition, after the program is written in the ROM, a defect may be found in the program and it may be necessary to change the program. Such a problem is avoided by replacing some non-executable instructions stored in the ROM with executable instructions. The present invention has been made for the purpose of facilitating the replacement of the above instructions, and one embodiment of the present invention will be described below.

FIG. 1 is a diagram showing an electrical configuration of a program execution device according to an embodiment of the present invention. The program execution device is a central processing unit (hereinafter, CPU) 1
And read-only memory (hereinafter referred to as ROM) 2,
Random access memory (hereinafter referred to as RAM) 3,
And an integrated circuit (hereinafter referred to as ASIC) 4 for a specific application. The ASIC 4 includes a determination unit 8, a permission signal generation unit 9, and an address conversion unit 16.

The ROM 2 stores a plurality of instructions constituting a program executed by the CPU 1 in each storage area. The address of the storage area in the ROM 2 is generically called the first address.

The RAM 3 has a storage area that can be used by the CPU 1 to execute programs, and the address indicating the storage area is generically called the second address. Data can be written to and read from the storage area indicated by the second address. Further, a plurality of addresses indicating a part of the storage area in the second address is set as a third address, and an instruction to be executed in the storage area indicated by the third address instead of the instruction stored in the ROM 2 (hereinafter, specified (Referred to as an instruction) is stored. The number of instructions stored is in the ROM
It is the same as the number of specific instructions in 2, and is read from the attached memory, hard disk, etc. of the apparatus and written in the storage area indicated by the third address in RAM 3 before the program in ROM 2 is executed.

The CPU 1 outputs an address signal to the address line 5 and a read signal and a write signal to the read / write line 7 in order to sequentially execute the programs stored in the ROM 2. Address line 5 from CPU1
Is the ROM 2 and the permission signal generating means 9 in the ASIC 4.
Then, it is connected to the judging means 8 and the address converting means 16. Further, the data line 6 capable of reading and writing instructions and data executed by the CPU 1 is the CPU 1
And ROM2 and RAM3. CPU
Read / write lines 7 from 1 are ROM 2 and RAM
3 is connected. Only the read signal is input to the ROM 2, and the instruction to be executed and necessary data are read to the CPU 1. A read signal and a write signal are input to the RAM 3, and the CPU 1 performs processing according to each signal.

The judging means 8 judges whether the address designated by the address signal D1 input from the address line 5 from the CPU 1 matches the address indicating the specific instruction stored in the ROM 2, and when they match. For example, the detection signal SSP is given to the permission signal generating means 9 and the address converting means 16, and the coincidence result signal X16 is given to the address converting means 16.

The address converting means 16 is supplied with the address signal D1 from the CPU 1 through the address line 5 and the detecting signal SSP and the coincidence result signal X16 from the judging means 8. When the detection signal SSP is input, the address signal D3 indicating the third address in the RAM2 created based on the match result signal X16 is output to the RAM3. When the detection signal SSP is not input, the input address signal D1 is output to the RAM3.

The permission signal generating means 9 inputs the address signal D1 from the CPU 1 through the address line 5 and the detection signal SSP from the judging means 8. Permission signal generating means 9
Outputs to the ROM 2 or the RAM 3 a ROM select signal permitting the reading of the instruction of the ROM 2 or a RAM select signal permitting the reading of the instruction and the data of the RAM 3, respectively, based on the input signal.

For example, when the input address signal D1 indicates the first address and the detection signal SSP is not input, the permission signal generating means 9 outputs the ROM select signal to the ROM2, and the address signal D1 indicates the first address. When the detection signal SSP is input, the RAM select signal is output to the RAM 3, and when the address signal D1 is the second address, the RAM select signal is RA.
Output to M3.

When the CPU 1 outputs the address signal D1 to the address line 5 and the read signal to the read / write line 7, the read signal is given to the ROM 2 and the RAM 3. The address signal D1 is given to the judging means 8, and the judging means 8 compares the address indicated by the address signal D1 with the addresses of a plurality of specific instructions in the ROM 2,
It is determined whether they match.

When the judging means 8 judges that they coincide with each other, the judging means 8 outputs the detection signal SSP to the permission signal generating means 9 and the address converting means 16, and outputs the coincidence result signal X16 to the address converting means 16. Output. The address conversion means 16 creates an address signal D3 indicating the third address based on the coincidence result signal X16, and outputs the address signal D3 to the RAM3 via the RAM address line 15. At this time, the permission signal generating means 9 outputs a RAM select signal to the RAM 3. Therefore, the reading of the RAM 3 is permitted, and the CPU 1 replaces the instruction stored in the ROM 2 and executes the instruction stored in the RAM 3.

Next, when the judging means 8 judges that they do not coincide with each other and the address indicated by the address signal D1 is the first address, the judging means 8 detects the enable signal generating means 9 and the address converting means 16. Does not output the signal SSP. The address conversion means 16 outputs the input address signal D1 to the RAM 3 via the RAM address line 15. The permission signal generating means 9 outputs the ROM select signal to the ROM.
Output to 2. Therefore, the reading of the ROM 2 is permitted, and the CPU 1 executes the instruction stored in the ROM 2.

Further, when the judging means 8 judges that they do not coincide with each other and the address indicated by the address signal D1 is the second address, the judging means 8 causes the enable signal generating means 9 and the address converting means 16 to detect the detection signal. Do not output SSP. The address conversion means 16 outputs the input address signal D1 to the RAM 3 via the RAM address line 15. The permission signal generating means 9 sends the RAM select signal to the RAM.
Output to 3. Therefore, the reading of the RAM 3 is permitted, and the CPU 1 reads the data stored in the RAM 3 and performs the processing. If the signal output to the read / write line 7 is a write signal, the CPU 1 performs a process of writing data in the RAM 3.

The judgment means 8 is a register R1 to R for storing the addresses of a plurality of specific instructions stored in the ROM2.
n, the address stored in each of the registers R1 to Rn, and C
It includes comparators S1 to Sn for comparing with the address indicated by the address signal input from PU1 via the address line 5, and an OR circuit 21 for inputting each comparison result in each comparator S1 to Sn and outputting a detection signal SSP. Composed of.

The registers R1 to Rn respectively store the addresses of a plurality of specific instructions stored in the ROM2. That is, an address indicating one specific instruction is stored in one register. For example, when the address indicating one specific instruction is “0110”, the register R
“0110” is stored in 1.

Each of the comparators S1 to Sn has two input terminals and one output terminal, and one input terminal S1a.
Each register R1 to Rn is connected to Sna. The other input terminal S1 of each comparator S1 to Sn
Address lines 5 from the CPU 1 are connected to b to Snb, respectively. All the outputs of the comparators S1 to Sn are O.
It is input to the R circuit 21, the OR circuit 21 performs an OR operation, and the operation result is output to the address conversion means 16 and the permission signal generation means 9 as a detection signal SSP. Further, the coincidence result signal X16 which is each output of each comparator S1 to Sn
Is given to the address conversion means 16.

In the judging means 8, when the address signal D1 is inputted from the CPU 1 through the address line 5, the comparators S1 to Sn are sequentially stored in the registers R1 to Rn and the address indicated by the address signal D1. It compares each address and detects whether they match. When the comparators S1 to Sn detect a match, the OR circuit 21
For example, a high-level match signal is output, and the output signals of the comparators S1 to Sn are applied to the address conversion means 16 as the match result signal X16. The OR circuit 21 is
When a high level coincidence signal is given from any one of the comparators S1 to Sn, a high level detection signal SSP is output to the address conversion means 16 and the permission signal generation means 9.

For example, when the comparator S8 detects a match between the address stored in the register R8 and the address indicated by the address signal D1 input from the CPU 1, it outputs a high-level match signal to the OR circuit 21. Then, the match result signal X16 including the match signal is output to the address conversion means 16. The OR circuit 21 outputs the high-level detection signal SSP to the address conversion means 16 and the permission signal generation means 9.

The permission signal generating means 9 includes a decoder 23,
The AND circuit 24, the OR circuit 25, and the delay unit 22 are included.

The decoder 23 is connected to the address line 5 and receives the address signal D1 from the CPU 1. In the decoder 23, the address indicated by the address signal D1 is the first
If it is an address, the high level selection signal Cx is set to A
The signal is output to one input terminal of the ND circuit 24. On the other hand, when it is the second address, the high-level selection signal Cy is OR
It outputs to one input terminal of the circuit 25.

The AND circuit 24 is a 2-input AND circuit, and the selection signal Cx from the decoder 23 is applied to one input terminal.
Is input, and the detection signal SSP is inverted and input to the other input terminal. The AND circuit 24 performs an AND operation on the input signals and outputs the operation result to the ROM 2 as a ROM select signal.

The OR circuit 23 is a 2-input OR circuit, and the selection signal Cy from the decoder 23 is applied to one input terminal.
Is input to the other input terminal and the delay unit 22
The detection signal SSP is input via the. OR circuit 2
3 performs a logical sum operation and outputs the operation result to the RAM 3 as a RAM select signal.

FIG. 2 is a circuit diagram showing a configuration example of the delay unit 22. The delay unit 22 includes a delay element 30 and a delay element 30 that delay the input signal by a predetermined period.
And a type flip-flop 31.

The delay unit 22 includes a detection signal SS
P is input. The input detection signal SSP is input to the clock terminal CK of the D-type flip-flop 31 via the delay element 30. Further, the inverted signal of the detection signal SSP is input to the inversion reset terminal of the D-type flip-flop 31, and the constant DC voltage Vcc is applied to the input terminal D of the D-type flip-flop 31.

"L" to "H" for the delay unit 22
When the detection signal SSP that has risen at is input, the inverted detection signal SSP is input to the inverting reset terminal,
A high-level detection signal delayed by a predetermined time by the delay element 30 is input to the clock terminal CK.
Therefore, after the detection signal SSP is input, the delay time determined in the delay element 30 and the time required from the level of the clock terminal CK in the D-type flip-flop 31 to the level of the output terminal Q changes. The level of the output signal changes with a delay of the sum of and. Conversely, when the detection signal SSP falling from "H" to "L" is input to the delay unit 22, the level of the inverting reset terminal in the D-type flip-flop 31 changes and then the level of the output terminal Q changes. The output signal falls with a delay of the time required until.

The address conversion means 16 outputs from the encoder unit 10 for generating an address signal D3 designating a third address indicating an instruction to be executed in place of the specific instruction stored in the RAM 2, and the determination means 8. The selector 11 is configured to output to the RAM 3 either the address signal D1 output from the CPU 1 or the address signal D3 generated by the encoder unit 10 based on the detection signal SSP.

FIG. 3 is a block diagram showing a concrete configuration example of the encoder unit 10, and FIG. 4 is a diagram showing a storage area designated in the RAM 3 at the third address. The encoder unit 10 has 16 units as shown in FIG.
It has an input signal line and an output signal line for each line, and receives the 16-bit coincidence result signal X16 from the judging means 8. Here, it is assumed that the number of specific instructions stored in the registers R1 to Rn of the judging means 8 is 16 or less, and the numerical value of n is "16" or less. Encoder unit 10
Stores an encoder 35 that calculates 4 bits of the address signal D3 designating the third address based on the match result signal X16, and stores 10 bits of the address signal D3 corresponding to the third address of the RAM 3. Memory 36
It is comprised including. The encoder unit 10
Has 16 output terminals A0 to A15. Output terminal A
0 indicates the LSB (least significant bit), and the output terminal A15
Indicates the MSB (most significant bit). Further, here, the output terminals A0 and A1 of the encoder unit 10 are connected to the ground potential inside the encoder unit 10 and always output a low level signal.

The encoder 35 receives the coincidence result signal X16 from the judging means 8 and produces a 4-bit signal output from the output terminals A2 to A5 of the encoder unit 10. For example, when the comparator S5 of the judging means 8 detects a match between the first address indicated by the address signal D1 and the first address stored in the register R5, the encoder 35 has only the fifth input signal line. Is given a high-level match result signal X16 and 4-bit "0101"
Signal is generated and output from the output terminals A2 to A5.

In the memory 36, the encoder unit 10
The 10-bit address output from the output terminals A6 to A15 is stored and is output from the output terminals A6 to A15 as the upper 10 bits of the address signal D3. 4 bits of the address signal D3 generated by the encoder 35 and the address signal D previously stored in the memory 36
3 bit and address signal D3 created by forcibly setting the output terminals A0 and A1 to low level
2 bits, the 16-bit address signal D3 is output from the output terminals A0 to A15 of the encoder unit 10.

As described above, the address signal D3 is detected by the comparators S1 to S16 which detect the coincidence between the address of the specific instruction stored in the registers R1 to R16 of the judging means 8 and the address indicated by the address signal D1 from the CPU 1. It is decided according to. For example, in the output address signal D3, when the upper 10 bits of the address signal D3 from the memory 36 is TBLADR, TBLAD
R, TBLADR + 4, ..., TBLADR + 4 × 15, and the storage area at the third address in the RAM 3 has the configuration shown in FIG.

For example, when the comparator S1 detects a match, the lower 35 bits of the address signal D3 becomes "000000" by the encoder 35, the address indicated by the address signal D3 becomes TBLADR, and the CPU 1 specifies in the ROM2. Instead of the instruction, an absolute jump instruction which is an instruction in the storage area m1 in the RAM 3 is executed, and the processing of the jump destination is performed. When the comparator S2 detects a match, the encoder 35 causes the lower 6 bits of the address signal D3 to be “000100”, the address indicated by the address signal D3 to be TBLADR + 4, and the CPU 1 replaces the specific instruction in the ROM 2 with it. , R
The absolute jump instruction which is the instruction of the storage area m2 in the AM3 is executed, and the processing of the jump destination is performed. Similarly, when the comparators S3 to S15 respectively detect a match, the encoder 35 determines the lower 6 bits of the address signal D3, and the address indicated by the address signal D3 is TBLADR + 4 × 2, TBLADR + 4 × 3 ,.
TBLADR + 4 × 15, and the CPU 1 replaces the specific instruction in the ROM 2 with each storage area m3 in the RAM 3
The absolute jump instruction, which is the instruction up to m16, is executed, and the processing of the jump destination is performed.

FIG. 5 is a time chart for explaining the operation when reading an instruction from the RAM 3. When the address signal D1 is output from the CPU 1 to the address line 5, the level of the address line changes as shown in FIG. In the judging means 8, the address signal D outputted from the CPU 1
When 1 and the address of each specific instruction stored in each register R1 to Rn match, the detection signal SSP rises with a delay of the period A. The period A indicates a delay time by each of the comparators S1 to Sn of the judging means 8 and the OR circuit 21.

The level of the RAM address line 15 changes in synchronization with the change of the level of the address line 5. Selector 1
1, when the detection signal SSP is input (when it rises),
The address signal generated by the encoder unit 10 is RA
The output is switched to M3. Therefore RAM
The address line 15 is delayed by the period B from the rising time of the detection signal SSP, and the RAM address line 15 is further changed. The period B is a delay time required for changing the output of the selector 11.

Delay unit 2 of permission signal generating means 9
2 is a detection signal SSP that rises from "L" to "H"
Is input, a RAM select signal is output to RAM3. Therefore, the RAM select signal is the detection signal SSP.
Rises with a delay of B + C after the rise. The period B + C is a delay time obtained by adding the delay time determined by the delay element 30 and the delay time required from the change of the level of the clock terminal CK of the D-type flip-flop 31 to the change of the level of the output terminal Q. Indicates. As a result, the instruction from the RAM 3 is given to the CPU 1,
Since no ROM select signal is input to ROM2,
No instructions are read from the ROM2.

The delay time of the period B + C is the address signal D
3 is provided in order to ensure the setup time required for the data to be input to the RAM 3. This is because when the RAM select signal is input (started) to the RAM 3 before the address signal D3, the address signal D originally input is input.
This is because an address is designated by an address signal different from 3, and therefore an instruction different from the instruction to be originally executed is input to the CPU 1, which causes malfunction of the CPU 1.

When the CPU 1 outputs the next address signal D1 to the address line 5 after executing the instruction indicated by the third address in the RAM 3 in place of the specific instruction stored in the ROM 2, it is shown in FIG. Thus, the level of the address line 5 changes.

The output address signal D1 is the judgment means 8
When no match is detected by being input to each of the comparators S1 to Sn, the time change from the level change of the address line 5 to the time D
The detection signal SSP falls with a delay. The period D indicates a delay time by each of the comparators S1 to Sn of the judging means 8 and the OR circuit 21.

When the detection signal SSP falls, the selector 11 of the address conversion means 16 switches to output the address signal D1 output by the CPU 1 to the RAM 3. Therefore, the RAM address line 15 is connected to the detection signal S
The level changes with a delay of a period E from the fall time of SP. The period E is a delay time required for changing the output of the selector 11.

Delay unit 2 of permission signal generating means 9
2 lowers the RAM select signal from "H" to "L" when the detection signal SSP falls from "H" to "L". Therefore, the RAM select signal falls with a delay of the period F after the detection signal SSP falls. The period F indicates a delay time required from the change of the level of the inverting reset terminal of the D-type flip-flop 31 to the change of the level of the output terminal Q. The period F is set shorter than the period C when the RAM select signal rises, and RA
At almost the same time as the fall of the M address line 15, the RAM select signal also falls. This prevents malfunction of the CPU 1 caused by the output of an unnecessary RAM select signal.

FIG. 6 is a diagram for explaining another embodiment of the invention, FIG. 6 (1) is a diagram showing a register configuration in the above-mentioned embodiment, and FIG. 6 (2) is a diagram. FIG. 3 is a diagram showing a register configuration in the present embodiment. FIG.
In the configuration A shown in (1), the address designating one specific instruction is stored in one register. Therefore, when the number of addresses to be stored in the register increases, the number of registers increases accordingly, and the number of gates configuring the register also increases in proportion to the increase in the number of registers. Further, since the number of gates used in the ASIC in which the registers R1 to Rn are provided is limited, it is necessary to suppress the increase in the number of registers so as not to exceed the limited number even if the number of addresses to be stored increases.

Therefore, in the present embodiment, as shown in FIG. 6B, an upper bit register RA1 for storing one upper bit and a lower bit for storing a plurality of lower bits having the upper bit in common. Registers R1a to Rn
a group B composed of a, another upper bit register RA2 for storing another upper bit, and lower bit registers R1b to Rnb for storing a plurality of lower bits having another upper bit in common Group C
And form a register. That is, a plurality of lower bits that are common to the upper bits are set as one group, and the address is stored in units of a plurality of groups. As a result, FIG. 6 (1)
From the register configuration of (1), the number of bit registers of (the number of upper bits) × (the number of addresses to be stored-the number of groups) can be reduced, and the number of gates can be reduced accordingly. For example, if the total number of registers of the configuration A is 32 and the upper bits are 4 bits and divided into two groups B and C, 4 × (32−
From 2) = 120, the number of registers G for 120 bits can be reduced.

FIG. 7 shows the judging means 4 in this embodiment.
It is a figure which shows the example of a specific structure of 0. As described above, the determining unit 40 is configured by a circuit in units of addresses. One group stores an upper bit register RA1 that stores each upper bit of an address of a specific instruction stored in the ROM 2 and each lower bit of an address that commonly has the upper bit stored in the upper bit register RA1. Lower bit register R1a to Rna and upper bit comparator SA1 for comparing the upper bit of the address stored in upper bit register RA1 with the upper bit of the address indicated by address signal D1 input from CPU1.
A lower bit comparator Sa1 to San for comparing the lower bit of the address stored in each lower bit register R1a to Rna with the lower bit of the address of the address signal D1 input from the CPU1, and an upper bit comparator SA.
An AND circuit A which inputs the comparison result of 1 and the comparison results of the lower bit comparators Sa1 to San and performs a logical product operation
1a to Ana and a first OR circuit OA1 which inputs the operation results of the AND circuits A1a to Ana, performs a logical sum operation, and outputs the comparison result of the groups. Although only one group has been described here, other groups have the same configuration. Further, the judging means 40
It is configured to include a second OR circuit 41 which inputs the comparison result from each of the first OR circuits OA1 to OAx and outputs the detection signal SSP.

In the judging means 40, when the address signal D1 is inputted from the CPU 1 through the address line 5, the upper bit comparator SA1 causes the upper bit of the address indicated by the address signal D1 and the address stored in the upper bit register RA1. Of the lower bit of the address indicated by the address signal D1 and the lower bit register R1.
The lower bits stored in a to Rna are compared with each other. When both the high-order bit comparator SA1 and each of the low-order bit comparators Sa1 to San match, both comparators output a high level signal. One of the AND circuits A1a to Ana that has input the two high-level signals inputs the high-level match signal to the first OR.
Output to the circuit OA1. The first OR circuit OA1 to which the high-level match signal is input outputs a high-level match signal to the second OR circuit 41, and the second OR circuit 41 outputs a high-level detection signal SSP.

For example, the high-order bit stored in the high-order bit register RA1 and the input address signal D
The upper bit comparator SA1 detects a match with the upper bit of 1, and the lower bit comparator S5a matches the lower bit stored in the lower bit register R5a and the lower bit of the input address signal D1. If the high-order bit comparator SA1 and the low-order bit comparator S5a output high-level signals, and the high-level signals are input to both inputs, the AND circuit A5a outputs the high-level match signal Output to the 1OR circuit OA1.
The first OR circuit OA1 outputs a high-level match signal to the second OR circuit 41 when the high-level match signal is input. The second OR circuit 41 has a high level detection signal SS.
P is output to the address conversion means 16 and the permission signal generation means 9.

FIG. 8 is a diagram showing another example of register configuration in the present embodiment. FIG. 8 (1) shows the register configuration AA in the above-mentioned embodiment, and FIG. 8 (2) shows the register configuration AA. Configuration D with the same total number of bits as
FIG. Here, it is assumed that there is a 24-bit address line. A program execution device having a 24-bit address line has an address space of 16 Mbytes. Register configuration AA is 24 in one register
Bit address can be stored and 32 registers R1 ~
The total number of bits of the register configuration AA configured by R32 is 24 × 32 = 768 bits. If two groups of one high-order bit register and a plurality of low-order bit registers are created with the same total number of bits,
As shown in (2), the register configuration D includes a group BB composed of a 4-bit upper bit register RA1 and nineteen lower bit registers R1a to R19a, and an upper bit register RA.
2 and lower bit registers R1b to R19b. Therefore, 38 addresses can be stored in the register configuration D, and 6 more addresses than the 32 addresses in the register configuration AA. Therefore, if the total number of bits in the register configuration is the same, the number of addresses that can be stored can be increased compared to the register configuration AA that stores addresses in a one-to-one correspondence.

When the upper bits of the address of a specific instruction to be stored are shared, the number of lower bit registers may be insufficient when a plurality of addresses indicating the specific instruction are concentrated in the neighborhood. In the entire address space, the space occupied by the first address of ROM2 is
Since it becomes a part of the entire address space, the number of bits of the high-order bit register is adjusted so that the high-order bit is the first bit of the ROM 2.
This can be avoided by associating with the address space. For example, when the storage area of the ROM 2 is 1 Mbyte, the upper 4 bits are set to the upper bit register RA1
And store the lower 20 bits in the lower bit register R1.
a to Rna, and when the storage area of the ROM 2 is 2 Mbytes, one upper 4 bits is stored in the upper bit register RA1 and the lower 20 bits corresponding to the upper bit are stored in the lower bit register R1a. ~ R
The above inconvenience can be avoided by storing the upper 4 bits of the other in the upper bit register RA2 and storing the lower 20 bits corresponding to the upper bit in the lower bit registers R1b to Rnb.

FIG. 9 is a block diagram showing an electrical configuration of an encoder unit 10 according to still another embodiment of the present invention. The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. The encoder unit 10 is
It comprises a memory 36 that is registered. The address conversion means 16 including the encoder unit 10 includes a memory 36.
A dedicated decoder 45 is provided. CPU1 to decoder 4
When the address line 46 is connected to 5 and the address signal is input to the decoder 45, the select signal is output to the memory 36 by the select line 48. A data line 47 and a read / write line 49 are connected to the memory 36. As a result, the upper bit of the third address stored in the memory 36 can be freely read and written by the read / write signal from the CPU 1 and the select signal from the decoder 45.

[0068]

As described above, according to the present invention, when it is judged by the judging means that the address designated by the address signal from the instruction executing means coincides with the address in which the specific instruction is stored. , An address signal indicating an address of the second storage means from the address conversion means is the first and second address signals.
By giving a permission signal to the second storage means from the permission signal generation means and given to the storage means, an instruction from the second storage means is given instead of the specific instruction that should originally be output from the first storage means. It is output and executed by the instruction executing means. Therefore, as in the first and second prior arts,
For example, by using the interrupt processing of the instruction executing means realized by the CPU, and replacing any one of the instructions constituting the program to be executed, the processing other than the program executing processing in the instruction executing means is performed. Some overhead can be reduced. Further, unlike the first conventional technique, since the interrupt processing of the instruction executing means realized by the CPU is not used, it is possible to prevent the interruption of another interrupt processing.

Further, according to the present invention, the second storage means is readable / writable and has a data storage area in which a plurality of second addresses different from the first address of the first storage means are respectively set. Further, the second storage means is an instruction to be executed in the data storage area indicated by one or more third addresses existing in the second address, instead of the specific instruction among the instructions stored in the first storage means. Is remembered. Therefore, a RAM used by the instruction executing means as a so-called work area as needed during program execution.
Since it is possible to realize the second storage means by using, for example, it is not necessary to prepare a dedicated storage means for storing an instruction to be executed instead of the specific instruction, and the existing means has a relatively simple configuration. The present invention can be realized by utilizing.

Further, according to the present invention, the address storing means stores a predetermined number of high-order bits of the address signal, and a plurality of high-order bit registers for storing the remaining low-order bits having a common high-order bit in the address signal. A plurality of groups are provided, with the lower bit register of 1 as one group. A predetermined number of high-order bits of an address designating a specific instruction among the instructions stored in the first storage means are stored in a high-order bit register, and a plurality of low-order bits common to the high-order bits of the address are low-order bits. Store in register. Therefore, the number of registers can be reduced as compared with the case where one address is stored for one register in the conventional storage means, and if the same number of registers is used, more addresses can be stored than the conventional one. it can.

Further, according to the present invention, the upper bits of the address stored in the upper address memory in the address signal generating means can be changed corresponding to the change of the value of the third address of the second storing means. Therefore, since the storage area of the second storage means can be used freely without being bound by the third address, the degree of freedom in selecting the storage area that can be used by the second storage means in the system design of the present apparatus is increased. The versatility of this device is enhanced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of a program execution device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an electrical configuration of a delay unit 22.

3 is a block diagram showing a specific configuration of an encoder unit 10. FIG.

FIG. 4 is a diagram showing a storage area designated by a third address in RAM 3.

FIG. 5 is a time chart for explaining an operation when reading an instruction from RAM 3.

FIG. 6 is a diagram for explaining another embodiment of the present invention, FIG. 6 (1) is a diagram showing the register configuration shown in FIG. 1, and FIG. 6 (2) is a diagram showing the present invention. It is a figure which shows the register structure in other embodiment.

FIG. 7 is a determination means 40 according to another embodiment of the present invention.
3 is a block diagram showing a specific configuration of FIG.

FIG. 8 is a diagram showing another register configuration example in another embodiment of the present invention, FIG. 8 (1) shows the register configuration AA shown in FIG. 1, and FIG. 8 (2) shows the register configuration AA. It is a figure which shows the register structure D with the same total number of bits.

FIG. 9 is a block diagram showing an electrical configuration of an encoder unit 10 according to still another embodiment of the present invention.

FIG. 10 is a block diagram showing a specific configuration of a first conventional technique.

[Explanation of symbols]

 1 CPU 2 ROM 3 RAM 5 address line 6 data line 7 read / write line 8 determination means 9 permission signal generation means 10 encoder unit 11 selector 21, 25 OR circuit 22 delay unit 23 decoder 24 AND circuit D1, D3 address signal R1 Rn register S1 to Sn comparator

Claims (10)

[Claims] 1. A plurality of instructions forming a program to be executed are stored in advance, and a plurality of predetermined addresses are set in a storage area in which each instruction is stored, and instructions for reading the instructions are given. Read-only first storage means for outputting the designated instruction when a read signal, an address signal designating a storage area in which the instruction to be read is stored, and a permission signal permitting the reading of the instruction are given. And a command to be executed instead of the specific command selected from a plurality of commands constituting the program to be executed is stored in advance, and in the storage area in which the command is stored,
An address different from the address of the first storage means is set, a read signal for instructing to read an instruction, an address signal for designating a memory area in which an instruction to be read is stored, and a permission signal for permitting the instruction to be read. Second storage means for outputting a designated instruction when is given, and a read signal for reading the instruction and an address signal for designating an address of the first storage means.
Alternatively, it is determined whether the instruction execution unit that executes the instruction read from the second storage unit and the address designated by the address signal from the instruction execution unit match the address of the storage area in which the specific instruction is stored. An address signal for specifying the address of the second storage means when the addresses coincide with each other, in response to the output of the determination means,
When the addresses do not match, the address signal from the instruction executing means is provided to the first and second storage means, and in response to the output of the judging means, when the addresses match, the second storage means is permitted. A program execution device, comprising: a permission signal generating unit that outputs a signal and outputs a permission signal to the first storage unit when the addresses do not match. 2. A plurality of instructions constituting a program to be executed are stored in advance, and a plurality of predetermined first addresses are set in a storage area in which the respective instructions are stored, and the instructions are read out. A read-only first output for outputting a designated instruction when a read signal for instructing, an address signal for designating a storage area in which an instruction to be read is stored, and a permission signal for permitting reading of the instruction are given. The storage means has a data storage area in which a plurality of second addresses different from the first address are respectively set, and the data storage area having one or more third addresses selected from the second addresses Read / write for instructing read / write of data, in which an instruction to be executed is stored in place of a specific instruction selected from the instructions constituting the above-mentioned program to be executed Read / write, which outputs / inputs the specified data when a read signal, an address signal that specifies a data storage area for reading / writing data, and a permission signal that permits reading / writing of data are given A second storage means which is free to output the read signal and an address signal designating an address of the first storage means to the first storage means to read the instruction, execute the read instruction, and execute the instruction And an instruction executing means for outputting the read / write signal and an address signal designating an address of the second storing means for reading / writing data from / into the second storing means as necessary, and the instruction executing means. Determining means for determining whether or not the address designated by the address signal from the same matches the address of the storage area in which the specific instruction is stored; Based on the output of the stage, when the judgment of the judgment means is affirmative, the address signal designating the third address is outputted to the second storage means, and when the judgment of the judgment means is negative, the instruction execution means. An address conversion unit for outputting the address signal from the second storage unit to the second storage unit, and an address designated by the address signal based on the address signal from the instruction execution unit and the output of the determination unit is the first address, and When the judgment of the judgment means is affirmative, the permission signal is outputted to the second storage means, and when the address designated by the address signal is the first address and when the judgment of the judgment means is negative, the first signal is outputted. And a permission signal generating means for outputting a permission signal to the second storage means when the permission signal is output to the storage means and the address designated by the address signal is the second address. Program executing apparatus according to claim and. 3. The determination means includes an address storage means for storing an address signal indicating an address of a storage area in which the specific instruction is stored, an address signal stored in the address storage means, and an instruction execution means. 3. The program execution device according to claim 2, further comprising: a detection unit that detects whether or not the address signal of FIG. 4. The address storage means is one or more registers for storing an address signal composed of a plurality of bits, and the detection means is provided corresponding to the register, and the address signal from the register and instruction execution are executed. 4. The program execution device according to claim 3, further comprising a comparison circuit for comparing the address signal from the means, and an OR operation circuit to which an output from the comparison circuit is given. 5. The address storage means divides an address signal composed of a plurality of bits into a predetermined number of high-order bits and remaining low-order bits, and divides each address signal having a high-order bit in common into groups. Address signals are stored in units, and each group is provided with a high-order bit register of 1 and low-order bit registers of the same number as the number of address signals belonging to the group, and the detection means includes a high-order bit register for each of the groups. 1 high-order bit comparison circuit for comparing the signal of 1 to the high-order bit of the address signal from the instruction execution means, and the same number of low-order bit registers as the number of low-order bit registers and the address signal from the instruction execution means. One or more lower bit comparison circuits for comparing lower bits and the same number of lower bit registers are provided. The present invention further comprises one or more AND circuits to which the output of each lower bit comparison circuit and the output of the higher bit comparison circuit are provided, and a first OR circuit to which the output of each AND circuit is provided. 4. The program execution device according to claim 3, further comprising a second logical sum circuit to which the output of the first logical sum circuit is given. 6. The permission signal generating means outputs a first signal based on the address signal from the instruction executing means when the address designated by the address signal is the first address, and outputs the second signal. And a decoding means for outputting the second signal, a logical product operation means for performing a logical product operation of the first signal and an inverted signal of the output of the judging means, and giving an operation result to the first storage means, 3. The program execution device according to claim 2, further comprising: a logical sum calculation unit that performs a logical sum calculation of the two signals and the output of the judgment unit and gives the calculation result to the second storage unit. 7. The program execution device according to claim 6, wherein the permission signal generation means includes a delay means for delaying the output of the judgment means for a predetermined period and giving the output to the logical sum operation means. 8. The address conversion means is responsive to the output of the address signal generating means for generating an address signal designating the third address, and the output of the determining means, and when the determination of the determining means is affirmative, the address converting means 3. The program executing device according to claim 2, further comprising switching means for outputting the address signal from the signal generating means and for outputting the address signal from the instruction executing means when the judgment of the judging means is negative. . 9. The determination means compares the address storage means for storing a plurality of address signals, the address signal from the instruction execution means, and the address signal stored in the address storage means, and matches them. The address signal generating means includes a detection means for detecting whether or not the upper-order address memory stores an address signal of a predetermined number of higher-order bits, and a residual lower-order bit of the remaining lower bits based on the comparison result in the detection means. 9. The program execution device according to claim 8, further comprising a lower address generation means for generating an address signal. 10. The program execution device according to claim 9, wherein the instruction execution unit reads / writes from / to the upper address memory.