JPH09153542A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable an even thickness trench structured element separating region to be formed regardless of width dimension by providing a trench in a semiconductor substrate to make a trench in a substrate for burying an oxide film in this trench to polish the surface of the trench by chemical mechanical polishing process. SOLUTION: After the formation of a wide trench in a silicon substrate 1, a silicon nitride film is selectively formed on the inside wall of the trench to form a thermal oxide film 7 as an oxidation-resistant film on the inner bottom in the central part of the trench. Next, oxide films 8 are buried in the trench to be polished by CMP process for the formation of an element separating resion. Through these procedures, the decrease in the film thickness on the central part of the wide element separating region can be avoided thereby enabling trench structure element isolation region in excellent flatness to be formed.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an element isolation region.

[0002]

2. Description of the Related Art Conventionally, LOCOS (Local Oxidation) has been used as a method for manufacturing element isolation of a semiconductor device.
of silicon) has been used. However, this selective oxidation method has a problem that a so-called bird's beak occurs in which the selective oxide film enters the element region, and the effective area of the element region is reduced. In addition, since the selective oxide film is formed to protrude above the element region surface to cause a step, in the process after the formation of the element isolation region, problems such as a decrease in lithography accuracy and wiring coverage failure, so-called step disconnection, occur. . For this reason, the element isolation structure of a semiconductor device for the purpose of high integration in recent years has shifted to a trench isolation structure which solves these problems.

As an example of a method of forming such a trench isolation structure, there is a method described in, for example, Japanese Patent Application Laid-Open No. 4-250650. FIG. 5 is a cross-sectional view showing the process. First, as shown in FIG. 5A, the surface of the silicon substrate 11 is thermally oxidized to form a pad oxide film 12, and a C oxide film is formed thereon.
CMP (Chemical Mechanical Polishing: Chemical)
(Mechanical Polish) stopper film 13 is formed. Then, the stopper film 13, the pad oxide film 12, and the silicon substrate 11 in the element isolation region are selectively etched to form a trench T. Next, thermal oxidation is performed to form a silicon oxide film 14 on the inner wall of the trench.

Then, as shown in FIG. 5B, a buried film 15 such as a silicon oxide film is deposited on the entire surface,
Then, CMP is performed as shown in FIG. 5C to remove the buried film 15 on the element region. CMP at this time is CMP
It is stopped by the stopper film 13 having a slow rate. Finally, as shown in FIG. 5D, the stopper film 1 on the element region is formed.
3. Remove the pad oxide film 12 to form an element isolation region.

In this method, the buried film 15 is polished by CMP. At this time, the buried film 15 on the wide trench region is polished in the same manner as the convex portion, although it is a concave portion. Therefore, when CMP is stopped by the stopper film 13, the embedded film 15 is considerably polished and becomes thin as shown in FIG. As described above, when the buried film 15 in the trench becomes thin, the element isolation characteristics are deteriorated. In particular, the capacitance between the silicon substrate 11 below the trench and the gate electrode or wiring on the trench isolation region increases, and the operating speed of the semiconductor device decreases.

As described above, several methods have been proposed to solve the problem that the buried oxide film in the wide trench becomes thin. As a first method, there is one described in JP-A-63-281441. In this method, as shown in FIG. 7, first, as shown in FIG. 7A, a dense silicon oxide film 22 is formed on the entire surface of a silicon substrate 21 by the CVD method, and the silicon oxide film 22 on the element isolation region is formed. Oxide film 22, silicon substrate 21
Is selectively etched to form a trench T. Next, ECR (Electron Cyclotron)
By a CVD method using Resonance, a dense silicon oxide film 23 is formed in a trench step portion and a dense silicon oxide film 23 is formed in a flat portion.

Next, as shown in FIG. 7B, wet etching is performed on the silicon oxide film 23. The wet etching rate is 30 times higher for a dense film than for a dense film.
~ 40 times faster. Therefore, the dense silicon oxide film 232
Selectively removed. By this wet etching, first, the coarse / dense film at the trench step portion is removed. Then, the coarse and dense silicon oxide film 22 is side-etched from the side wall of the removed trench step. Along with this, the dense silicon oxide film 23 is lifted off and removed at the same time as the dense silicon oxide film 22. As a result, due to this wet etching, the silicon oxide film 23 does not exist in the narrow trench, and the dense silicon oxide film 23 remains only in the portion excluding the side wall of the wide trench.

Next, as shown in FIG. 7C, after a silicon oxide film 24 is formed on the surface by thermal oxidation, a silicon oxide film 25 is deposited by a CVD method. Silicon oxide film 2
Prior to the growth of 5, the surface is in a state where only narrow trenches are present. Therefore, the surface of silicon oxide film 25 after growth is substantially flat. Finally, FIG.
As shown in (d), etching is performed until the surface of the element region is exposed to form an element isolation region. in this way,
Since the surface after the growth of the silicon oxide film 25 is substantially flat, if the surface is exposed by etching, a uniformly buried trench can be formed regardless of the separation width.

A second method is disclosed in Japanese Patent Laid-Open No. 2-545.
FIGS. 8 and 9 show a process flow of the technology described in Japanese Patent Publication No. 62-62. In this method, first, as shown in FIG. 8A, a silicon substrate 31 is thermally oxidized to form a thermal oxide film 32. Next, a silicon nitride film 33 and a silicon oxide film 34 are sequentially formed by a CVD method. Then, the silicon oxide film 34, the silicon nitride film 33, the thermal oxide film 32 on the element isolation region,
Then, the trench T is formed by selectively etching the silicon substrate 31. Next, as shown in FIG. 8B, after performing thermal oxidation, anisotropic etching is performed to leave the thermal oxide film 35 only on the side walls of the trench.

Next, as shown in FIG. 8C, oxygen ions are implanted into the bottom of the trench T using the silicon oxide film 34 as a mask to form a buried silicon oxide film layer 36 in the substrate 31 at the bottom of the trench. Next, as shown in FIG. 8D, a silicon layer 37 is grown from the bottom of the trench to the surface of the element region by a selective epitaxial growth method. Moreover,
As shown in FIG. 9A, oxygen ions are implanted again to form a silicon oxide film layer 38 connected to the buried silicon oxide film layer 36. Then, as shown in FIG. 9B, after removing the silicon oxide film 34, thermal oxidation is performed using the silicon nitride film 33 as an oxidation-resistant mask. By this oxidation, the silicon layer 39 on the surface which has not been converted into the silicon oxide film by the second oxygen ion implantation is used as the silicon oxide film and integrated with the silicon oxide film 38.

Finally, as shown in FIG. 9C, the silicon nitride film 33 and the thermal oxide film 32 are removed to form an element isolation region. In this method, silicon in an implanted region is converted into a silicon oxide film by oxygen ion implantation to form an element isolation region. Therefore, a trench isolation region having a uniform thickness can be formed irrespective of the isolation width.

[0012]

As described above, it is possible to manufacture an element isolation structure in which the film thickness is not reduced even in a wide trench isolation region. The method of (1) requires a step of removing a dense silicon oxide film on the element region by wet etching by wet etching, and when the element region width is narrow, it can be easily removed by lift-off, but is actually provided in the semiconductor device. It is very difficult to lift off a dense silicon oxide film in an element region having a width of several 100 μm. Therefore, it is difficult to apply the first method to a semiconductor device including such an extremely wide element region.

On the other hand, in the second method shown in FIGS. 8 and 9, silicon is converted to a silicon oxide film by oxygen ion implantation to form an element isolation region, but silicon is converted to a silicon oxide film. To make it work, 1E18ion
/ Cm ² of oxygen ions is required. Since a considerable amount of crystal defects are generated in silicon implanted with this amount, the crystal defects remain without being recovered even if annealing is performed after the implantation. Therefore, the crystal defects cause deterioration of the characteristics of the semiconductor device, such as a leak at a PN junction facing the trench isolation region.

An object of the present invention is to be able to suitably manufacture a wide element isolation region without being affected by the dimensions of an element region or an element isolation region in a semiconductor device and without deteriorating the characteristics of the semiconductor device. To provide a method for manufacturing a semiconductor device.

[0015]

According to the manufacturing method of the present invention, a step of forming a trench on the surface of an element isolation region of a semiconductor substrate and a thermal oxide film is formed on the central portion of the widest trench. A step of forming a buried oxide film over the entire surface of the semiconductor substrate so as to fill the trench,
And a step of polishing the buried oxide film up to a substantially surface height position of the semiconductor substrate.

Here, as a method of forming the thermal oxide film, a nitride film is selectively formed on the inner side surface of the wide trench, and the nitride film is used as an oxidation resistant film to form the thermal oxide film in the central portion of the trench. The method of doing can be adopted. Alternatively, in the wide element isolation region, trenches are formed on the surfaces of both ends thereof, and the trench is filled with a mask to etch the semiconductor substrate at the center of the wide element isolation region to a required depth to form a shallow trench. It is possible to employ a method in which the thermal oxide film is formed on the surface of the shallow trench after forming the trench and burying the nitride film in the trench.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings. 1 and 2 are process flow cross-sectional views of a first embodiment of the present invention. First, as shown in FIG. 1 (a), the surface of the silicon substrate 1 is thermally oxidized to form 1
A thin silicon oxide film 2 of 0 nm is formed. Also, CV
The silicon nitride film 3 and the silicon oxide film 4 are sequentially formed by the D method to have a thickness of 50 nm and 50 nm. Next, a photoresist mask (not shown) is formed in the element region by photolithography, and the silicon oxide film 4, the silicon nitride film 3, the silicon oxide film 2, and the silicon substrate 1 in the element isolation region are sequentially dry-etched to obtain a width. Narrow trench Ta
And a wide trench Tb is formed. Each trench is formed in the silicon substrate 1 at a depth of 300 nm. afterwards,
Strip the photoresist mask.

Next, as shown in FIG. 1B, thermal oxidation is performed using the silicon nitride film 3 as an oxidation resistant mask to form a 40 nm silicon oxide film 5 on the inner walls of the trenches Ta and Tb. Further, a silicon nitride film 6 is
After the formation, anisotropic etching back by dry etching is performed, so that the silicon nitride film 6 is not removed in the narrow trench Ta, but the wide trench T
In step b, a sidewall of the silicon nitride film 6 is formed on the side wall of the trench. Next, as shown in FIG. 1C, high-temperature thermal oxidation is performed using the silicon nitride films 3 and 6 as an oxidation-resistant mask to form a thick 780-nm thick silicon oxide film 7 at the center of the bottom of the wide trench Tb. At this time, the oxidation conditions are set so that the height of the surface of the silicon oxide film 7 is the same as the height of the silicon oxide film 4 in the element region.

Subsequently, as shown in FIG. 2A, the sidewall of the silicon nitride film 6 is removed by wet etching, and then the silicon oxide film 8 is removed by 800 nm by CVD.
m to cover the trenches Ta and Tb. Before the formation of the silicon oxide film 8, the silicon oxide film 7 formed by thermal oxidation is located at the center of the wide element isolation region, and only the narrow recess exists on the surface. After the formation, the surface is substantially flat. Then, annealing is performed at a temperature of 900 ° C. for 30 minutes in a nitrogen atmosphere. This annealing is performed to make the silicon oxide film 8 dense.

Thereafter, as shown in FIG. 2B, the silicon oxide film 8 is subjected to CMP. The CMP is stopped at the silicon nitride film 3 having a low CMP rate. Then, as shown in FIG. 2C, wet etching is performed using the silicon nitride film 3 as a mask, and the silicon oxide films 7 and 8 on the trenches Ta and Tb are retracted to the level of the surface of the silicon oxide film 2. Finally, the silicon nitride film 3 and the silicon oxide film 2 are removed to form an element isolation region.

As described above, in the first embodiment of the present invention, even if the CMP method is used, the polishing of the central portion of the wide element isolation region is not promoted and the surface is flattened. To be polished. That is, in the CMP method shown in FIG.
Although the buried film 12 on the wide trench region was a concave portion, it was polished in the same manner as the convex portion, and the buried film 12 in the trench was thinned. This is because the polishing pad has elasticity, the polishing pad is deformed according to a certain degree of unevenness, and the polishing pad comes into contact with the bottom of the concave portion.
Thus, the surface shape before CMP is transferred to some extent after CMP. As a result of investigating the transfer, in the case of a recess having a width of 500 μm or more, the C
It becomes concave like before MP. On the other hand, in the present invention, since the thermal oxide film 7 of silicon is formed at the center of the trench, the surface before the CMP is almost flat. Therefore, the buried film in the trench does not become thin.

A second embodiment of the present invention will be described. FIG.
4 and FIG. 4 are process flow cross-sectional views thereof, in which parts equivalent to those in the first embodiment are designated by the same reference numerals. First, FIG.
As shown in (a), a thin silicon oxide film 2 of 10 nm is formed on the surface of the silicon substrate 1 by thermal oxidation. Next, C
A silicon nitride film 3 and a silicon oxide film 4 are sequentially formed to a thickness of 50 nm and 50 nm by the VD method. Then, a photoresist mask (not shown) is formed by the photolithography method, and the silicon oxide film 4, the silicon nitride film 3, the silicon oxide film 2, and the silicon substrate 1 in the region not covered with the photoresist mask are sequentially dry-etched. Then, a trench Ta having a narrow width is formed. At this time, the photoresist mask has both ends of the element isolation region with a width of 0.7 μm or more (the distance from the edge of the element isolation region is 0.3.
The pattern is formed such that a region within 5 μm) and a narrow element isolation region portion of 0.7 μm or less are opened. The trench is formed to a depth of 300 nm from the silicon substrate surface.

Next, as shown in FIG. 3B, after the photoresist mask is removed, a photoresist mask 9 is formed again by photolithography. The photoresist mask 9 is formed in a pattern that opens at the center of the wide element isolation region (the region separated from the edge of the element isolation region by 0.35 μm or more). And
The silicon oxide film 4, the silicon nitride film 3, the silicon oxide film 2, and the silicon substrate 1 in the region not covered by the photoresist mask 9 are sequentially dry-etched. By this etching, a silicon layer having a thickness of 105 nm is removed from the surface, a relatively shallow trench Tc is formed here, and a narrow trench Ta on both sides thereof is formed as a wide trench Tb.

Next, as shown in FIG. 3C, after the photoresist mask 9 is peeled off, thermal oxidation is performed using the silicon nitride film 3 as an oxidation resistant mask to expose the exposed trenches Ta and T.
40 nm silicon oxide film 5 on the surface of the silicon substrate
To form Next, a silicon nitride film 6 is deposited on the entire surface for 200 n.
After the formation of m, anisotropic etching back by dry etching is performed to fill the trench with the silicon nitride film 6. Next, as shown in FIG.
High-temperature thermal oxidation is performed using the oxidation-resistant mask 6 to form a 430-nm thick silicon oxide film 7 on the surface of the shallow trench Tc. At this time, the oxidation conditions are set so that the height of the surface of the silicon oxide film 7 is the same as the height of the silicon oxide film 4 in the element region.

Next, as shown in FIG. 4B, after the silicon nitride film 6 filling the trench is removed by wet etching, a silicon oxide film 8 is formed to a thickness of 800 nm by the CVD method. Before the formation of the silicon oxide film 8, the silicon oxide film 7 formed by thermal oxidation is located at the center of the wide element isolation region, and only a narrow recess exists on the surface. Therefore, the surface after forming the thick silicon oxide film 8 is substantially flat. Next, FIG.
As shown in (c), annealing is performed in a nitrogen atmosphere at a temperature of 900 ° C. for 30 minutes. This annealing is performed by the silicon oxide film 8.
Is performed in order to densify. Then, CMP is performed on the silicon oxide film 8. This CMP is stopped at the silicon nitride film 3 having a low CMP rate. Then, FIG.
As shown in FIG. 3D, wet etching is performed using the silicon nitride film 3 as a mask to form a silicon oxide film 7 on the trench.
8 is retracted to the level of the silicon oxide film 2 surface. Finally, the silicon nitride film 3 and the silicon oxide film 2 are removed by wet etching to form element isolation regions.

Also in the second embodiment, since the thermal oxide film 7 of the shallow trench Tc exists in the central portion of the element isolation region constituted by the wide trench Tb, CM
The surface of the element isolation region before P is in a substantially flat state. Therefore, unlike the method of FIG. 5, the shape before the CMP is transferred and the buried film in the trench is not thinned. Further, in the second embodiment, the thermal oxide film 7 of silicon formed in the central portion of the trench is shallow in the depth direction of the silicon substrate and its thickness is formed thinner than that of the first embodiment. Generation of crystal defects due to stress during thermal oxidation can be suppressed.

[0027]

As described above, according to the present invention, the trench is formed on the surface of the element isolation region of the semiconductor substrate, and the thermal oxide film is formed at the center of the wide trench among the trenches. After forming a buried oxide film so as to fill the trench, the buried oxide film is polished to a substantially surface height position of the semiconductor substrate to obtain a trench structure having a uniform thickness regardless of the width dimension of the element isolation region. The element isolation region can be formed. Therefore, in the present invention, it is not necessary to use a lift-off technique, and it is not necessary to perform a very difficult operation of lifting off a wide area. Also, there is no need to use a process for converting silicon into a silicon oxide film by oxygen ion implantation, and there is no problem of junction leakage due to implantation defects.

[Brief description of the drawings]

FIG. 1 is a first cross-sectional view showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a second sectional view showing the first embodiment of the present invention in the order of steps.

FIG. 3 is a first sectional view showing the second embodiment of the present invention in the order of steps.

FIG. 4 is a second sectional view showing the second embodiment of the present invention in process order.

FIG. 5 is a sectional view showing a conventional manufacturing method in the order of steps.

FIG. 6 is a cross-sectional view for describing a problem in the manufacturing method of FIG. 5;

FIG. 7 is a cross-sectional view showing a conventional improved first method in the order of steps.

FIG. 8 is a first cross-sectional view showing a second improved conventional manufacturing method in the order of steps;

FIG. 9 is a second sectional view showing the second improved conventional manufacturing method in the order of steps;

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 silicon oxide film 3 silicon nitride film 4 silicon oxide film 5 silicon oxide film 6 silicon nitride film 7 silicon oxide film Ta, Tb, Tc trench

Claims (7)

[Claims] 1. A step of forming a trench in a surface of an element isolation region of a semiconductor substrate, a step of forming a thermal oxide film in a central portion of a wide trench among the trenches, and a step of filling the trench so as to fill the trench. A method of manufacturing a semiconductor device, comprising: a step of forming an oxide film on the entire surface of the semiconductor substrate; and a step of polishing the embedded oxide film to a substantially surface height position of the semiconductor substrate. 2. A method of manufacturing a semiconductor device according to claim 1, wherein a nitride film is selectively formed on the inner side surface of the wide trench, and the thermal oxidation film is formed in the center of the trench by using this nitride film as an oxidation resistant film. . 3. A nitride film is formed on the entire surface including the trench,
3. The method of manufacturing a semiconductor device according to claim 2, wherein the nitride film is anisotropically etched to leave the nitride film on the inner surface of the trench. 4. In the wide element isolation region, trenches are formed on the surfaces of both ends thereof, and the trench is filled with a mask to etch the semiconductor substrate at the center of the wide element isolation region to a required depth. To form a shallow trench,
3. The method of manufacturing a semiconductor device according to claim 2, wherein a nitride film is buried in the trench, and then a thermal oxide film is formed on the surface of the shallow trench. 5. The method of manufacturing a semiconductor device according to claim 4, wherein a nitride film is formed in a region including the trench and the shallow trench, and the nitride film is anisotropically etched to fill the nitride film only in the trench. 6. A polishing method is a chemical mechanical polishing method (C
6. The method for manufacturing a semiconductor device according to claim 1, wherein the method is the MP method). 7. The method of manufacturing a semiconductor device according to claim 1, wherein a thermal oxide film is formed in a central portion of an element isolation formation region having a width of 0.4 μm or more.