JPH09149380A - Memory strucutre for reformatting and storing display data in standard tv system and hdtv system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data reformatter/frame memory processing the picture data of normal TV and HDTV systems. SOLUTION: The data reformatter/frame memory 112 is used together with a display device 124 displaying digital data and a display controller 132 adjusting data transfer between the data reformatter/frame memory 112 and the display device 124. A data reformatter adds at least one reformatter memory plane and the memory plane adds an input has, the mxn array of a memory cell for executing communication with the input bus and an m-bit width output bus. Memory cell array receives an m-number n-bit width output data language, stores it and outputs an n-number m-bit width output data language. The respective words of the m-bit width output data language are constituted of jone bit of the respective words in the m-number n-bit width input data language.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to display systems, and more particularly to image data processing circuits used in digital television display systems.

[0002]

Display systems such as televisions display a fully moving video image as a series of still frames. Each frame of an image consists of a two-dimensional array of pixels, known as pixels, arranged in orthogonal rows and columns.
The image information is transmitted one line at a time from top to bottom in raster scan format. Pixel information for each row is transmitted from left to right. The standard television system in the United States has 480 lines, each line having a resolution of about 572 pixels. The video graphics adapter (VGA) standard defines an image consisting of 480 rows of 640 pixels. The horizontal NTSC television standard defines an image having a width of 853 pixels and a height of 480 lines. Although there is no globally accepted standard for high definition television, some formats are designed to display up to 2048 columns and 1152 rows.

Since standard television broadcasts transmit analog signals, each pixel in a row is not transmitted in discrete units, but an entire row is transmitted as an analog signal from left to right. An analog display device, such as a cathode ray tube (CRT), receives raster scan image data and projects one row of image data at a time in real time on a display screen as received. However, many digital display systems require data to display the entire screen at one time. This requires the data to be stored as received until all the data on a given screen can be displayed. One aspect of the present invention is an effective data storage means.

Up to this point, the description of image data transfer refers to image data of one pixel as an indivisible unit. However, digital display systems require image data composed of one or more weighted binary bits. Digital systems that use more than one bit of image data are usually
Send all bits in parallel for a given pixel. For example, a three color display using 8 bits of data for each color sends one word 24 bits wide for each pixel. 1 digital display pixel
If only one bit can be displayed at a time, each of the 24 bits must be displayed in order to produce a pixel of the desired brightness level and color. Commonly assigned US Pat. No. 5,278,562, "DMD Architecture and Timing for use in a Pulse".
-Width Modulated display System)) to generate the required grayscale 1
One method is pulse width modulation.

Using the method taught in the above-referenced patents and assuming an 8-bit monochrome system, an 8-bit image is displayed as a series of eight 1-bit images or 1 "bitplane". Each bit plane is displayed for a time that is directly related to its bit significance. For example, a bit plane composed of the most significant bits of each word of a data word representing a pixel is extracted and displayed for a certain time. A second bitplane consisting of the second most significant bit of each data word is extracted and displayed for half the length of the first time. This process continues until each bit of the data word has been displayed.

Image data is received as a serial stream of pixels, where each pixel is composed of parallel data bits, and each bit plane is a serial stream of bit planes composed of one data bit for each pixel. Is displayed. What is desired is an effective means of converting from a bit-parallel and pixel-serial format to a pixel-parallel and bit-serial format, which is one aspect of the present invention.

[0007]

DETAILED DESCRIPTION OF THE INVENTION A data reformatter / frame memory is disclosed which provides an effective means for orthogonal reordering of data pixels. The data reformatter enables the first stream of data words to be transformed into a second stream of data words, where each word of the second data word has one bit of each word of the first data word. include. The disclosed frame memory is used until the data word is needed for display.
Store the second data word stream.

According to one embodiment, the data reformatter includes at least one reformatter memory plane, which reformatter memory plane includes:
An m × n array of memory cells is included that receives and stores m n-bit wide input data words from the input bus and outputs n m-bit wide output data words to the output data bus. Here, an m-bit wide output data word is composed of 1 bit of each word of m n-bit wide input data words.

According to another embodiment of the disclosed invention, a display system comprises a data reformatter, a display device, and a controller for coordinating the operation of the data reformatter and the display device. The data reformatter consists of an m × n array of memory cells that receives and stores m n-bit wide input data words and outputs n m-bit wide output data words. Here, an m-bit wide output data word is composed of 1 bit of each word of m n-bit wide input data words.

The disclosed data reformatter / frame memory enables the processing of video data, where m n-bit wide input data words are written to the reformatter memory, each word of the input data word. This is a process in which n m-bit wide output data words each consisting of 1 bit of each word are read from the reformatter memory.
The n m-bit wide output data words are typically stored in the frame memory until the data is displayed.

[0011]

For a better understanding of the present invention and its advantages, reference is made to the following description in conjunction with the accompanying drawings.

The eight waveforms 20 shown in FIG. 1 are a series of 8-bit binary image data words for one row of 16 pixels. The diagram below waveform 20 in FIG. 1 is a hexadecimal representation of the binary value of the image data for each pixel of 16 pixels. If clarity is required, the letter "h" will be appended to the hexadecimal number in this disclosure. The 16-pixel image data is transmitted as 16 8-bit data word strings shown below the waveform in FIG. As discussed above, the data in a given bit order for all pixels in a row is input to the digital display simultaneously. For example, the image data shown in FIG. 1 has a series of 16 8-bit words, F0h, E1h, D2h, C3h, B4.
h, A5h, 96h, 87h, 78h, 69h, 5A
h, 4Bh, 3Ch, 2Dh, 1Eh, 0Fh, but a series of eight 16-bit words, FF00h,
F0F0h, 3333h, 5555h, 00FFh, 0
It is loaded into the display device as F0Fh, 3333h, 5555h. The function performed for this regrouping is called orthogonal reordering. One function of the reformatter memory disclosed herein is to receive a stream of data from a video source in one format and reorder the data bits so that they are output to the display device in the required order. By doing so, orthogonal reordering is performed.

One way to accomplish this reordering is shown in FIG. When the data for the 16 pixels of a row is received by reformatter 40, each word is written to a separate register. In FIG. 2, the data word for pixel 1 is written to register 42 and the second word is written to register 4
4 and the 16th word is written to register 48.
Once all the words have been written to the register, the data is read from the reformatter 40 and stored in the frame memory. FIG. 2 shows the multiplexer 56 used to select the bits output to the frame memory from each of the 16 registers. If the outputs of the registers were individually enabled, the outputs of each register may be interconnected and multiplexer 56 would be unnecessary. FIG. 2 shows only the data reformatting mechanism, and there are other circuits that can perform the same function. For example, rather than using a register and multiplexer 56, a standard RAM cell using a quadrature read write enable signal may be used.

FIG. 3 shows a schematic diagram of another embodiment of the data reformatter circuit 59. In the example shown in FIG. 3, each data word is 24 bits wide and contains 8 bits of luminance data for each of the three colors. The reformatter circuit 59 shown in FIG. 3 is designed to reformat the data for a horizontally long NTSC image. Commonly assigned and commonly assigned US patent application 08 / , "A New Digital Micromirror Architecture f used for landscape displays
It is believed that a modulator having a horizontal resolution of 864 pixels can be used to display a horizontally long NTSC image of 853 pixels, as described in "Or Wide Display Applications)". Since 864 is a multiple of 16, the digital processing circuit can be simplified by adding an extra 11 pixels. The extra 11 pixels in each row can be used to center the displayed image as well as the front image projection.
It can be used to simplify the circuitry needed to change from n) to rear image projection.
The reformatter shown in FIG. 3 holds two rows of image data of 864 (32 × 27) pixels. The data for one row of pixels has been written to one half of the reformatter 61 and the data for the other row has been read from the other half of the reformatter 63. Each half of the data reformatters 61, 63 has 32 individual memory planes 60, 62,
64, 66, each memory plane reformatting a 27 pixel video data word. One data word for each pixel in a row is a memory plane 60, 6
Written once in 2, 64, 66. The data from pixel 1 to pixel 27 is written to memory plane 60. The plane 62 has pixels 28 to pixels 54.
Up to the pixel 83.
It holds the data from 8 to pixel 864. Writing one row of data to the first half of the reformatter 61,
Switch 68 sends the second row of data to the second half of reformatter 63 and switch 70 allows the data of the first row to be read from the first half of reformatter 61.

The data is sent from the reformatter 59 to 86.
It is read in 24 words that are 4 bits wide. Each word contains 27 bits of each of the 32 memory planes of the reformatter memory and consists of the same weighted bits of each pixel of the row. Reformatter 61, 6
32 27-bit registers 7 at the output of each half of 3
The 2,74 array latches the reformatted output data. When all of the image data for one weight value has been read in one read cycle, switch 76 is incremented to select the next bit value to output. Since the data is written to the reformatter 59 in 24 bit words and read from the reformatter 59 in 864 bit words, 864 write cycles are required to fill the reformatter, but the reformatter is emptied. Only 24 read cycles are required to do so.

One feature of the disclosed data reformatter 59 is the ability to pass data through the reformatter 59 without reformatting. This feature simplifies fault isolation between the data reformatter 59 and the frame store memory used to store the reformatted output data. 27 input buses for data reformatting memory planes 60, 62, 64, 66
It is a bit width. When the data reformatter 59 is in reformatting mode, only 24-bit words are written to the data reformatter 59 and the remaining three buses are unused. When the data reformatter 59 is in test mode, a 27-bit word is written to the data reformatter 59. In the test mode, the 27 input lines are connected to the 27 output lines of each memory plane 60, 62, 64, 66, and the test data is first stored in the memory plane 6.
It is written directly to the output register array 72, 74 without being stored by 0, 62, 64, 66. In reformatting mode, 32 27 of arrays 72, 74
All of the bit output registers are latched at the same time. In test mode, the registers can be individually latched so that each register can be written with its own data.

The size of the data words and reformatter memory used in the above description have been chosen for illustration purposes. For example, one embodiment uses 16 instead of the 32 memory planes 60, 62, 64, 66 described above.
Only one memory plane 60, 62, 64, 66 can be used. In this case, the capacity of each half of the reformatters 61 and 63 is reduced from one row of data to half row of data.
The output word of the reformatter 59 is 432 bits wide,
It will contain 1 bit of data for half a row of pixels. In another embodiment, a data reformatter 59 designed for use in a VGA compatible display system has memory planes 60, 62, 6 in which each memory plane holds 32 24-bit words.
Reformatter 61, 63 including only 4 and 66
Each half of the can be enabled to contain all the data for half the row of 640 pixels.

Another feature of the disclosed reformatter 59 is the ability of the reformatter 59 to invert the bit planes so that the image can be projected forward or backward. The only slight change that must occur to invert a bit plane using the disclosed reformatter 59 is a memory plane 60,
Only the order of filling 62, 64, 66. For example,
In the front projection display system, if data is written in the reformatter 59 in the order from the first position of the memory plane 60 to the last position of the memory plane 66, the last position of the memory plane 66 moves to the memory plane 60. Memory planes 60, 62, 6 to first position
The system can be converted to a rear projection display by simply satisfying 4, 66. No other operation is changed, including reading the data from memory.

FIG. 4 shows the memory plane 60 shown in FIG.
Representative memory plane 80 similar to 62, 64, 66
The schematic diagram of is shown. Memory plane 80 is line 6
Holds a 4-bit word for each pixel of the pixel.
The data word for the first pixel is the input data bus 8
Via 6 to four memory cells 84 in the first row 82 of memory plane 80, with the least significant bit at signal 88 and the most significant bit at signal 90. A memory write cycle for memory cell 84 is enabled by row enable signal 92. The data for the second pixel is loaded into the memory cells of the second row 94 using the row enable signal 96. When the third to sixth image data words are written in the memory plane 80, the data is embedded in all the memory cells 84 of the memory plane 80.

The data is 1 from the array of memory cells 84.
One column is read at a time. For example, the column output enable signal 98 enables the memory cell column 100 to drive the data output bus 102. The memory cell column 100 sends the least significant bit of the pixel 1 data word on line 104 and the least significant bit of the pixel 6 data word on line 106.
The image data output by the reformatter 80 is
The data can be stored in the frame memory until it needs to be displayed. Prior art data reformatters have converted the reformatted data from parallel to serial to prevent too many connections between the data reformatter and the frame memory. This parallel to serial conversion
ion) was usually implemented by an array of parallel input shift registers at the output of the data reformatter. The present invention contemplates incorporating the data reformatter 59 and frame memory into one integrated circuit,
The shift register array is unnecessary.

FIG. 5 is a block diagram of the reformatter / frame memory 112 according to the present invention. Data representing a row of pixels is input to half of the reformatter 61 via input bus 114. When the first half of the reformatter 61 is filled with data, the switches 68, 7
The position of 0 has changed and the data in the next row is reformatter 6
Reformatted first written in second half of 3
The data for a row is read from the first half of the reformatter 61 into the frame memory 122 and stored in the frame memory 122 until the data is needed for display.

The interface between frame memory 122 and digital display device 124 includes two shift register arrays to reduce the number of connections. A first shift register array 126 is built on the reformatter / frame memory 112 integrated circuit,
According to one embodiment of the present invention, 27 32-bit parallel-input serial-shift registers.
output shift registers). One row of data on the display is stored in the first shift register array 12
6 and is shifted out into the form of 32 27-bit words. Each word of the 27-bit data word consists of one bit of every 32nd pixel in each row. The digital display device 124 has 32 2
It includes a second input shift register array that receives the 7-bit data word and performs a serial to parallel conversion of the data to regenerate the 864-bit wide data word.

The controller 132 shown in FIG. 5 supplies address data, timing signals, and switch control signals to the reformatter / frame memory 112 and the display device 124. These data and signals are passed through the reformatter / frame memory 112. Necessary to coordinate the transfer of data to the display device 124.

FIGS. 6, 7, 8 and 9 are block diagrams showing the reformatter / frame memory and digital display device in four different digital television systems. FIG. 6 illustrates the use of two reformatter / frame memories 134, each reformatter / frame memory storing data for half a row of pixels. Each reformatter / frame memory 134 includes 27 16-pixels that allow a row of pixel data to be read from the frame memory in 16 words.
It contains an array of bit shift registers.

The display system of FIG. 7 alternates between two reformatter / frame memories as if playing ping-pong. In FIG. 7, each reformatter / frame memory 144 is used to store all one frame and output one frame while another reformatter / frame memory 144 is being written. In this case, the size of the reformatter / frame memory is as shown in FIG.
For the same size as described above.

FIG. 8 shows four reformatters / reformatters for reformatting and storing one frame of video data.
It indicates that the frame memory 140 is used. In FIG. 8, each reformatter / frame memory 140
Stores video data for each quarter row. Each quarter line of data is stored in the reformatter / frame memory 14
16 32-bit words are transferred between 0 and the digital display device 142. The digital display device 142 receives the parallel 32-bit words and converts them into 2048-bit single words using the shift register technique described above. Reformatter / frame memory 1
40 individually reformats the left, center left, center right, right quarters of each row.

FIG. 9 shows a digital display device 14
6 shows two separate data paths are used. One reformatter / frame memory 14
8 is the first data path 150 (1 to 24 in this example).
(Line 0) is used to load the data in half of the digital display device. The second reformatter / frame memory 154 includes a data path 156 (lines 241 through 4).
80) is used to load the other half of the digital display device with data.

Although the above example refers to a display device as a digital display, it should be understood that digital image data can be converted to analog image data and displayed on an analog display device.

Thus, a particular method for reformatting and storing digital image data and a particular embodiment of an apparatus therefor have been disclosed in this regard, and are set forth in the following claims. Except that
These particular references are not intended to be considered as limiting the scope of the invention. Moreover, since the present invention has been described in conjunction with specific embodiments of the invention, further modifications are themselves to those skilled in the art, and all modifications that come within the scope of the appended claims are covered. Intended to be.

With respect to the above description, the following items are further disclosed. (1) At least one reformatter including an input bus, an array of memory cells composed of m rows and n memory cells and communicating with the input bus, and an m-bit wide output bus communicating with the memory array. A data reformatter for a video display system, comprising a memory plane, wherein the memory cell array receives and stores m n-bit wide input data words from the input bus, n
A plurality of m-bit wide output data words are output to the output data bus, the m-bit wide output data words being composed of one bit of each word of the m n-bit wide input data words. A data reformatter that does.

(2) The data reformatter of claim 1, further comprising at least one frame memory in communication with the reformatter for storing the n m-bit output data words. Reformatter.

(3) The data reformatter according to item 2, wherein at least one of communicating with the frame memory, receiving parallel data from the frame memory, and performing parallel / serial conversion on the parallel data. A data reformatter comprising a shift register.

(4) The data reformatter according to the second aspect, wherein the input bus selectively communicates with the frame memory.

(5) The data reformatter of claim 1, further comprising a second said at least one memory plane, said first mentioned memory plane receiving said input data word from said input bus. , A second memory plane outputs the output data word to the output bus.

(6) The data reformatter according to the first aspect, wherein the input data word includes n data bits representing one pixel of an image.

(7) The data reformatter according to the first aspect, wherein the at least one reformatter memory plane further includes a test data path electrically connecting the input bus and the output bus. A characteristic data reformatter.

(8) m m-bit input data words are written to the reformatter memory and from the reformatter memory, n m-bit output data consisting of 1 bit of each word of the input data words. A method of processing video data, comprising: reading a word, writing the output data word to a frame memory, and reading the output data word from the frame memory.

(9) The method according to the eighth item, further comprising a step of converting the video data read from the frame memory from a parallel format to a serial format.

(10) The method of claim 8, wherein the step of reading n m-bit output data words reads n m-bit output data words from the reformatter memory and outputs the output data. A word is made up of one bit of each word of the input data word, the most significant bit of the output data word from the first input data word written to the reformatter memory, and the least significant bit of the output data word. The method is characterized in that the bits are from the last input data word written to the reformatter memory.

(11) The method of claim 8, wherein the step of reading n m-bit output data words reads the n m-bit output data words from the reformatter memory and outputs the output data. A word is made up of one bit of each word of the input data word, the most significant bit of the output data word from the last input data word written to the reformatter memory, and the least significant bit of the output data word. The method is characterized in that the bits are from the first said input data word written to said reformatter memory.

(12) A data reformatter comprising a memory cell array configured as m rows and n memory cells, said memory cell array receiving and storing m n bit wide input data words, outputting n m-bit wide output data words, said m-bit wide output data word comprising a data reformatter comprising one bit of each word of the m n-bit wide input data words, said output data word A display system, comprising: a display device for receiving the data; and a controller for adjusting the operations of the data reformatter and the display device.

(13) A data reformatter / frame memory 112 that effectively reorders the flow of digital data. Generally, the disclosed data reformatter / frame memory 112 is used in conjunction with a display device 124 for displaying digital data and a display controller 132 for coordinating data transfer between the data reformatter / frame memory 112 and the display device 124. According to one embodiment, the data reformatter of the video display system has at least one
Contains one reformatter memory plane. The memory plane includes an input bus, an m × n array of memory cells in communication with the input bus, and an m-bit wide output bus. The memory cell array receives and stores m n-bit wide input data words and outputs n m-bit wide output data words. Each word of the m-bit wide output data word consists of 1 bit of each word of the m n-bit wide input data words.

[Brief description of the drawings]

FIG. 1 is a waveform diagram showing 8-bit image data for each pixel of 16 pixels.

FIG. 2 is a schematic diagram of an embodiment of a reformatter circuit according to the present invention.

FIG. 3 is a block diagram of one embodiment of a reformatter circuit according to the present invention.

FIG. 4 is a schematic diagram of an embodiment of a reformatter function according to the present invention.

FIG. 5 is a block diagram of a reformatter / frame memory disclosed in accordance with one embodiment of the present invention.

FIG. 6 is a block diagram of one embodiment of a display system including two reformatter / frame memories according to the present invention.

FIG. 7 is a block diagram of one embodiment of a display system including two reformatter / frame memories according to the present invention.

FIG. 8 is a block diagram of one embodiment of a display system including four reformatter / frame memories according to the present invention.

FIG. 9 is a block diagram of one embodiment of a display system including two reformatter / frame memories according to the present invention.

[Explanation of symbols]

20 8-bit image data word waveform 40 reformatter 42, 44, 46, 48 register 56 multiplexer 59 data reformatter 60, 62, 64, 66, 80 memory plane 68, 70, 76 switch 61, 63 reformatter 72, 74 27-bit shift register array 82 First row memory cell 84 Memory cell 86 Input data bus 88 Least significant bit signal 90 Highest bit signal 92, 96 Row enable signal 94 Second row memory cell 98 Column enable signal 100 Memory cell Column 102, 128 Data output bus 104 Pixel 1 output line 106 Pixel 6 output line 112 Reformatter / frame memory integrated circuit 114 Input bus 122 Frame memory 124, 136, 142, 146 Digital display Ray device 126 First shift register array 132 Controller 134, 140, 144, 148, 154 Reformatter / frame memory 150 First data path 156 Second data path

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Donald B. Doherty 16 Walnut Creek Place, Richardson, Texas, United States

Claims (3)

[Claims] 1. At least one of: an input bus; an array of memory cells composed of m rows and n memory cells; communicating with the input bus; and an m-bit wide output bus communicating with the memory array. A data reformatter for a video display system, comprising a reformatter memory plane, wherein the memory cell array receives and stores m n-bit wide input data words from the input bus, and n m-bit wide. Output data words to the output data bus,
A data reformatter characterized in that the bit-width output data word is composed of one bit of each word of the m n-bit width input data words. 2. Write m number of n-bit input data words to a reformatter memory, and from said reformatter memory, n number of m-bit output data words consisting of 1 bit of each word of said input data word. And writing the output data word to a frame memory, and reading the output data word from the frame memory. 3. A data reformatter comprising a memory cell array configured as m rows and n memory cells, said memory cell array receiving and storing m n-bit wide input data words, n Outputting m number of m-bit wide output data words, said m-bit width output data word comprising a data reformatter consisting of 1 bit of each word of m number of n-bit width input data words; A display system, comprising: a display device for receiving; and a controller for adjusting operations of the data reformatter and the display device.