JPH09149082A - Packet string mixing generating method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a capacity of a storage device storing a packet arrangement from being increased even when kinds of periods T required to circulate the packet arrangement are increased. SOLUTION: A packet generated is stored in a memory 100 and whether or not a packet is extracted in a time and to be generated from the packet arrangement managed by a packet generating element based on a set period is discriminated and the presence of other packet generating element to taken precedence over the packet generating element is discriminated. As a result of discrimination, when a packet is generated, an address is controlled (20) to generate one packet in the packet arrangement to extract the packet from the memory 100.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet sequence mixture generation method and device, and more particularly to a packet sequence mixture generation method and device used for generating packet sequences having different generation frequencies by mixing them.

More specifically, the present invention relates to a packet sequence mixture generation method and apparatus for generating a packet by mixing a plurality of different packet sequences while maintaining a time average of the number of packets generated from each packet sequence at a predetermined value. . In particular, the functional verification of the conversion system (packet disassembly device) that receives a packet and sends the contents of the payload (packet information portion of the packet) to a specific time region (specific time slot) in a temporally periodic frame is performed. To a packet string mixture generation method and apparatus used for the purpose of generating a packet for use.

[0003]

2. Description of the Related Art When a plurality of packet sequences are mixed at different occurrence frequencies to generate packets, in the conventional technique, as shown in FIG. It is generated by cyclically reading it according to the instruction of the address counter 1.

A conventional method for preparing a packet arrangement will be described. Generally, a packet is composed of a header part and a payload part, and the contents of the payload part are transferred to a frame. For example, when the content of the payload portion of one packet is transferred to a frame, the length of the payload of one packet is 47 bytes, and the content of one byte of the packet is stored in one time slot of one frame. In order to verify the transfer function, it is necessary to give one packet every 47 frames.

In order to disperse the packets, a method of arranging a predetermined number of predetermined packets (empty cells) calculated in advance at necessary locations in the array is adopted. An empty cell is a packet that is not itself processed by the packet decomposer. During the time when an empty cell arrives, processing for packets that have arrived up to that time that is not an empty cell progresses in the packet decomposing device, so including an empty cell in the array simplifies the packets before and after the empty cell. Has the effect of pulling apart in time.

For example, in order to give a test packet of 1 packet in a time of 47 frames, the time of 47 frames is converted into the number of packets, and one of the empty cells of that number is replaced with a test packet. You can prepare an array. To convert the time of a certain number of frames into the number of packets, it is assumed that the time of one time slot of a frame is equal to the time of one byte of a packet for the sake of simplification of explanation. If the number is divided by the number of bytes in one packet, the quotient becomes the time of the frame converted into the number of packets, and if an array consisting of that number of packets is prepared and packets are cyclically generated from that array, Good.

However, if this quotient is not an integer, it is not possible to construct an array of packets to be circulated by that number, so the reference cycle for circling the packets is represented by the number of frames (47 in the above example). Frame) is T, the number of time slots in one frame is LF, and the number of bytes in a packet is LP, and the least common multiple LC of T × LF and LP
It is necessary to construct a packet array that circulates the quotient obtained by dividing by as the number of packets.

Thereafter, for the quantitative evaluation of the conventional technique,
Taking the standard widely used today as an example, LF is 24
30, LP is 53. Considering a cyclic packet arrangement for generating one packet in 47 frames,
LC = LCM ((47 × 2430), 53) is 605
3130, and eventually the number of packets in the array to be circulated becomes LC / 53 = 114210. This number of empty cells is arranged, and 53 empty cells are replaced with test packets at an averaged time interval, and the cells are circulated. The interval of the replaced test packets is
The intervals are not strictly equal, but this causes the contents of the temporary storage unit to increase due to the storage of test packets in the temporary storage unit inside the device under test, and the contents of the frame being extracted from the temporary storage unit. The content will be perfectly balanced no matter how long the time passes.

With the values of T, LF, and LP described here, a packet array to be circulated when N test packets are generally generated in 47 (= T) frames is 11
4210 vacant cells are arranged, and N × 53 vacant cells are replaced with test packets at an averaged time interval, which is stored.

Further, as a packet array to be circulated in order to verify a function of processing a packet having a plurality of headers in multiple, first, N1 packets are generated per 47 frames for a packet having a certain header. Then, 114210 empty cells are arrayed, and N1 × 53 empty cells are replaced with test packets at an averaged time interval. Next, in order to generate N2 packets per 47 frames for a packet having another one header, N2 × 53 empty cells are tested at an average time interval in the array for which replacement has been completed. Replace with packet. This is repeated as many times as necessary to store a packet array, and packets are cyclically generated from this array.

When the cycle T (frame unit) of circulating the packet array has a single value, the array of packets to be circulated can be created by the above method, and the packet is conventionally based on this. Has been generated. In some cases, a plurality of packet sequences having a cycle T (frame unit) for circulating the packet array are not equal to each other. In this case, for example, one packet sequence A tries to generate one packet in 47 frames, another packet sequence B attempts to generate eight packets in 375 frames, and both packets are generated to generate packets. In the conventional method, each T, that is, the least common multiple of 47 of the former and 375 of the latter is set as a cyclic period of a new frame, and the number of packets of each packet sequence is overlapped at a ratio commensurate with the new cyclic period. , A packet array to be circulated will be created.

That is, in this example, the cycle period of the new frame is 47 × 375 = 17625 frames, and the packets of the packet sequence A during this period are 1 × 375.
= 375 packets, the packet in packet sequence B is 8 ×
47 = 376 packets so that they occur at a frequency of
You will have to create a packet array.

In order to make the integer multiple of 17625 frames, which is the cyclic period, match the integer multiple of the packet length, the evaluation condition in the case described above, LF is 2430, L
When P is 53 and the scale of the packet array, that is, the required storage device capacity is calculated, LC = LCM ((17625 ×
2430) and 53) are about 2266 × (10 ⁶ ), and a storage device for storing about 42 × (10 ⁶ ) packets is required.

[0014]

However, the packet array is generally stored in the storage device, and the capacity of the storage device required at that time is proportional to the least common multiple of the cyclic period Ti of the packet to be generated. Due to its nature, if it is attempted to generate a plurality of types of packet sequences having different cyclic periods, the required memory capacity will become extremely large.
A storage device for storing a large packet array of more than 10 ⁶ as in the above-mentioned conventional technique is expensive and not practical. In practice, the number of frames T, which is the standard for the frequency of packet generation, can take many types, so that LC
The value of also becomes large. Therefore, the capacity of the storage device for storing the packet array becomes larger than this. As described above, it is difficult to predict the sufficient capacity of the storage device, which is a technical problem in designing the packet generator.

In the above-mentioned conventional technique, the packet array is repeated an integral number of times so that the boundary coincides with the integer number of repetitions of T (period), which is the number of frames for the period for cyclically generating a packet: When it is necessary to generate packets at a plurality of Ts (cycles) and mix these packets, the least common multiple of all Ts is adopted as a new T, so that it is based on a single T for convenience. Create a custom packet array,
This is stored in the storage device, and the test packet is generated from this.

Therefore, as the number of types of the cycle T for circulating the packet array increases, the capacity required for the storage device for storing the packet array increases rapidly in proportion to the least common multiple of T, and the required packet There is a problem that a row cannot be generated. The present invention has been made in view of the above points, and does not increase the capacity of a storage device that stores a packet array even if the number of types of cycle T that circulates the packet array increases. The purpose is to provide.

[0017]

According to a packet sequence mixture generation method of the present invention, packets to be generated are stored in a memory, and a packet array managed by the packet generation element based on a set cycle T is used. It is determined whether a packet should be extracted and generated at a time, and whether or not there is another packet generation element that has priority over the packet generation element, and if a packet is generated as a result of the determination, the packet array The address is controlled so that one packet is generated, and the packet is taken out from the memory.

Further, the packet sequence mixture generation method of the present invention is such that when a plurality of types of packet generation elements are present,
The packet generation element is a packet generation element dedicated to empty cells so that the packet generation criterion is always satisfied. Also,
The packet string mixture generation method of the present invention also notifies other packet generation elements that the generation of packets by the packet generation elements will end after a certain time.

FIG. 1 is a block diagram of the first principle of the present invention. The packet sequence mixture generation device of the present invention compares the number of packets generated from the reference time and the elapsed time with the set packet generation frequency;
Priority arbitration means 30 for adjusting the priority of packet generation in accordance with the priority determined by the connection, arbitration timing control means 40 for activating the priority arbitration means, and address control for reading packets from the memory 100. The packet generating elements having the means 20 are sequentially connected according to the priority order output from the priority arbitration means 30 in the required number according to the kind of parameters required for packet generation, and the parameters are set in each packet generating element. As a result, a plurality of types of isochronous packet sequences are mixed and generated.

FIG. 2 is a block diagram of the second principle of the present invention. In addition to the above-mentioned configuration, the packet sequence mixing / generating device of the present invention is configured such that each packet generating element replaces the result of the packet generation criterion determination means 10 by setting parameters so that the packet generation criterion is always satisfied. It further comprises means 90.

FIG. 3 is a block diagram of the third principle of the present invention. In the packet string mixture generating apparatus of the present invention, the memory 100 stores the packet to be generated and the notice information that the packet ends, and the priority arbitration means 30 is activated based on the notice information.

FIG. 4 is a block diagram of the fourth principle of the present invention. In the packet string mixture generating device having the empty cell setting means 90 of the present invention, the memory 100 stores the packet to be generated and the advance notice information about the end of the packet,
The priority arbitration means 30 is activated based on the advance notice information.

As described above, in the first and fourth aspects of the invention, the packet generation criterion judging means generates a packet by extracting it at that time from the packet array managed by the packet generating element based on the set period T. Whether there is another packet generating element that the priority arbitration means gives priority to over the packet generating element,
As a result, when a packet is generated, the address control means of the packet array controls the address so as to generate one packet. As a result, even when the cycle of circulating packets does not match the boundary of the packet array, packets can be generated at a constant frequency. Further, by providing the priority arbitration means, it is possible to generate a mixed packet from a packet array that circulates in a cycle of a plurality of values.

Further, in the second and fifth aspects of the invention, the packet generating element is configured as an empty cell by the above empty cell setting means so that the result of the packet generation criterion judgment is always satisfied with the packet generation criterion. Thus, it is possible to generate a plurality of types of packets by mixing them.

Further, in the third, sixth, and seventh inventions, the arbitration timing control unit notifies other packet generating elements that the generation of the packet will be completed after a fixed time, so that the packet generating elements can be restarted. Can be arbitrated. Since each packet generation element only manages the number of packets generated during the set period T, the capacity of the storage device managed by each packet generation element is much smaller than that of the conventional method. .

Further, all packet generating elements are provided with such a function so that different periods T can be set respectively and interact with each other through the wiring for priority arbitration, so that the number of types of T is increased. Even if the required amount of storage device does not increase rapidly as in the conventional case, a packet for verifying the normal operation of the packet decomposing device on a practical device scale by combining the packet generating elements by the number of types of T Can be generated.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION FIG. 5 shows the system configuration of the present invention. In the present invention, different packet generating elements A, B, ... Are provided for each packet sequence having different settings for the cycle T for circulating the packet array.

Each packet generation element shown in the figure is composed of a packet generation reference determination unit 10, an address control unit 20, a priority arbitration unit 30, and an arbitration timing control unit 40. The packet generation criterion determination unit 10 compares the number of packets generated from the packet array after the reference time and the elapsed time for each packet generation element with the set packet generation frequency. As a result, packets are generated at a constant frequency even when the cycle T of the packet array and the boundary of the packet array do not match.

The priority arbitration unit 30 adjusts the priority of packet generation with other packet generation elements on the assumption that a plurality of packet generation elements A, B, ... Which generate packets are connected. As a result, a mixed packet can be generated from a packet array that circulates with a plurality of values of T.

The address controller 20 reads the packet from the memory 100. The arbitration timing control unit 40 activates the priority arbitration unit 30. As a result, the priority arbitration unit 3
According to the priority determined by 0, the required number of packets are sequentially connected according to the types of parameters required for packet generation, and parameters are set for each packet generation element to create multiple types of isochronous packets. Generate rows by mixing.

[0031]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 6 shows the structure of a packet component according to the first embodiment of the present invention. In the figure, among the 1 to N packet generation elements, the value read from the memory 100 is the value that constitutes the packet as it is (for the unit time).

A diagram of the packet array stored in the memory 100 is shown in FIG. In the example of the figure, the header and payload of all packets are stored in each address of the memory 100, one byte at a time. Since only one packet is generated at a time, it can be stored in a single memory 100 as shown in this figure, regardless of which packet generation element manages the packet.

The frame cycle generator 200 of FIG. 6 generates a constant interval signal at a constant frame cycle. This interval signal is input from the terminals ST (input terminals of the packet generation reference determination unit 10) of all packet generation elements. The packet generation element performs a specific counting operation with respect to the terminal ST in order to determine whether a packet has been generated.

Packet generating element i (i = 1 to N) of FIG.
The terminal PTO (output terminal of the arbitration timing control unit 40) broadcasts the start timing of the priority arbitration determination to the priority arbitration determination unit 30 to all packet generating elements including itself. The broadcast start timing of the priority arbitration determination is received by the terminal PTI (the input terminal of the priority arbitration unit 30), and the received packet generation element starts the priority arbitration at that timing.

The packet generation element i (i = 1 to N- in FIG. 6)
1) uses the terminal JO (output terminal of the priority arbitration unit 30) to notify the i + 1th packet generation element of the presence or absence of the packet generation right. The packet generating element N of FIG. 6 has no destination specifically transmitted by the output terminal JO of the priority arbitration unit 30.

The packet generating element i (i = 2 to N) in FIG. 6 performs the priority arbitration processing according to the value given to the input terminal JI of the priority arbitration unit 30 from the packet generating element number i-1. In the packet generation element 1, a fixed value “t = true” is given to the input terminal JI of the priority arbitration unit 30. this is,
The packet generation element [1] is notified that there is no packet generation element having a higher priority than the packet generation element [1], that is, the packet generation element [1] is always the highest priority.

Since the N-th packet generation element [N] has the lowest priority due to the connection of the input terminal JI and the output terminal JO of the priority arbitration unit 30, all other (1 to N-1). You get the right to generate a packet only if none of the packet generators (up to number) generate a packet. Therefore, the N-th packet generation element [N] is set to generate a packet whenever the right to generate a packet is obtained, and a packet with a default value indicating that there is no meaningful packet (for example,
It can also be used to generate empty cells.

The packet generation element i (i = 1 to N) in FIG. 6 gives an address to be read to the memory 100 storing the packet array by the terminal AD (output terminal of the address control unit). FIG. 8 shows an example of parameters included in the packet generation criterion determination unit of the packet generation element according to the embodiment of the present invention. The example shown in the figure is a parameter included in the packet generation criterion determination unit 10 of the i-th (i = 1 to N) packet generation element. This parameter is used in the packet generation criterion determination unit 10 of the packet generation element to determine whether to generate a packet. D
i is the number of packets in the packet array, which is an area in the memory managed by the i-th packet generation element [i]. Li has flag = 1 when the length of the packet generated by the i-th packet generation element [i] is designated, and flag = 0 when it is not designated. In this embodiment, flag = 1. The length of a packet is represented by the time from the start of packet transmission to the end of packet transmission, based on an appropriate unit time.

Hereinafter, for the sake of explanation, the reference unit time is the time taken to send 1 octet (8 bits) of a packet, and 1 octet (8 bits) of a frame.
It is the same as the time required to send the data, and is represented by "1TS". Therefore, when the packet size is 53 bytes, the Li of the packet generation element is 53.
TS.

Ti is the i-th packet generation element [i]
Is the cycle for circulating the packet array. The unit is arbitrary, but is common to all i (1 to N). In order to match the above description, the number of frames is used. A request for the i-th packet generation element [i] to generate a packet is issued under the following conditions.

Di (t) is the number of packets generated by the packet generating element from time 0 to time t, T (t) is the number of frames elapsed from time 0 to time t, Ti and D
When i is the number of the i-th frame and the number of packet generation elements and Di packets are generated within the number of frames Ti, condition 1: (Di (t) / T (t)) <(Di / Ti) If so, the i-th packet generation element [i] issues a request to generate a packet.

Here, rewriting condition 1 while noting that both T (t) and Ti are positive numbers, condition 2: (Di (t) .Ti) <(Di.T (t) ). If PC = Di (t) · Ti FC = Di · T (t) is set on the left side and the right side, respectively, the normalized packet amount PC increases by Ti each time one packet is generated, and the normalized frame is calculated. The quantity FC will increase by Di each time one frame elapses.

As it is, the normalized packet amount P
Since C and the normalized frame amount FC also become infinitely large, they are not suitable for carrying out the invention. Therefore, the processing is performed as follows. The normalized packet amount PC is the value (Di · T
When i) is reached, the value of the normalized packet amount PC is replaced with 0 instead of (Di · Ti): The value of the normalized frame amount FC is decreased by (Di · Ti): By this process The components for counting the normalized packet amount PC and the normalized frame amount FC need only have a capacity for storing a numerical value of at most (2 · Di · Ti).

In this way, when each packet generation element issues a packet generation request, the packet generation criterion determination unit 10 applies the priority order to the request and permits the packet generation. For example, only when the i-th packet generation element [i] issues a request to generate a packet and the packet generation element with a smaller number (that is, a higher priority) does not issue a packet generation request. , I-th packet generation element [i] may be permitted to generate a packet.

FIG. 9 shows the structure of one packet generating element according to the first embodiment of the present invention. In the figure, the same components as those in FIG. 5 are designated by the same reference numerals. The packet generation element i (i = 1 to N) shown in the figure includes a packet generation element criterion determination unit 10, an address control unit 20, a priority arbitration unit 30,
It is composed of an arbitration timing control unit 40 and an operation sequence control unit 50.

The packet generation element determination unit 10 has an FC update control unit 11, a PC update control unit 12 and a comparison unit 13. The operation sequence performed by the operation sequence controller 50 based on the operation timing shown in FIG. 10 will be described below.

Assume that the address control unit 20 controls the address of the memory 100 shown in FIG. 6 so that the i-th packet generation element [i] outputs the packet a. In the unit time zone (machine cycle) of A shown in FIG. 10, the arbitration timing control unit 40 of the i-th packet generation element [i] sets the value of the terminal PTO to "valid".

In FIG. 6, the terminal PTO is the input terminal PTI of the priority arbitration unit 30 of all other packet generating elements.
And, the packet generating elements other than the i-th packet generating element that are electrically connected to the terminal PTO of the arbitration timing control unit 40 and that do not perform control for outputting a packet keep their terminals PTO in an insulated state. ing. Therefore, all the packet generating elements including the i-th packet generating element [i] itself detect that the value of the terminal PTI becomes "valid" at the machine cycle A in FIG.

The priority arbitration unit 30 of all packet generation elements including the i-th packet generation element [i] itself starts priority arbitration when the value of the terminal PTI becomes “valid”,
The values of the output terminal K and the terminal JO to the operation sequence control unit 50 are determined based on the values of the terminal JI and the terminal Q that receives the input from the packet generation criterion determination unit 10. The value given to the terminal Q is a logical value indicating whether or not the packet generating element at that time satisfies the packet generating criterion. The value given to the terminal JI is from the 1st packet generation element [1] to the (i-1) th packet generation element [i
-1] are all logical values indicating that the packet generation criteria are not satisfied. However, for the i = 1st packet generation element [1], this logical value is always "true" as shown in FIG.

The priority arbitration unit 30 determines that, after a fixed time,
As a result of the priority arbitration, the terminal K shows a logical value indicating whether or not the i-th packet generation element has acquired the right to control the output of the packet. What appears at the terminal JO is a logical value indicating that all of the first packet generation element [1] to the i-th packet generation element [i] do not satisfy the packet generation criterion.

When many packet generating elements are connected as shown in FIG. 6, it takes a long time for the priority arbitration unit 30 of all the packet generating elements to determine the value of the terminal K. Therefore, in all the packet generation elements, the P of the terminal Q is temporarily stored until the machine cycle of the priority arbitration of the next packet b in which the terminal PTI becomes “valid” again, and then C shown in FIG.
In this machine cycle, a logical value is represented at the terminal K.

By doing so, it is possible to secure the time to wait for appropriate priority arbitration processing even when the number of packet generating elements is increased by additionally expanding the packet generating elements. If the value of the terminal K in the i-th packet generation element [i] does not have the right to control the output of the packet, then the i-th packet generation element [i] controls the output of the packet. If so, the control for outputting the packet is continued only for the machine cycle D shown in FIG. 10, and the address controller 2 starts from the next machine cycle.
Output 0 is isolated. Further, when the control for outputting the packet is not performed, the output of the address control unit 20 is kept in the insulating state as it is.

When the value of the terminal K in the j-th packet generation element [j] has the right to control the output of the packet, the unit time zone (machine cycle of D shown in FIG. ), The insulation state of the output of the address control unit 20 is continued, and from the next machine cycle,
Address control for outputting the output of the address control unit 20 as a packet is started. The operation order control unit 50 controls the operation order.

At the j-th packet generation element [j], terminal K
If the value of is the right to control the output of the packet, the value of the packet amount PC normalized by the PC update control unit 12 is further updated. Since the time parameters r and q of the operation performed by the operation sequence control unit 50 determine the unit time zone (machine cycle) of A to D shown in FIG. 10, r and q are set according to the operation speed of the parts used. If determined, this configuration can be applied more widely.

FC of the packet generation criterion determination unit 10 of FIG.
The update control unit 11 sends the time signal generated periodically to the terminal S.
Detected at T, the value of the normalized frame amount FC is updated. The value of the normalized frame amount FC is compared with the value of the packet amount PC normalized by the comparison unit 13, and the normalized frame amount FC is the normalized packet amount PC.
Greater than the value of, the packet generation criteria are met,
The value given to the terminal Q of the priority arbitration unit 30 indicates “valid”.

When an empty cell is generated by the Nth packet generation element [N], a packet generation element which always gives "true" to the terminal Q may be used as shown in FIG. it can. The configuration of the packet generation element shown in FIG. 11 does not include the packet generation criterion determination unit 10 but uses a logic unit 70 that always gives “true” to the input terminal Q of the priority arbitration unit 30.

FIG. 12 shows the configuration of the priority arbitration unit according to the first embodiment of the present invention. The priority arbitration unit 30 receives a signal Q indicating whether or not to generate a packet from the packet generation reference determination unit 10 in advance, and when a value indicating "valid" is given to the terminal PTI, the packet generation unit Has a function to indicate to the terminal K whether or not the next packet can be generated. The terminals JI and JO are used to receive and pass the right to generate a packet from another packet generating element adjacent to each other in priority.

When the terminal PTI reaches a value indicating that it is valid, FIG.
The selection circuit D of 2 inputs the input value of the terminal Y to the flip-flop C
Give to. When the terminal PTI becomes a value indicating invalidity, the selection circuit D gives the input value of the terminal X to the flip-flop C, and thus the value stored in the flip-flop C at that time is held. Therefore, when the value of the terminal PTI once becomes “valid” and then returns to “invalid”, the value of the terminal Q at that time is stored in the flip-flop C. All the packet generation units are given the terminal PTI at the same time, and the terminal Q is given from the packet generation reference determination unit 10 whether or not this packet generation unit is going to generate a packet. The PTI of the generation unit flip-flop C is changed from "valid" to "invalid".
Packet generation criterion determination unit 1 at the same time
The result of 0 is stored.

Further, the value of the flip-flop C is always given to the logic element A and the logic element B. FIG.
14 shows a truth table of the logic element A of the priority arbitration unit of the first embodiment of the present invention, and FIG. 14 shows a truth table of the logic element B of the priority arbitration unit of the first embodiment of the present invention.

In the logic element A, the input supplied from the terminal JI is a value indicating "valid" (for example, "1"), and the other value (given from the flip-flop C) is a value indicating "invalid" ( For example, output is "valid" only when "0")
Is set to a value (for example, "1"). Therefore, the terminal JI
Is given a valid value, and the value of the flip-flop C of this packet generation unit indicates "invalid" (that is, this packet generation unit did not reach the criterion for generating a packet). Only in the case), a value indicating validity is output to the terminal JO.

As a result, the 1st to i-1th packet generation elements shown in FIG. 6 have not reached the packet generation reference, and the ith packet generation element [i] has reached the packet generation reference. When it is present, the values of the JIs from the 1st to the i-th are “valid”, and the JIs after the i + 1th are
Since the value of is "invalid", the i-th packet generation element [i] is prioritized even if there is a packet generation element that has reached the packet generation reference after the i + 1th,
It will be adjusted so that there is no conflict between multiple packet generating elements.

The logic element A of the priority arbitration unit 30 is connected to the terminal JI.
The value provided by the input is "valid" (for example,
"1") and the other value (given from the flip-flop C) is "valid" (for example, "1"), the output is "valid" (for example, "1"). ).

This output is given to the logic element G. FIG. 15 shows a truth table of the logic element G of the priority arbitration unit according to the first embodiment of the present invention. The logic element G has a value (for example, “1”) indicating that the input supplied from the logic element B is “valid”,
The other (given from column E of flip-flops)
Only when the value is a value indicating valid (eg, “1”), the output is set to a value indicating “valid” (eg, “1”).

As a result, when the output of the logic element B stabilizes after a certain period of time elapses after the terminal PTI becomes a value indicating "valid", and the output of the logic element B is "valid", , The value of the terminal K is valid only for the same period as the terminal PTI is valid. The row E of flip-flops delays the input given from the terminal PTI in proportion to the number q of flip-flops forming the row and outputs the delayed input.

When many packet generating elements are connected as shown in FIG. 6, it takes some time to stabilize the output of the logic element B at the last Nth packet generating element. The row E of the flip-flops is until the output of the logic element B stabilizes even if the value of the terminal PTI becomes “valid”.
The logic element G functions so as not to output a "valid" value.

The value of the terminal K of the priority arbitration unit 30 is given to the operation sequence control unit 50, and if the value is "valid",
The control for packet generation is started after a certain period of time. In this way, the priority arbitration unit 30 receives the signal Q indicating whether to generate a packet from the packet generation criterion determination unit 10 in advance at the terminal Q, and then the terminal PT
When a value indicating "valid" is given to I, the function of indicating to the terminal K whether or not this packet generation unit can generate the next packet within a fixed time is realized.

The FC update control unit 11 of FIG. 9 detects a time signal that occurs periodically at the terminal ST and updates the value of the normalized frame amount FC to a value larger by Di than the previous value. To do. When the PC update control unit 12 notifies that the value of the normalized packet amount PC has reached (Di, Ti), the value of the normalized frame amount FC is decreased by (Di, Ti). .

The PC update control unit 11 in FIG. 9 uses the signal from the operation control unit 50 to normalize the packet amount P.
The value of C is updated to a value that is larger than the previous value by Ti. However, the value of the normalized packet amount PC is (Di,
When (Ti) is reached, the value of the normalized packet amount PC is immediately replaced with "0" instead of (Di, Ti).

When the arbitration timing unit 40 of FIG. 9 generates a packet in the unit of packet generation based on the signal from the operation sequence control unit 50, the arbitration timing unit 40 sets the time to leave a fixed time until the end of the packet as Li. Based on (the packet length generated by the i-th packet generation element [i]), the value of the terminal PTO is set to "valid" for a certain period of time.

The address control unit 20 of FIG. 9 is based on a signal from the operation sequence control unit 50, and while the packet generation unit is generating a packet, the address of the memory for taking out the contents of the packet to the terminal AD. Is being output. When the packet generation unit is not generating a packet, the address control unit 20 insulates the terminal AD based on the signal from the operation sequence control unit 50 and affects other packet generation elements connected in parallel. Try not to hit. The address of the memory in which the packet to be generated next is stored from the packet generating element is internally held.

Further, the address control unit 20 holds area information in the memory 100 in which the packet handled by the packet generating element is stored. For example, from the memory area to where the packet generating element is stored. It holds packets to be handled and cyclically generates packets in the area to be handled.

When the signal from the priority arbitration unit 30 becomes "valid", the operation sequence control unit 50 of FIG. 9 sends a notification of the timing for performing the series of operation sequence control described above to each unit. Is. As a result, according to the first embodiment described above, the parameter (D
(packets of i, Ti, Li) are installed to store the packets, and the storage device mixes the packets with a capacity of at most proportional to N. Can be generated isochronously. For example, 47 used in the description of the conventional technique.
A packet sequence that generates one packet in a frame,
In the case of generating a packet sequence that generates eight packets in 375 frames, three packet generation elements are installed, one of which is a dedicated element for generating empty cells, and the remaining two 1 (D)
i, Ti, Li) = (1, 47, 53), and (Di, Ti, Li) = (8, 3) for the other packet generation element.
75, 53) is set. At that time, the required memory amount is
It will be possible to carry out a total of 10 packets by adding 1 packet for an empty cell. This is much smaller than the required memory amount of 42 × (10 ⁶ ) packets in the conventional example.

[Second Embodiment] Next, a second embodiment of the present invention will be described. The present embodiment is an example in which the packet generating element of the first embodiment described above can be used as a packet generating element dedicated to an empty cell. FIG. 16 shows the configuration of the packet generation element according to the second embodiment of the present invention. In the figure, the same components as those of FIG. The configuration of the packet generation element shown in FIG. 16 is a configuration in which an OR circuit 80, an empty cell setting unit 91, and an empty cell designating unit 92 are added to the configuration of FIG.

When the value given to the terminal DC of the packet generation element is "valid", the packet generation request is always generated regardless of the result of comparison between the normalized packet amount PC and the normalized frame amount FC. A certain Q becomes "valid". In this way, the OR circuit 80 is set so that the request given to the terminal Q of the priority arbitration unit 30 is always "valid".

In the above-mentioned first embodiment, the number of packet generating elements is determined according to the type of packet to be generated,
When the number is N, it is necessary to configure the N-th packet generation element [N] having the lowest priority as the empty cell dedicated module shown in FIG. But,
When the packet generating elements of this embodiment are used to configure M (M> N) packet generating elements in advance in the same wiring as in the first embodiment, the DC terminal of the Nth module is connected. By setting the value to be “valid”, it can be applied to the generation of arbitrary N kinds of packets that are not more than M without changing the mutual connection of the packet generating elements.

In this embodiment, in addition to the effects of the first embodiment described above, an apparatus having M packet generating elements can be used with the same configuration and parameters of any type from 1 type to M types can be used. It can be generated by mixing packet sequences. [Third Embodiment] Next, a third embodiment of the present invention will be described.

In the packet generating element of this embodiment, the connection between the packet generating elements of the first embodiment is changed as shown in FIG. 17, and the priority arbitration unit 30 in the packet generating element i is shown in FIG. I have replaced it with one. In FIG. 17, not only the packet main body but also information notifying the end position of the packet is written in the memory 100 storing the packet to be generated, and this information is extracted from the output of the memory, and based on this, all the information is extracted. The timing for starting priority arbitration is generated in the packet generation element.

For example, as shown in the array of packets in the memory shown in FIG. 19, when a certain number of octets before the last octet of a packet is read in any packet, "1" is read as a terminal symbol at the same time. Keep it. The read terminal symbol activates the timing adjustment unit 300 in FIG. 17, and broadcasts the timing at which the timing adjustment unit 300 starts priority arbitration to all packet generation elements.

The packet generating elements shown in FIG. 19 are respectively shown in FIG.
It holds the parameters shown in 8. At this time, the Li flag = “0” is set, and the length of the packet handled by the packet generation element is not designated. Further, as shown in FIG. 18, each packet generating element does not require the terminal PTO.

FIG. 20 shows the configuration of the priority arbitration unit of the packet generating element according to the third embodiment of the present invention. In the priority arbitration unit 30 shown in the figure, a logic element H and a terminal N are added as compared with the configuration of FIG. 12 of the first embodiment described above. The truth table of the logic element H is shown in FIG. The value of the signal appearing at terminal N is "valid" if this packet generating element does not have the right to generate a packet.

The terminal N is connected to the terminal E of the operation sequence control unit 50 in the configuration of the packet generating element shown in FIG. Note that the terminal K is connected to the terminal B of the operation sequence control unit 50, as in the first embodiment. The operation sequence control unit 50 in the third embodiment operates in the same manner as in the first embodiment when a valid value is given to the terminal B, but a valid value is given to the terminal E. If the address control unit 20 is connected to the terminal A, 1. If a packet is currently being output, the output terminal AD of the address control unit 20 will be output after the output packet is completed.
Insulate: If no packet is currently output, the output terminal AD is continuously set to the insulated state:

As described above, in this embodiment, if the information indicating the end position of the packet is written in the memory 100, for example, the terminal symbol is written in the memory shown in FIG. 19 at a fixed position from the end position. Thus, it is possible to control the generation of packets having different lengths with one packet generation element.

In addition to the effect of the first embodiment, the third embodiment has the following advantages:
It can be generated by handling one packet generation element. Moreover, since it is not necessary to set Li (the length of the packet handled by the i-th packet generation element [i]) (flag of the parameter Li = 0), the parameters set in each packet generation element can be simplified.

[Fourth Embodiment] This embodiment is the same as the third embodiment described above.
The priority arbitration unit 30 of this embodiment is applied to the above-mentioned second embodiment. FIG. 23 shows the structure of a packet generation element according to the fourth embodiment of the present invention. With the configuration shown in the figure,
Since the configurations of the second and third embodiments described above are combined, both effects can be obtained.

The present invention is not limited to the above embodiments, but various modifications and applications are possible within the scope of the claims.

[0086]

As described above, according to the present invention, packets are stored by installing N packet generating elements corresponding to a plurality of types of packet sequences according to the types of parameters of the packet sequences to be generated. With respect to the storage device to be stored, it is possible to generate packets by mixing the packets in a capacity that is proportional to N. Therefore, even if the number of types of the cycle T that circulates the packet array increases, the capacity of the storage device that stores the packet array increases only to an extent proportional to the number of types, which increases the required capacity of the storage device. Can be practically solved.

[Brief description of the drawings]

FIG. 1 is a first principle configuration diagram of the present invention.

FIG. 2 is a second principle configuration diagram of the present invention.

FIG. 3 is a third principle configuration diagram of the present invention.

FIG. 4 is a fourth principle configuration diagram of the present invention.

FIG. 5 is a system configuration diagram of the present invention.

FIG. 6 is a configuration diagram of packet components according to the first embodiment of this invention.

FIG. 7 is a diagram showing a packet array in the memory of the first exemplary embodiment of the present invention.

FIG. 8 is a diagram showing an example of parameters included in the packet generation criterion determination unit of the packet generation element according to the first embodiment of this invention.

FIG. 9 is a configuration diagram of one packet generating element according to the first embodiment of this invention.

FIG. 10 is a diagram showing an operation timing of the first embodiment of the present invention.

FIG. 11 is a configuration diagram of a packet generation element when generating an empty cell according to the first embodiment of this invention.

FIG. 12 is a configuration diagram of a priority arbitration unit according to the first embodiment of this invention.

FIG. 13 is a truth table of the logic element A of the priority arbitration unit according to the first embodiment of this invention.

FIG. 14 is a truth table of the logic element B of the priority arbitration unit according to the first embodiment of this invention.

FIG. 15 is a truth table of the logic element G of the priority arbitration unit according to the first embodiment of this invention.

FIG. 16 is a configuration diagram of a packet generation element according to the second embodiment of the present invention.

FIG. 17 is a diagram showing connections between packet generation elements according to the third embodiment of this invention.

FIG. 18 is a configuration diagram of a parameter list and a priority arbitration unit according to the third embodiment of this invention.

FIG. 19 is a diagram showing an example of an array of packets in the memory of the third exemplary embodiment of the present invention.

FIG. 20 is a configuration diagram of a priority arbitration unit of a packet generation element according to the third embodiment of this invention.

FIG. 21 is a truth table of the logic element H according to the third embodiment of the present invention.

FIG. 22 is a configuration diagram of a packet generation element according to the third embodiment of this invention.

FIG. 23 is a configuration diagram of a packet generation element according to the fourth embodiment of the present invention.

FIG. 24 is a diagram showing an example of conventional packet generation.

[Explanation of symbols]

10 packet generation reference determination means, packet generation reference determination portion 11 FC update control portion 12 PC update control portion 13 comparison portion 20 address control means, address control portion 30 priority arbitration means, priority arbitration portion 40 arbitration timing control means, arbitration timing control Part 50 Operation order control part 70 Logic circuit 80 Logic circuit 90 Free cell setting means 92 Free cell designating part 91 Free cell setting part 100 Memory 200 Frame cycle generating part 300 Timing adjusting part

Claims (7)

[Claims] 1. A packet to be generated is stored in a memory, and it is determined whether or not the packet should be extracted at that time from a packet array managed by the packet generation element based on a set cycle T. It is determined whether or not there is another packet generating element that has priority over the packet generating element, and when a packet is generated as a result of the determination, the address is controlled so that one packet in the packet array is generated. Then, the packet sequence mixture generation method is characterized in that the packet is retrieved from the memory. 2. The packet string mixture generation method according to claim 1, wherein when there are a plurality of types of packet generation elements, the packet generation element is a packet generation element dedicated to an empty cell so that the packet generation criterion is always satisfied. . 3. The packet string mixture generation method according to claim 1, further notifying other packet generation elements that the generation of packets by said packet generation element will be terminated after a fixed time. 4. A packet generation reference determining means for comparing the number of packets generated from a reference time with a packet generation frequency for which an elapsed time has been set, and a packet generation right according to a priority determined by connection. A packet generating element having priority arbitration means for adjusting the priority of the generation of the packet, arbitration timing control means for activating the priority arbitration means, and address control means for reading the packet from the memory are required for the packet generation in accordance with the priority order. Packets characterized in that a plurality of types of isochronous packet strings are mixed and generated by sequentially connecting the required number of wires according to the types of various parameters and setting parameters in each of the packet generation elements. Row mixing generator. 5. The packet according to claim 4, further comprising empty cell setting means for replacing the result of said packet generation criterion determination means by setting a parameter in each said packet generation element so that the packet generation criterion is always satisfied. Row mixing generator. 6. The packet string mixture generating apparatus according to claim 4, wherein the memory stores the packet to be generated and the advance notice information that the packet ends, and the priority arbitration unit is activated based on the advance notice information. 7. The packet string mixture generating apparatus according to claim 5, wherein the memory stores, together with a packet to be generated, advance notice information that the packet will end, and the priority arbitration unit is activated based on the advance notice information.