JPH09148541A - Ferroelectric memory device and driving method thereof - Google Patents

Abstract

Kind Code: A1 A ferroelectric memory device and a method of driving the same are provided, and a ferroelectric memory cell structure that ensures a write operation and has no imbalance in write voltage and a method of driving the same. SOLUTION: One field effect transistor type ferroelectric memory cell having a ferroelectric film 7 on a part of gate insulating films 5 to 7 is arranged in a matrix, and source / drain regions 3 and 4 are commonly used. Of the source / drain regions are connected to the well lines 2 and the plate lines 9 are connected to the well regions 2 and the gate electrodes 8 are used as the word lines 11. In addition to being commonly connected, the other 3 of the source / drain regions is commonly connected to the drive line 12 extending in the direction of the bit line 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device and a method of driving the same, and more particularly to a ferroelectric memory device in which a MISFET using a ferroelectric as a gate insulating film performs a non-volatile memory action. And a driving method thereof.

[0002]

2. Description of the Related Art Conventionally, an EEPROM, a flash memory or the like has been used as a non-volatile semiconductor memory device, but since a high voltage of 10 to 12 V is required for writing, it is different from other semiconductor memory devices. There is a problem that it cannot be operated with a single 5V power source, and
There is a problem that the writing time is long and it cannot be operated at high speed.

In recent years, in order to solve such problems of high voltage and write time, a ferroelectric memory device using a ferroelectric material such as PZT (PbZr _0.52 Ti _0.48 O ₃ ) in the gate insulating film of MISFET has been proposed. Although developed, this ferroelectric memory device has two methods: a method of detecting a change in the storage capacity of a ferroelectric capacitor and a method of detecting a resistance change due to the influence of remanent polarization of a ferroelectric material. There is.

First, the first method is FRAM (trademark of Ramtron Co., Ltd.) proposed by Ramtron Co., Ltd.
The ferroelectric substance is used as the dielectric substance of the information storage capacitor to detect the change in the storage capacitance due to the polarization reversal. However, since the cell structure of 2Tr + 2C is currently on the market, the integration degree is improved. Is not enough,
In addition, there is a drawback that the reading is destructive. Also, a FRAM having a cell structure of 1Tr + 1C similar to a conventional DRAM.
(Trademark of Ramtron Co., Ltd.) has also been developed, but it is in the state of practical application.

On the other hand, the second method is a 1Tr type MFS.
-FET (Metal Ferroelectric)
There is a Semiconductor FET), and this M
The FS-FET will be described with reference to FIG.
92173).

See FIGS. 11A and 11B. In the p-type well region 81, the n ⁺ -type source / drain region 8 is formed.
After forming 2, 83, a ferroelectric thin film 84 such as PZT
Is provided as a gate insulating film and a gate electrode 85 is provided thereon, and the electric field vector is directed downward between the n ⁺ type source region 83 short-circuited with the p type well region 81 and the gate electrode 85. The ferroelectric thin film 84 is polarized by applying a voltage.

Since this polarization remains as a remnant polarization even if the voltage is 0, electrons are induced at the interface of the p-type well region 81 / ferroelectric thin film 84 to become normally on, and information is semipermanently stored. Become. Information may be stored as a normally-off type by reversing the applied electric field.

Next, when reading information, the potential of the bit line (BL) 86 selected first is set to 0 V, and then the reference line (RL) 9 connected to the sense amplifier 92.
Precharge the reference potential of 3 to V _CC (power supply voltage) / 2 and add 5.0V to the selected plate line (PL) 88.
A voltage of (V _CC ) is applied. At this time, a voltage of 5.0 V is applied to the word line (WL) 87 selected so that the data is not rewritten, and the non-selected plate line (PL) 88 and word line (WL) 87 are floated. State.

In this case, if "1" is stored in the MFS-FET and it functions as a normally-on type, that is, a depletion type, the potential of the selected bit line (BL) 86 gradually rises, and eventually the reference. Since the potential becomes higher than _Vcc / 2, the bit line (BL) 86 becomes 5.0V and the reference line (RL) 93 becomes 0V by turning on the sense amplifier 92 here, and this potential is detected. By doing so, the content of the information is read out.

In FIG. 11, reference numerals 89, 90,
Reference numerals 91 and 91 represent a ferroelectric memory cell, a word selection decoder driver, and a plate selection decoder driver, respectively.

However, in such an MFS-FET, the plate line (PL) 88 and the word line (WL) 87 are set to 5.0 V at the time of reading, and as a result, they are connected to the bit line (BL) 86. Since the pn junction forming the n ⁺ -type drain region 82 is forward biased and becomes conductive, the bit line (BL) 86 is irrespective of the content of information.
However, there is a problem that the memory does not operate.

On the other hand, an MFS-FET without such a problem
As such, a 1Tr type ferroelectric memory device shown in FIG. 12 has also been proposed (see Japanese Patent Laid-Open No. 7-45794). See FIG. 12A. The cell structure of this 1Tr type ferroelectric memory device is shown in FIG.
The cell structure is substantially the same as the cell structure shown in (a), and the wiring structure and therefore the bias structure are different.

12B, that is, in this case, the plate electrode T connected to the p-type well region 81 and the source extraction electrode S connected to the n ⁺ -type source region 83 are independent, and the plate electrode T Is applied with the lowest potential in the integrated circuit, while the source extraction electrode S is applied with the same potential as the bit line BL or the ground potential. FIG. 12B shows the same potential as the bit line BL. It shows an example of applying.

[0014] Then, the write voltage V _W of -1/2 to bit lines BL _0, which is selected, i.e., by applying a -V _W / 2, is -V _W / 2 to the source extraction electrode S ₀ When applied, the potential of the channel region under the gate electrode 85 is also −V _W
/ 2 becomes the same potential, and by applying 1/2 of the write voltage V _W , that is, V _W / 2 to the selected word line WL ₀ , the selected cell (upper left cell in the figure) is applied. Is V
The voltage of _W is applied and writing is performed.

When a ground potential is applied to the source extraction electrode S, the n ⁺ type drain region 82 and the gate electrode 8 are formed.
Ferroelectric film 8 in the overlapping part sandwiched between 5 and
It is explained that only 4 will be polarized.

See FIG. 12C. As another driving method, the selected word line WL is used.
_The write voltage V _W is applied to ₀ , V _W / 3 is applied to the unselected word line WL ₁ , the selected bit line BL _{0 is set} to 0 V, and 2 V _W is applied to the unselected bit line BL _1. / 3 is applied, and the voltage of V _W is applied to the selected cell (the cell at the upper left in the figure) to perform writing. Note that FIG. 12C shows an example in which a ground potential is applied to the source extraction electrode S.

However, in such an MFS-FET, since the ferroelectric substance is an oxide, the p-type well region 81 is formed.
And SiO ₂ film (not shown) on the interface between the ferroelectric thin film 84 and
Is formed, and not only the operating voltage is increased by the formation of this SiO ₂ film, but also trap levels are generated, and charges are injected into the ferroelectric thin film 84 to cancel the charges due to remnant polarization. .

When the film forming temperature of the ferroelectric thin film 84 is high, the constituent elements of the ferroelectric thin film 84 are p-type well regions 8.
1, that is, there is a problem that the element characteristics are changed by diffusing into the silicon substrate. Therefore, in order to improve such a problem, MFIS (Metal Ferroelectric
ic Insulator Semiconductor
r) structure and MFMIS (Metal Ferroel)
electric Metal Insulator Se
A ferroelectric memory device having a microstructure (see Japanese Patent Laid-Open No. 7-202035) has been proposed.

Of these, MFIS is not shown, but p
SiO in the well region or p-type silicon substrate surface
_The ferroelectric thin film is formed after the _two films are formed, and the constituent elements of the ferroelectric thin film are prevented from diffusing into the well region or the silicon substrate by actively providing the SiO ₂ film. It is a thing.

See FIG. 13A. Further, in the MFMIS, in order to improve the retention characteristic of the remanent polarization of the MFIS, the compatibility between the SiO ₂ film 94 and the ferroelectric thin film 84 and the ferroelectric thin film 84 is maintained. With a good Pt film interposed, a high-quality ferroelectric thin film 84 can be obtained by the presence of the Pt film, that is, the floating gate 95.

However, in the driving method described in Japanese Unexamined Patent Publication No. 7-202035, the unselected word line WL is used.
_{Since 1} is in a floating state, the potential may be unstable and the operation may become unstable. In addition, unselected word line WL ₁
A reverse electric field to the selected cell (upper left cell in the figure) is applied to the ferroelectric thin film 84 of the unselected cell (lower right cell in the figure) connected to the unselected bit line BL ₁ and the unselected cell. Therefore, there is a problem that the stored information is likely to be destroyed while the writing is repeated many times.

Further, the present inventor has proposed a ferroelectric memory device which can be highly integrated and can surely operate by improving the wiring structure and the driving method (Japanese Patent Application No. 2000-242242). No. 7-230868), this ferroelectric memory device will be described with reference to FIG.

Referring to FIG. 14A, first, a common p-type well region 2 extending in the column selection line direction on the n-type silicon substrate 21 in the same manner as the bit line (BL) 30.
2 is formed, and then a SiO ₂ film having a thickness of 100 Å to 300 Å, preferably 250 Å, and a thickness of 150 to be a floating gate.
A Pt film having a thickness of 0Å to 3000Å, preferably 2000Å, a PZT thin film having a thickness of 1000Å to 7000Å as a ferroelectric film, preferably 4000Å, and a conductive film such as Pt are sequentially deposited and then patterned. SiO
_A gate insulating film made of the ₂ film 25, the Pt film 26, and the PZT thin film 27 and a plurality of gate electrodes 28 are formed so as to be arranged in the column selection line direction. Note that only one is shown in the figure.

Next, using the gate electrode 28 as a mask, A
An n-type impurity such as s is selectively introduced to form an n-type drain region 23 and an n-type source region 24, a plate line (T) 29 is formed in the p-type well region 22, and an n-type drain region 23 is formed.
The bit line (BL) 30, the word line (WL) 31 to the gate electrode 28, and the drive line (D) 32 to the n-type source region 24 are connected to complete the ferroelectric memory cell.

See FIG. 14B. This ferroelectric memory cell is provided in mirror symmetry.
Each bit line (BL ₀, BL₁・ ・) Column selection for 30
The transistor 39 and the resistor 37 connected to the ground potential
A sense amplifier 38 is connected via the. In addition, this
The sense amplifier 38 of FIG.
The p-type well region 22 formed at the same time as the base region
The n-type drain region 23 and the n-type source region 24.
Lateral bipolar as the miter region and collector region
It is formed as a transistor.

Further, although not shown, each write signal
Line, that is, each plate line (T₀, T ₁・ ・) 29
Bit line (BL₀, BL₁..) Column selection hand like 30
Connected to each word line (WL₀, W
L₁・ ・) 31 and each drive line (D₀, D₁・ ・) 3
2 is ground potential or 1.65V (V_CC/ 2)
Row selection means for applying the first potential is connected.

With such a memory cell structure, since the p-type well region 22 itself can be used as the plate line (T), a separate wiring space for the plate line (T) becomes unnecessary, The degree of integration is improved.

When erasing information in this ferroelectric memory device, first, all bit lines (BL) and drive lines (D) are brought into a floating (floating) state, and power is supplied to all plate lines (T). Apply voltage V _CC (3.3V),
At the same time, the ground potential is applied to all the word lines (WL) to make the ferroelectric memory cells non-conductive, and the PZT thin film 27 is set to -P.
By reversing the polarization in the r direction and making it correspond to the data "0", the information in all the ferroelectric memory cells is erased collectively as in the floating gate transistor type flash memory.

Next, when writing data "1", 1.65 V is applied to all bit lines (BL) and drive lines (D).
With the second potential of (V _CC / 2) applied, 0V (ground potential) is applied to the selected plate line T and the third potential is applied to the selected word line (WL) to select the strong potential. Data "1" is written in the dielectric memory cell. The plate line T and the word line (WL) not selected are 1.65.
Since the second potential of V is applied, the writing of the data “1” to the cell whose write data is “0” is prohibited.

This third potential (V _W ) is applied to the PZT thin film 27 so that the memory cell output becomes "1" at the time of reading.
Is a potential polarized by + Pr ^* in the + Pr direction, and the memory cell polarized by + Pr ^* is in a normally-off state in which the threshold value (V _th ) is lowered to the extent of conduction when a read potential is applied.

Further, since the second potential of 1.65 V is applied to the unselected plate line T and word line (WL), it is possible to prevent information from being erroneously written in unselected memory cells during writing. The operation stabilizes.

Next, when reading the information, all the plate lines (T) are set to the ground potential, and all the drive lines (D) are set to the second potential of 1.65 V, and the selected bit is selected. The line (BL) is brought to the ground potential through the resistor, that is, the ground potential side, and the selected word line (WL)
Is applied with a first potential of 1.65 V (V _CC / 2). In this case, the unselected bit line (BL) is floated and the word line (WL) is set to 0V.

In this case, when "1" is written in the memory cell, the read voltage (1.65V) is applied to bring the memory cell into a conductive state and the bit line (BL).
Information is detected through the sense amplifier due to the potential fluctuation of the. Note that when "1" is not written in the memory cell, that is, when the data in the memory cell is "0", the memory cell does not conduct, so that no potential change occurs.

Further, unlike the conventional 1Tr type ferroelectric memory device shown in FIG. 11, the plate line (T) corresponding to the plate line is set to the ground potential, so that it is not selected and connected to the bit line (BL). The pn junction of the n-type drain region 23 will not be forward-biased, and the memory cell will operate reliably.

Further, in such a conventional ferroelectric memory, there is a problem that the polarization characteristics are deteriorated in the half-selected memory cells or the non-selected memory cells. It has been proposed to interpose a two-terminal switch element between the thin film and the word line (see Japanese Patent Application Laid-Open No. 7-106450), which will be described with reference to FIG.

That is, the selected memory cell and the memory cell in which only one of the word line or the bit line is commonly connected are in the half-selected state, and the gate electrode and the gate electrode are used when writing "1" or "0" information. Since an intermediate voltage equal to or lower than the coercive voltage V _c is alternately applied between the source region and the drain region in opposite directions to each other, the “lack of true” is applied.
The phenomenon of "E _c " deteriorates the polarization characteristics and finally causes a problem that information is rewritten.

15A and 15B, in order to solve such a problem, the ferroelectric memory cell shown in FIG. 15A has a ferroelectric thin film 84 and a gate. Two-terminal switch element 9 between electrode 85
8 is provided, and FIG. 15B shows an equivalent circuit thereof.

In this improved ferroelectric memory, as in the ferroelectric memory shown in FIG. 12, which is a prerequisite for the improved ferroelectric memory, the gate electrode 85 and the word line 87 are provided.
, The n ⁺ type drain region 82 is connected to the bit line 86, the n ⁺ type source region 83 is grounded via the source extraction electrode 94, and the p type well region 81 (or p type substrate) is connected. Is fixed to the lowest voltage in the integrated circuit through the plate electrode 88.

As described above, by providing the two-terminal switch element 98, the PrV characteristic (polarization vs. voltage characteristic) becomes a PrV curve with a very good squareness ratio, and the rising and falling at on and off become very good. The polarization value hardly changes depending on the voltage applied when the semiconductor device is half-selected, and the polarization characteristic does not deteriorate due to "lack of true E _c ".

[0040]

However, the ferroelectric memory device of the first type has a relatively complicated structure such as requiring storage capacity, or the ferroelectric memory device shown in FIG. As described above, there is a problem that a reliable memory operation cannot be obtained.

12B and 12C. Further, in the case of the ferroelectric memory device shown in FIG. 12, when the source extraction electrode S is set to the same potential as the bit line BL,
As described, whether or not the channel region has the same potential as that of the bit line BL is unknown, and therefore, whether or not reliable writing is actually performed is unknown, and the source extraction electrode S is grounded. When the potential is set, there is a problem that writing can actually be performed due to the overlap between the source region and the gate electrode.

Further, even if reliable writing is possible, there is a problem that the information in the half-selected cell is destroyed. That is, when using it as a flash memory,
Although the driving method of FIG. 12B has no problem,
In the case of the driving method of (c) will become the reverse electric field of _{-V W / 3 (= V W} / 3-2V W / 3) to the half-selected cell at the bottom right of the figure is applied, the write operation There is a problem that the information of the half-selected cell to which the reverse electric field is applied is destroyed while repeating the above, and when used as a RAM (random access memory), which drive method is used? Also causes the problem of information destruction.

Further, in the case of the ferroelectric memory device shown in FIG. 13, since the unselected word line WL ₁ is in the floating state as described above, the potential becomes unstable and the operation becomes unstable. And the unselected word line WL ₁
Since a reverse electric field is applied to the non-selected cells connected to the non-selected bit line BL ₁ , there is a problem that the stored information is destroyed while writing is repeated many times. is there.

In the case of the ferroelectric memory device shown in FIG. 14, a channel is generated at the time of writing "1", and the channel becomes the same potential as the source / drain region to which the second potential is applied. It was found that writing was impossible because the ferroelectric thin film was applied with a voltage of V 2 only.

Further, in the case of the ferroelectric memory device shown in FIG. 15, the problem of the deterioration of the polarization characteristics due to the write operation and the read operation in the ferroelectric memory device shown in FIGS. 11 to 14 is solved. However, since the write operation itself is the same as that of the ferroelectric memory device shown in FIG. 12, it is uncertain whether or not a reliable write is actually performed as in the ferroelectric memory device shown in FIG. And also
When the source extraction electrode S is set to the ground potential, there is a problem that it is unclear whether data can be actually written in the overlapping portion between the drain region and the gate electrode.

Therefore, an object of the present invention is to provide a ferroelectric memory cell structure in which the write operation is reliable and the write voltage is not unbalanced, and a driving method thereof, and the write operation and the read operation are performed. The purpose is to reduce the deterioration of the polarization characteristics associated with the above.

[0047]

FIG. 1 is an explanatory view of the principle structure of the present invention. Means for solving the problems in the present invention will be described with reference to FIG. Refer to FIG. 1. (1) The present invention is a ferroelectric memory in which one field effect transistor type ferroelectric memory cell having a ferroelectric film 7 in a part of the gate insulating films 5 to 7 is arranged in a matrix. In the device, the source / drain regions 3 and 4 are provided in the common well region 2, the well region 2 is connected to the plate line 9, and the gate electrode 8 is used as the word line 11 to provide row selecting means. One of the source / drain regions 4 is commonly connected to the bit line 10, and the other 3 of the source / drain regions is commonly connected to the drive line 12 extending in the direction of the bit line 10.

Since the common well region 2 is used as the plate line 9 in this manner, the wiring space for the plate line 9 for applying the erase voltage is not required, so that the degree of integration is improved and "1" is obtained. At the time of writing the information of ", since the writing is performed by the electric field applied between the channel generated just below the gate electrode 8 and the gate electrode 8, the write voltage is" 0 "and" 1 ". There is no balance.

(2) Further, the present invention is characterized in that, in the above (1), the gate insulating film has a laminated structure of an insulating film 5 / a floating gate 6 / a ferroelectric film 7.

As described above, since the floating gate 6 is provided between the insulating film 5 and the ferroelectric film 7, the high quality ferroelectric film 7 can be provided with good reproducibility as in the conventional MFMIS. In addition, when a voltage is applied to the gate electrode 8 to polarize the ferroelectric film 7, a normally-off state having a predetermined threshold value (V _th ) can be stably realized.

(3) Further, according to the present invention, in the above (1) or (2), in order to enable trimming of the third potential (V _W ) for writing information in the ferroelectric memory cell chip by chip, A third potential trimming means having a polycrystalline semiconductor fuse is provided therein.

As described above, the third potential (V _W ) for writing information in the ferroelectric memory cell can be trimmed on a chip-by-chip basis, so that the ferroelectric memory cell when data "1" is written can be trimmed. The threshold value (V _th ) can be set stably.

(4) Further, the present invention provides the method for driving a ferroelectric memory device according to any one of the above (1) to (3), in which the plate line 9 and all the gate electrodes 8 are provided. An erase voltage (V _E ) is applied to bring the surface of the semiconductor layer facing the gate electrode 8 into an accumulated state, so that all the ferroelectric memory cells are polarized so as to be non-conductive and data “0” is stored. It is characterized in that information is erased by making it correspond to ".

By applying the voltage in this manner, the surface of the semiconductor layer facing the gate electrode 8 is in an accumulation state, and a sufficient electric field is applied to the ferroelectric thin film 7, so that the normal erasing voltage (V _E ) is applied. The information in all the ferroelectric memory cells can be erased at once, and it can be operated in the same manner as the conventional floating gate transistor type flash memory.

(5) In the method of driving a ferroelectric memory device according to any one of the above (1) to (3), the present invention sets the plate line 9 to the ground potential and selects the selected word line 11. Is set to the third potential (V _W ), and the selected bit line 10 and drive line 12 are set to the ground potential,
In addition, by setting the unselected word line 11, bit line 10, and drive line 12 to the second potential (approximately V _W / 2), the ferroelectric memory cell is read when the selected ferroelectric memory cell is read. "1" by polarization so that
It is characterized by writing information by making it correspond to.

As described above, when writing information, since the writing is performed by the electric field applied between the channel generated directly below the gate electrode 8 and the gate electrode 8, the writing voltage is "0".
There is no unbalance between "1" and "1", and the unselected word line 11 and bit line 10 are set to the second potential (approximately V).
_{Since W} / 2) is set, the conventional 1Tr shown in FIG.
Instability such as erroneous writing in a half-selected cell is not caused unlike the type ferroelectric memory device.

(6) Further, the present invention is the method for driving a ferroelectric memory device according to any one of the above (1) to (3), wherein the plate line 9 and the drive line 12 are set to the ground potential, and , The selected word line 11 is set to the first potential (V _r ) and the selected bit line 10 is set to the first potential side (V _r ) so that the selected ferroelectric memory cell is turned on or off. It is characterized in that the data of the dielectric memory cell is read out by detecting.

In this way, at the time of reading, unlike the conventional 1Tr type ferroelectric memory device shown in FIG. 11, since the plate line 9 is set to the ground potential, an unselected source connected to the bit line 10 The pn junction of one of the drain regions 3 is not forward-biased, and the memory cell operates reliably.

(7) Further, the present invention provides the above (1) to (1).
Driving a ferroelectric memory device according to any one of (3)
In the moving method, the plate line 9 is set to the ground potential, and
The drive line 12 has a first potential (V_r) And select
Of the word line 11 to the first potential (V _r) And select
By selecting the selected bit line 10 to the ground potential side,
Conductivity / non-conduction of the selected ferroelectric memory cell can be detected.
By reading the data of the dielectric memory cell
Features.

With such a configuration, information can be read by a driving method different from the above (6), and the degree of freedom of the driving method is increased.

(8) Further, according to the present invention, the gate insulating films 5 to 5 are
In a ferroelectric memory device in which one field effect transistor type ferroelectric memory cell having a ferroelectric film 7 in a part thereof is arranged in a matrix, a source / drain region 3 of each ferroelectric memory cell is formed. , 4 are provided in a common well region 2 extending in the direction of the bit line 10, the well region 2 and one of the source / drain regions 3 are short-circuited, the well region 2 is used as a drive line, and the gate electrode 8 is formed.
Is provided as a word line 11 and row selection means is provided, and the other 4 of the source / drain regions is commonly connected to the bit line 10.

In this way, the common well region 2 and source
Information can be written by the well region 2 by short-circuiting one of the drain regions 3 and the well region 2 as the drive line 12.
A wiring layer such as an Al wiring layer for No. 2 is not required, the integration degree is improved, and the manufacturing process is simplified.

(9) Further, the present invention is characterized in that, in the above (8), the gate insulating film has a laminated structure of insulating film 5 / floating gate 6 / ferroelectric film 7.

Since the floating gate 6 is provided between the insulating film 5 and the ferroelectric film 7 as described above, it is possible to provide the high-quality ferroelectric film 7 with good reproducibility as in the conventional MFMIS. In addition, when a voltage is applied to the gate electrode 8 to polarize the ferroelectric film 7, a normally-off state having a predetermined threshold value (V _th ) can be stably realized.

(10) Further, in the present invention according to (8) or (9) above, in order to enable trimming of the third potential (V _W ) for writing information in the ferroelectric memory cell for each chip, Third with a polycrystalline semiconductor fuse inside
It is characterized in that a potential (V _W ) trimming means is provided.

As described above, the third potential (V _W ) for writing information in the ferroelectric memory cell can be trimmed on a chip-by-chip basis, so that the ferroelectric memory cell can be erased when data "1" is written. The threshold value (V _th ) can be set stably, and the read margin can be improved.

(11) Further, according to the present invention, in any one of the above (8) to (10), a two-terminal switch element having a metal / dielectric / metal structure is provided between the gate insulating film and the word line 11. It is characterized by being provided.

As described above, by providing the two-terminal switch element of the metal / dielectric / metal structure, that is, the MIM structure between the gate insulating film and the word line 11, the apparent appearance of the ferroelectric thin film 7 is improved. Since the polarization characteristics can be made to have an extremely good squareness ratio, deterioration of the polarization characteristics due to repeated writing operations can be reduced, and therefore erroneous rewriting of information can be prevented.

When writing or reading, MI
Since charges are accumulated in the M layer (metal) between the I layer (dielectric thin film) of the M structure and the ferroelectric thin film 7, immediately after writing or reading, a voltage for extracting the accumulated charges is applied to change the potential. Operation to reset to 0V is required.

(12) Further, the present invention provides all the bit lines 10 and the drive lines 1 in the driving method of the ferroelectric memory device according to any one of the above (8) to (10).
2 and the same potential, and the bit line 10 and all the gate electrodes 8
By applying an erasing voltage (V _E ) between the surface of the semiconductor layer and the surface of the semiconductor layer facing the gate electrode 8,
It is characterized in that all ferroelectric memory cells are polarized so as to be non-conductive and correspond to data "0" to erase information.

By applying the voltage in this manner, the information in all the ferroelectric memory cells can be erased in a lump by a normal erase voltage, so that it is similar to the conventional floating gate transistor type flash memory. Can be operated.

(13) Further, the present invention is the method for driving a ferroelectric memory device according to any one of the above (8) to (10), wherein the bit line 10 and a drive line corresponding to the bit line 10 are provided. 12, the selected bit line 10 is set to the ground potential, the selected word line is set to the third potential (V _W ), and the unselected word line 11 and the bit line 10 are set to the second potential (V _W ). _By setting _W / 2), information is written by polarization so that the ferroelectric memory cell becomes conductive when reading the selected ferroelectric memory cell and corresponding to data "1". And method for driving a ferroelectric memory device.

In this way, as in the case of (5) above, when writing information, writing is performed by the electric field applied between the gate electrode 8 and the channel generated immediately below the gate electrode 8, so that the writing voltage Is not unbalanced between "0" and "1", and the non-selected word line 11 and bit line 10 are set to the second potential (V _W / 2). Unlike the conventional 1Tr type ferroelectric memory device, instability such as erroneous writing does not occur.

(14) Further, the present invention is the method for driving a ferroelectric memory device according to any one of the above (8) to (10), wherein the drive line 12 is set to the ground potential and the selected word line 11 is used. To the first potential (V _r ),
The selected bit line 10 is set to the first potential (V _r ) side, and data of the dielectric memory cell is read by detecting conduction / non-conduction of the selected ferroelectric memory cell.

In this case, the non-selected bit line 10 is floated at the time of reading, but the well region 2 and one of the non-selected source / drain regions 3 are short-circuited. The pn junction of one of the drain regions 3 is not forward-biased, and the memory cell operates reliably.

(15) Further, according to the present invention, in the method for driving a ferroelectric memory device according to any one of the above (11), a positive write voltage or a negative write voltage is applied to the selected cell. It is characterized by operating as a random access memory by writing "1" or "0" corresponding to positive and negative, respectively.

As described above, a positive write voltage is applied to the common well region 2 in which the selected cells extending in the direction of the bit line 10 are provided, and 0 V is applied to the gate electrode 8 to obtain "0". Information can be written at any time, a positive write voltage is applied to the gate electrode of the selected cell, and the same potential (0
Since the information of "1" can be written by the voltage applied between the channel region which is V) and R,
It can be used as an AM (random access memory).

(16) Further, the present invention provides a ferroelectric memory device in which one field effect transistor type ferroelectric memory cell having a ferroelectric film on a part of a gate insulating film is arranged in a matrix. The field-effect transistor is a thin film transistor, and the thin film transistor is a word line serving as a gate electrode extending in a row direction on an insulating substrate,
A gate insulating film provided on the word line, a recrystallized polycrystalline semiconductor layer provided on the gate insulating film, and a source / drain region provided in the polycrystalline semiconductor layer. One of the source / drain regions is formed. It is characterized in that it is commonly connected to a bit line, and the other of the source / drain regions is commonly connected to a drive line extending in the bit line direction.

As described above, by forming the field effect transistor type ferroelectric memory cell by the thin film transistor, a highly integrated semiconductor memory device can be manufactured at low cost, and the word line is formed on the insulating substrate. Since it is provided, a space for word lines is not required, and the degree of integration can be improved as compared with the conventional thin film semiconductor memory device using a thin film transistor.

(17) Also, in the present invention according to the above (16), the overlapping capacitance between the gate electrode and the other of the source / drain regions commonly connected to the drive line is set to the source / drain region commonly connected to the bit line. It is characterized in that it is made larger than the overlapping capacitance between one side and the gate electrode.

Thus, the overlapping capacitance (C _GS ) between the source / drain regions connected to the drive line and the gate electrode
_{Is made} larger than the overlapping capacitance (C _GD ) between the source / drain region connected to the bit line and the gate electrode, so that the electric field applied between the overlapping region of the source / drain region and the gate electrode causes Information of "0" can be easily written.

(18) Further, the present invention is characterized in that, in the above (16) or (17), the gate insulating film has a laminated structure of a ferroelectric film / floating gate / insulating film.

As described above, since the floating gate is provided between the ferroelectric film and the insulating film, when a voltage is applied to the gate electrode to polarize the ferroelectric film, a predetermined threshold value ( V
_a stable normally-off state having a _th ) can be realized, and the heat treatment for recrystallizing the amorphous silicon layer and the heat treatment for forming the source / drain regions in the recrystallized polycrystalline semiconductor layer can enhance the stability. It is possible to prevent the elements forming the dielectric film from diffusing into the recrystallized polycrystalline semiconductor layer.

(19) Further, according to the present invention, in any one of the above (16) to (18), the third potential (V _W ) for writing information in the ferroelectric memory cell can be trimmed for each chip. In addition, a third potential (V _W ) trimming means having a polycrystalline semiconductor fuse is provided in the chip.

As described above, the third potential (V _W ) for writing information in the ferroelectric memory cell can be trimmed on a chip-by-chip basis, so that the ferroelectric memory cell can be erased when data "1" is written. The threshold value (V _th ) can be set stably, and the read margin can be improved.

(20) Further, according to the present invention, in any one of the above (16) to (19), a two-terminal switch element having a metal / dielectric / metal structure is provided between the gate insulating film and the word line. It is characterized by that.

As described above, by providing the two-terminal switch element having the MIM structure between the gate insulating film and the word line, the apparent polarization characteristic of the ferroelectric thin film is made to have an extremely good squareness ratio. Therefore, it is possible to reduce the deterioration of the polarization characteristics due to the repetition of the write operation, and thus to prevent the erroneous rewriting of information.

(21) Further, the present invention is the method for driving a ferroelectric memory device according to any one of the above (16) to (19), wherein all the word lines are set to the ground potential,
In addition, the erase potential (V _E ) is applied to all bit lines and drive lines.
In this way, all the ferroelectric memory cells are polarized so as to be non-conductive and correspond to the data "0" to erase the information.

By applying the voltage in this manner, the information in all the ferroelectric memory cells can be erased at once, so that it can be operated in the same manner as the conventional floating gate transistor type flash memory. it can.

(22) Further, in the present invention, in the method for driving a ferroelectric memory device according to any one of (16) to (19), the bit line and the drive line corresponding to this bit line are the same. Potential, the selected bit line is set to the ground potential, and the selected word line is set to the third potential (V _W ).
And by setting the non-selected word line and bit line to the second potential (V _W / 2), the ferroelectric memory cell is polarized so as to be conductive when the selected ferroelectric memory cell is read. It is characterized in that information is written by associating with data "1".

As described above, when writing information, since writing is performed by the electric field applied between the channel and the word line generated immediately below the word line, the normal writing voltage (V
_W ) makes it possible to write "1", and since the unselected word lines and bit lines are kept at the second potential (V _W / 2), the conventional 1Tr type ferroelectric substance shown in FIG. Unlike the memory device, instability such as erroneous writing does not occur.

(23) Further, the present invention is the method for driving a ferroelectric memory device according to any one of the above (16) to (19), wherein all the drive lines are set to the first potential (V).
_r ), the selected word line is set to the first potential (V _r ), the selected bit line is set to the ground potential side, and conduction / non-conduction of the selected ferroelectric memory cell is detected to detect the dielectric memory. It is characterized in that the cell data is read.

In this case, since the channel generated immediately below the word line is used for reading, stable reading is possible.

(24) Further, the present invention is the method for driving a ferroelectric memory device according to any one of the above (16) to (19), wherein the drive line is set to the ground potential and the selected word line is set to the first potential. while the first potential (V _r), and the selected bit line to a first potential (V _r) side, reads the data of the ferroelectric memory cell by sensing the conduction and non-conduction of the ferroelectric memory cell selected A method of driving a ferroelectric memory device, comprising:

With such a structure, it becomes possible to read information even by a driving method different from the above (23), and the degree of freedom of the driving method is increased.

(25) According to the present invention, in the method for driving a ferroelectric memory device according to the above (20), a positive write voltage or a negative write voltage is applied to selected cells, respectively. It is characterized in that it operates as a random access memory by writing "1" or "0" depending on whether it is positive or negative.

As described above, a positive write voltage is applied to the drive line of the selected cell and 0 V is applied to the gate electrode, and the other of the source / drain regions connected to the drive line overlaps with the gate electrode. Information of "0" can be written at any time by the electric field applied to the region, and
Apply a positive write voltage to the gate electrode of the selected cell,
Moreover, since the information of "1" can be written by the voltage applied between the selected bit line and the channel region having the same potential (0 V), the RAM (random.
Access memory).

[0098]

DETAILED DESCRIPTION OF THE INVENTION A ferroelectric memory device according to a first embodiment of the present invention will be described with reference to FIGS. 2A is a cross-sectional view of a main part of the memory cell structure, FIG. 2B is a schematic configuration diagram of a plane pattern of the memory cell, and FIG. 3 is the first embodiment. 5 is an explanatory diagram of operating characteristics of the ferroelectric memory cell of FIG. 4, FIG. 4 is an explanatory diagram of write operation in the first embodiment, and FIG. 5 is a read operation in the first embodiment. FIG.

First, the p-type well region 2 common to the n-type silicon substrate 21 is referred to.
2 is formed, and then a SiO ₂ film having a thickness of 100 Å to 300 Å, preferably 250 Å, and a thickness of 150 to be a floating gate.
A Pt film having a thickness of 0Å to 3000Å, preferably 2000Å, a PZT thin film having a thickness of 1000Å to 7000Å as a ferroelectric film, preferably 4000Å, and a conductive film such as Pt are sequentially deposited and then patterned. SiO
_A gate insulating film made of the ₂ film 25, the Pt film 26, and the PZT thin film 27, and a plurality of gate electrodes 28 are formed so as to be arranged in the column selection line direction. Note that only one is shown in the figure.

Next, using the gate electrode 28 as a mask, A
An n-type impurity such as s is selectively introduced to form an n-type drain region 23 and an n-type source region 24, a plate line (T) 29 is formed in the p-type well region 22, and a bit line is formed in the n-type source region 24. (BL) 30, the word line (WL) 31 in the gate electrode 28, and the drive line (D) arranged in the n-type drain region 23 in parallel with the bit line (BL) 30.
32 are connected to each other to complete the ferroelectric memory cell.

See FIG. 2B. This ferroelectric memory cell is provided in mirror symmetry.
Each bit line (BL ₀, BL₁・ ・) 30 is a column
Sense amplifier 36 connected via multiplexer 35
Have been. The sense amplifier 36 is a ferroelectric
P-well region formed at the same time as the body memory cell formation process
The region 22 serves as a base region and the n-type drain regions 23 and n
The type source region 24 is used as an emitter region and a collector region.
It is formed as a lateral bipolar transistor.

The plate line (T) 29 is connected to a means for applying an erase voltage (V _E ), and each drive line (D ₀ , D ₁ ...) 32 is connected to a drive line by a transistor 33. Is connected to the bit line (BL ₀ , BL ₁ ...) 30 corresponding to (D ₀ , D ₁ ...) 32,
Depending on the voltage applied to the gate of the transistor 33, it is made to have the same potential as the bit lines (BL ₀ , BL ₁ ...) 30 or separated.

Further, each word line (WL ₀ , WL ₁ ...)
31 is the ground potential, the first of 1.65V (V _CC / 2)
It is connected to the row selecting means, that is, the row multiplexer 34, which applies the potential (V _r ) or the third potential (V _W ).

See FIGS. 3A and 3B. FIG. 3A is an explanatory diagram of the operating characteristics of the ferroelectric cell.
3B is an explanatory diagram of polarization with respect to an applied electric field inside the ferroelectric thin film. First, a high potential is applied to the gate of the transistor 33 to short-circuit the bit line (BL) and the drive line (D). Then, all bit lines (BL) and drive lines (D) are brought into a floating (floating) state, the erase voltage V _E is applied to the plate line (T), and all the word lines (WL) are set to the ground potential. By applying the voltage to make the ferroelectric memory cell non-conducting and reversing the polarization of the PZT thin film 27 in the -Pr direction to correspond to the data "0", all the ferroelectric memory like the floating gate transistor type flash memory. The information in the body memory cells is erased collectively.

In this case, the surface of the p-type well region 22 just below the gate electrode 28 is in an accumulated state, and the applied voltage is applied to the PZT thin film 27 as it is, so that the information is erased by the normal erase voltage (V _E ). can do.

Next, when writing the data "1", a high potential is applied to the gate of the transistor 33 with the plate line (T) at the ground potential. Bit line (BL) and drive line (D) are short-circuited, 0 V (ground potential) is applied to the selected bit line (BL) and drive line (D), and
The third potential (V _W ) is applied to the selected word line (WL) to write the data “1” in the selected ferroelectric memory cell.

In this case, a channel region (not shown) is provided immediately below the gate electrode in a state where a voltage is applied to the word line.
Is formed, and this channel region has the same potential as the source / drain regions, that is, the short-circuited bit line (BL) and drive line (D), so that V _W is applied to the gate electrode in the selected cell. And the channel area is 0V
Then, the ferroelectric thin film is polarized by the potential difference V _W , and data “1” is written in the ferroelectric memory cell.

The second word line (WL) not selected is not
Applying a potential (V _W / 2), and, in the non-selected bit line (BL) and the drive line (D) a second potential (V _W /
Since 2) is applied, the writing of data "1" to the non-selected or half-selected cells is prohibited.

This third potential (V _W ) is applied to the PZT thin film 27 so that the memory cell output becomes "1" at the time of reading.
Is a potential polarized by + Pr ^* in the + Pr direction, and the memory cell polarized by + Pr ^* is in a normally-off state in which the threshold value (V _th ) is lowered to the extent of conduction when a read potential is applied.

Since the bias is applied in this manner, the reverse electric field is not applied to the half-selected cells, and the polarization characteristics are not deteriorated even if the write or read operation is repeated, so that the written data is written. Is never destroyed.

When writing "1", the electric field applied between the gate electrode 28 and the channel region is used, and the electric field between the gate electrode 28 and the plate line 29 is not used. It is possible to avoid a large increase in the write voltage due to.

Further, third potential generating means provided with a trimming means made of a polycrystalline silicon fuse is provided in a chip constituting the ferroelectric memory device so that the third potential (V _W ) can be trimmed. As a result, the third potential can be arbitrarily set for each chip according to the memory cell characteristics, and the read margin can be improved.

5 (a) and 5 (b) Next, when reading information, the plate line (T) is set to the ground potential, and a low potential is applied to the transistor 33 to set the bit line (BL) and In a state where the drive line (D) is separated, all the drive lines (D) are set to the ground potential, the selected bit line (BL) is set to the first potential (V _r ) side via the detection resistor 37, and A first potential (V _r ) first potential is applied to the selected word line (WL). In this case,
The unselected bit line (BL) is floated and the unselected word line (WL) is set to 0V.

In this case, when "1" is written in the memory cell, the memory cell becomes conductive by the application of the first potential (V _r ) which is the read voltage, and the potential of the bit line (BL). Variations in sense amplifier 36
Information is detected via. In addition, "1" is set to the memory cell.
Is not written, that is, when the data in the memory cell is "0", the memory cell does not conduct, so that no potential change occurs.

Also, in this case, in this case, the reverse electric field of V _r / 2 or V _r is applied to the non-selected cells or the semi-selected cells. As is apparent from FIG. 5A, the reverse electric field is applied only to the overlapping portion of the word line 31 serving as the gate electrode and the n-type source region 24.
As is clear from (a), since V _r ≤V _W / 2, even if a reverse electric field is applied, as shown in FIG. 3B, the influence is small and the written data may be destroyed. Since it does not exist, the memory cell operates reliably.

Further, another reading method is possible in the ferroelectric memory device of the first embodiment. That is, with the plate line (T) at the ground potential, and the low potential is applied to the transistor 33 to separate the bit line (BL) and the drive line (D), all the drive lines (D) are set to the first potential. The potential (V _r ) is set, the selected bit line (BL) is set to the ground potential side through the detection resistor 37, and the first potential (V _r ) first potential is applied to the selected word line (WL). In this case, the unselected bit lines (BL) are floated and the unselected word lines (WL) are
To 0V.

In this case, when "1" is written in the memory cell, the memory cell becomes conductive by applying the read voltage V _r , and the sense amplifier is turned on by the potential change of the bit line (BL). When information is detected via the memory cell and "1" is not written in the memory cell, the memory cell does not conduct, so that no potential fluctuation occurs.

The ferroelectric memory device of the first embodiment has a high degree of integration and is stable in operation because the reverse electric field is not applied to the non-selected cells or the half-selected cells during the write operation. It is useful for low density file memory with high integration.

In the above description of the first embodiment, the Pt film 26 as the floating gate is provided, but providing the Pt film 26 improves the quality of the PZT thin film 27 provided thereon. In addition, the memory cell can be brought into a low threshold normally-off state with good reproducibility, but this is not always necessary, and the PZ film is formed on the SiO ₂ film 25.
The T thin film 27 may be directly provided.

A cell structure of the ferroelectric memory device according to the second embodiment of the present invention using a common well region extending in the bit line direction will be described with reference to FIG. 6A is a cross-sectional view of a main part of the memory cell structure, and FIG. 6B is a schematic configuration diagram of a plane pattern of the memory cell.

Referring to FIG. 6A, first, a common p-type well region 22 extending in the column selection line direction is formed on the n-type silicon substrate 21 similarly to the bit line (BL) 30.
And then a thickness 10 is formed as in the first embodiment.
0 Å to 300 Å, preferably 250 Å SiO ₂ film, thickness of 1500 Å to 3000 Å to be a floating gate, preferably 2
000Å Pt film, thickness 1000Å as a ferroelectric film
.About.7000 Å, preferably 4000 Å, PZT thin film and conductive film such as Pt are sequentially deposited and then patterned to form a gate insulating film and a gate made of a SiO ₂ film 25, a Pt film 26 and a PZT thin film 27. An electrode 28 is formed in each p-type well region 22.

Next, using the gate electrode 28 as a mask, A
An n-type impurity such as s is selectively introduced to form the n-type drain region 23 and the n-type source region 24, and the p-type well region 22 and the n-type drain region 23 are electrically short-circuited to p
The type well region 22 is used as a drive line (D) 32, and
A word line (WL) 31 is connected to the gate electrode 28 and a bit line (BL) 30 is connected to the n-type source region 24, respectively, to complete a ferroelectric memory cell.

See FIG. 6B. This ferroelectric memory cell has bit lines (BL ₀ , BL
_A sense amplifier 36 is connected to the ₁ ...) 30 via a column multiplexer 35. The sense amplifier 36 uses the p-type well region 22 formed at the same time as the step of forming the ferroelectric memory cell as a base region, and the n-type drain region 23 and the n-type source region 24 as an emitter region and a collector region. It is formed as a lateral bipolar transistor.

Further, each drive line (D ₀ , D ₁ ...) 3
Reference numeral 2 is connected to a means for applying an erase voltage (V _E ) via the p-type well region 22, and each drive line (D
₀ , D ₁ ··· 32 is connected to the bit line (BL) corresponding to the drive line (D ₀ , D ₁ ··) 32 by the transistor 33.
₀ , BL ₁ ...) 30 and is applied to the bit line (BL
₀ , BL ₁ ···) 30 and the same potential, or separated.

Further, each word line (WL ₀ , WL ₁ ...)
Reference numeral 31 is connected to a row selection means, that is, a row multiplexer 34 for applying the ground potential, the first potential (V _r ) or the third potential (V _W ), respectively.

In this case, since the stripe-shaped p-type well region 22 is used as the drive line (D) and the plate line (T), a separate Al wiring layer space for the drive line (D) is unnecessary. As the degree of integration increases,
Since the Al wiring layer can be omitted, the manufacturing process is simplified.

Next, referring to FIG. 6B as well, a method of driving the ferroelectric memory device according to the second embodiment will be described. The operation characteristics of the ferroelectric memory cell of the second embodiment are basically the same as the operation characteristics of the ferroelectric memory cell of the first embodiment.

First, a high potential is applied to the gate of the transistor 33 to short-circuit the bit line (BL) and the drive line (D), and the erase voltage V _E is applied to all bit lines (BL). By applying the ground potential to all the word lines (WL) to make the ferroelectric memory cells non-conductive, the PZT thin film 27 is polarization-inverted in the -Pr direction to correspond to the data "0". In the same way as the floating gate transistor type flash memory, the information in all the ferroelectric memory cells is erased collectively.

In this case as well, the surface of the p-type well region 22 immediately below the gate electrode 28 is in an accumulated state, and the applied voltage is applied to the PZT thin film 27 as it is, so that information can be obtained by the normal erase voltage (V _E ). Can be erased.

Next, when writing the data "1",
By applying a high potential to the gate of the transistor 33, the bit line (B
L) and drive line (D) are short-circuited and the selected bit
Apply the ground potential to the line (BL) and select the selected wire.
The third potential (V _W) Is applied to select the strong
Data "1" is written in the dielectric memory cell. In addition, selection
1. For the bit line (BL) and word line (WL) that are not selected,
65V second potential (V_W/ 2) is applied.

The content of the third potential is substantially the same as that of the first embodiment, and is the same in that the trimming means is provided, and the write operation is stabilized or written. With respect to the data destruction prevention, the same effect as that of the first embodiment can be obtained.

When writing "1", the electric field applied between the gate electrode 28 and the channel region is used, and the electric field between the gate electrode 28 and the p-type well region 22 is not used. It is possible to avoid a large increase in the write voltage due to the inversion layer.

Next, when reading information, all drive lines (D) are grounded with a low potential applied to the transistor 33 to separate the bit line (BL) and drive line (D). Then, the selected bit line (BL) is set to the first potential (V _r ) side through the detection resistor 37, and the first potential (V _r ) is applied to the selected word line (WL). In this case, the unselected bit lines (BL) are floated and the unselected word lines (WL) are
To 0V.

The information detection principle in this case is the same as that of the first embodiment, and the non-selected bit line (BL) is floated at the time of reading, but the p-type well region 22 and Since the non-selected n-type drain region 23 is short-circuited, the pn junction of the non-selected n-type drain region 23 is not forward-biased, and the memory cell operates reliably.

Since the ferroelectric memory device of the second embodiment also has a high degree of integration and stable operation, it has a high degree of integration and a low speed like the ferroelectric memory device of the first embodiment. It is useful for file memory.

Although the Pt film 26 as the floating gate is provided also in the description of the second embodiment, providing the Pt film 26 improves the quality of the PZT thin film 27 provided thereon. and, and, although the memory cell can be normally-off state of good reproducibility low threshold, not always necessary, PZ on the SiO ₂ film 25
The T thin film 27 may be directly provided.

In the description of the driving method according to the second embodiment, a flash memory-like driving method for collectively erasing information is described. However, in the case of the cell structure according to the second embodiment. It is also possible to make the RAM operate like a RAM.

See FIG. 6B. That is, when writing "1" information is the same as the flash memory driving method, but when writing "0" information at any time, the gate of the transistor 33 is to be written. A high potential is applied to short-circuit the bit line (BL) and the drive line (D), and the third potential (V _W ) is applied to the selected bit line (BL), that is, the drive line (D), and at the same time selected. The ground potential is applied to the selected word line (WL), and the voltage V _W applied between the gate electrode 28 and the p-type well region 22 short-circuited with the drive line (D) causes the selected ferroelectric memory. Write data "0" to the cell.

By biasing in this way,
Since the data "0" can be written at any time to the ferroelectric memory cell in which "1" has been written by the normal write voltage V _W , a RAM-like operation becomes possible.
In addition, unselected bit lines (BL) and word lines (W
The second potential (V _W / 2) is applied to L). However, since a reverse voltage is applied to the half-selected cell, it is necessary to devise it.
This will be described later.

Next, with reference to FIG. 7, a ferroelectric memory device using a thin film semiconductor layer according to a third embodiment of the present invention will be described. Note that FIG. 7A is a cross-sectional view of a main part of the memory cell, and FIG. 7B is a schematic configuration diagram of a plane pattern of the memory cell.

Referring to FIG. 7A, first, an S film having a thickness of 1000 to 3000 Å, preferably 2000 Å, formed on the quartz substrate 41 by the sputtering method.
A Ti film having a thickness of 500 to 1500Å, preferably 1000Å, and a thickness of 1500 to 3000 through the iO ₂ film 42.
A word line 43 extending in the row selection line direction is formed by depositing a Pt film of Å, preferably 2000 Å and patterning it.

Next, the thickness 1 as a ferroelectric film is formed on the entire surface.
000 Å to 7,000 Å, preferably 4000 Å PZT thin film, and a thickness of 1500 Å to 3000 to be a floating gate
The PZT thin film 44 and the floating gate 45 are formed by depositing a Pt film of Å, preferably 2000 Å and then patterning.

Next, after depositing an insulating film having a thickness of 500Å to 1500Å, preferably 1000Å, which is made of a SiO ₂ film or the like on the entire surface, a thickness of 500Å to 1500Å is deposited thereon.
Preferably, an amorphous silicon film having a thickness of 800 Å is deposited, and the amorphous silicon film is recrystallized by laser annealing to be converted into a polycrystalline silicon film.

Then, the polycrystalline silicon film is patterned to form an island-shaped i which constitutes a pair of mirror-symmetric memory cells.
After forming the type polycrystalline silicon region 47, a channel protection film 48 is formed by depositing and patterning a silicon nitride film on the entire surface.

Next, an n-type impurity such as As is selectively introduced by using the channel protective film 48 as a mask to form an n ⁺ -type source region 49 and an n ⁺ -type drain region 50. 3000Å, preferably 1000
Polycrystalline silicon pads 51 and 52 are formed by depositing and patterning an n ⁺ -type polycrystalline silicon film of Å.

In this case, the channel protection film 48 is formed by
Provided near the ⁺ type drain region 50, the n ⁺ type source region 49 and the word line 43 serving as a gate electrode are overlapped with each other by n
⁺ Type drain region 50 and word line 43 to be a gate electrode
To be larger than the overlap with, that is, n
It is desirable that the parasitic capacitance C _GS of the ⁺ type source region 49 be larger than the parasitic capacitance C _{GD of the} n ⁺ type drain region 50.

Next, although not shown, the entire surface is PCV
SiO ₂ film is deposited by D method (plasma CVD method),
After forming an opening for electrode formation, WSi is formed on the entire surface.
By depositing a conductive film such as the above and then patterning, a bit line (BL) 53 and a drive line (D) 54 which are connected to the polycrystalline silicon pads 51 and 52 and extend in the same column direction are formed.

See FIG. 7B. This ferroelectric memory cell is provided in mirror symmetry.
Each bit line (BL ₀, BL₁・ ・) 53
Although not present, the column selection transistor and the first potential (V_r)
The sense amplifier is connected through a sense resistor connected to
Have been. This sense amplifier is a ferroelectric memory.
N-channel thin film transistor formed at the same time as the process of forming the resell
It is configured using a register.

As described above, since the ferroelectric memory cell is constructed by using the thin film semiconductor layer whose manufacturing technique is established in the active matrix type liquid crystal display device, the cost can be reduced and the word can be obtained. Since the line (WL) is provided on the side of the quartz substrate 41, a separate wiring space for the word line (WL) is not needed, and the degree of integration is improved.

The driving method of this ferroelectric memory device is
And FIG. 7 (b). See FIG. 7B. First, a high potential is applied to the gate of a transistor (not shown).
And short-circuited the drive line (D) and the bit line (BL)
In this state, erase voltage V is applied to all bit lines (BL). _EApply
And apply the ground potential to all word lines (WL)
To make the ferroelectric memory cell non-conductive, and to remove the PZT thin film 27.
Polarization is inverted in the -Pr direction to correspond to data "0"
By the floating gate transistor type
All ferroelectric memory cells as well as flash memory
Delete all information in batch.

[0151] In this case, since the impurity concentration of the n ⁺ -type source region 49 is very high, n ⁺ -type inversion layer on the surface of the source region 49 is not formed, n ⁺ -type source voltage applied to region 49 as it is Since it is applied to the PZT thin film 44, information can be erased by the normal erase voltage V _E.

Next, when writing data "1", a high potential is applied to the gate of a transistor (not shown) to short-circuit the bit line (BL) and drive line (D), and the selected bit line (BL) is connected. While applying the ground potential, the third potential (V _W ) is applied to the selected word line (WL) to write the data “1” in the selected ferroelectric memory cell. Note that unselected bit lines (BL) and word lines (WL)
The second potential (V _W / 2) is applied to the.

The third potential (V _W ) is applied to the PZT thin film 44 so that the memory cell output becomes "1" at the time of reading.
Is a potential polarized by + Pr ^* in the + Pr direction, and the memory cell polarized by + Pr ^* is in a normally-off state in which the threshold value (V _th ) is lowered to the extent of conduction when a read potential is applied.

Also in this case, the third potential generating means provided with the trimming means made of a polycrystalline silicon fuse is provided in the chip constituting the ferroelectric memory device so that the third potential (V _W ) can be trimmed. By providing the third potential, the third potential can be arbitrarily set according to the memory cell characteristics for each chip, and thus the read margin can be improved.

Also in this case, when writing "1", the electric field applied between the word line 43 serving as the gate electrode and the channel region is used, and the word line 43 and the i-type polycrystalline silicon region 47 are used. Since the electric field applied between and is not used, a large increase in the write voltage due to the inversion layer can be avoided.

Next, when reading information, all the drive lines (D) are separated with the bit line (BL) and the drive line (D) separated by applying a low potential to the gate of a transistor (not shown). Is set to the ground potential, the selected bit line (BL) is set to the first potential (V _r ) side through the detection resistor, and the first potential (V _r ) is applied to the selected word line (WL). In this case, the unselected bit lines (BL) are made floating and the unselected word lines (WL) are set to 0V.

The principle of information detection in this case is similar to that of the first embodiment, and V _r applied to the half-selected cells is the same.
Since the reverse electric field of / 2 is very small, there is no problem of erroneous rewriting accompanying the read operation.

Further, another reading method is possible in the ferroelectric memory device of the third embodiment. That is, a low potential is applied to the gate of a transistor (not shown) to separate the bit line (BL) and the drive line (D),
All the drive lines (D) are set to the first potential (V _r ), the selected bit line (BL) is set to the ground potential side via the detection resistor, and the selected word line (WL) is set to the first potential (V _r ). _r ) is applied. In this case, the unselected bit lines (BL) are made floating and the unselected word lines (WL) are set to 0V.

When the ferroelectric memory device of the third embodiment is designed according to the rule of 0.5 μm, the size of the memory cell is set to 1.5 × 3 μm to obtain 16 Mb.
6 x 12m semiconductor memory device for it's main memory
It can be realized with a chip area of m.

In the above description of the third embodiment, the Pt film as the floating gate 45 is provided,
Although the memory cell can be brought into a normally-off state with a low threshold value with good reproducibility, the i-type polycrystalline silicon region 47 serving as an operating region is formed after the PZT thin film 44 is formed, and the PZT thin film 44 serves as a channel of the device. It is not necessary because it has little effect on the interface.
The insulating film 46 may be directly provided on the T thin film 44.

Also, in the description of the third embodiment described above, a flash memory-like driving method for collectively erasing information is described. However, even in the case of the cell structure of the third embodiment, a RAM is also used. It is also possible to perform a specific operation.

See FIG. 7B. That is, when writing "1" information, it is the same as the flash memory driving method, but when writing "0" information at any time, the gate of a transistor (not shown) is shown. To the bit line (BL) and the drive line (D) by applying a high potential to the selected bit line (BL), that is, the drive line (D), and the third potential (V _W ) A ground potential is applied to the selected word line (WL), and the voltage V _W is applied to the overlapping portion of the n ⁺ type source region 49 connected to the drive line (D) and the word line 43 serving as the gate electrode. , Write data "0" in the selected ferroelectric memory cell.

[0163] In this case, since the impurity concentration of the n ⁺ -type source region 49 is very high, n ⁺ -type inversion layer on the surface of the source region 49 is not formed, n ⁺ -type source voltage applied to region 49 as it is Since it is applied to the PZT thin film 44, data "0" can be written at any time to the ferroelectric memory cell in which "1" has been written by the normal write voltage V _W , so that it is like a RAM. It becomes possible to operate. The second potential (V _W / 2) is applied to the unselected bit line (BL) and word line (WL).

Although the first to third embodiments have been described above, in particular, in the case of operating like a RAM, FIG.
Similar to the improved ferroelectric memory device shown in 5, the "1"
Also, as the write operation of "0" is repeated, the problem that the information is rewritten by mistake occurs. This situation will be described with reference to FIG.

8 (a) and 8 (b) As shown in FIG. 8 (b), the polarization characteristics of the ferroelectric thin film shown by the solid line are the ideal polarization characteristics with good squareness shown by the broken line. Since they are different, as shown in FIG. 8A, the half-selected voltage is alternately applied to the half-selected memory cells at the time of writing, and the movement is repeated so as to attenuate on the history curve, and finally, , The information in the memory cell in which "1" was written is erased. The same applies to the memory cell in which the information "0" is written.

If this hysteresis curve is made to have an ideal characteristic indicated by a broken line, the polarization value hardly changes at the half-selected voltage applied to the half-selected cell, so that the polarization characteristic deteriorates as the writing is repeated and an erroneous value is generated. There is almost no possibility of writing.

In order to obtain such ideal characteristics, as shown in the conventional example of FIG. 15, a two-terminal switch element is provided between the ferroelectric thin film and the word line and the history curve is set. Should be shifted to the plus and minus sides. In this case, the read voltage needs to be slightly lower than the voltage V which is the sum of the coercive voltage V _c and the ON voltage V _on of the two-terminal switch element. According to the first to third embodiments of the invention, a high voltage is required by the ON voltage V _on of the two-terminal switch element.

As such a two-terminal switch element, MIM
The element is used in the fourth embodiment of the present invention shown in FIG. See FIG. 9. The ferroelectric memory cell shown in FIG.
The Ta electrode 61 and the Ta ₂ O ₅ thin film 6 are formed on the gate electrode 28 of the ferroelectric memory cell of the second embodiment shown in FIG.
2 and the MIM element composed of the Ta electrode 63 is deposited, and other configurations are exactly the same as those of the second embodiment.

The ON voltage of the MIM element in this case
V_onIs Ta_TwoO_FiveON voltage depends on the thickness of the thin film 37
V_onAbout 1.5 to 5.0V, at least the coercive voltage
(V _C) Is desirable, and this on-voltage V_onWrite only minutes
Higher voltage and read voltage, but applied to half-selected cells
Half selection voltage (V_W/ 2 or V_rIn / 2)
Repeated writing because the polarization value hardly changes
Poor writing characteristics may deteriorate, resulting in erroneous writing.
Is almost gone.

When the MIM element is provided, Ta or I layer of the MIM element is used for writing or reading.
_Since charges are accumulated in the Ta electrode between the ₂ O ₅ thin film 37 and the PZT thin film 27, it is necessary to apply a voltage V _Re for drawing out the accumulated charges and reset the potential to 0 V immediately after writing or reading. Is.

In the fourth embodiment, MI
Although the M element is provided between the PZT thin film 27 and the gate electrode 28, the gate electrode 28 is omitted and the Ta film 61, the Ta ₂ O ₅ thin film 62, and the Ta film are directly formed on the PZT thin film 27.
The film 63 may be laminated, but it is necessary to consider mutual diffusion between the PZT thin film 27 and the Ta film 61.

Next, FIG. 10 illustrates a fifth embodiment of a thin film semiconductor type ferroelectric memory device having an MIM element according to the third embodiment of the present invention. See FIG. 10. In the case of the fifth embodiment, T is formed under the Pt film 65 corresponding to the word line in the third embodiment.
a electrode 61, Ta ₂ O ₅ thin film 62, and Ta electrode 63
The MIM element is formed, and the word line 43 is further provided below the MIM element.

The driving method in the fifth embodiment is also substantially the same as the driving method in the third embodiment, and MI
Although the write voltage and the read voltage are increased by the ON voltage V _on of the M element, the polarization value hardly changes at the half-selection voltage applied to the half-selection cell. There is almost no possibility of deterioration and erroneous writing.

Incidentally, in the above-mentioned first to fifth embodiments,
In the description, an n-channel type memory cell is used.
However, a p-channel type memory cell may be used.
Each line is marked as the conductivity type of the channel changes.
The applied potential is the third potential (V _W) And the first potential (V_r)
Is to the ground potential, and the ground potential is the third potential (V_W)
Is the first potential (V_r) Needs to be changed.

Further, in the fourth and fifth embodiments, the word line is provided on the quartz substrate 41, but a recrystallized polycrystalline silicon film is provided on the quartz substrate 41, and the insulating film 46 is provided thereon. , The floating gate 45, the PZT thin film 44, and the conductive film may be sequentially deposited and patterned to form the word line serving as the gate insulating film and the gate electrode. The degree improves.

Further, in the description of the fourth and fifth embodiments,
In this case, the quartz substrate 41 is used as the substrate.
SiO by CVD method_TwoThe film 42 is provided, but S
iO _TwoMembrane 42 is not necessary and is
The plate is not limited to the quartz substrate, but may be made of sapphire or the like.
Other insulating substrates may be used as well as silicon substrates.
Using an insulative substrate with an oxide film on its surface by thermal oxidation of
Is also good, and in this specification, various types of such
The substrate is called an insulating substrate.

Further, although PZT is used as the ferroelectric thin film in each of the above-mentioned embodiments, it is not limited to PZT, and PLZT, BaTiO ₃ , PbTi.
Other ferroelectric materials such as O ₃ or Bi ₄ Ti ₃ O ₁₂ may be used.

Further, although Pt is used as the floating gate in the above-mentioned respective embodiments, polycrystalline silicon may be used. However, when polycrystalline silicon is used as the floating gate, it is difficult to directly deposit PZT on the polycrystalline silicon film. Therefore, if PZT is deposited on the polycrystalline silicon film via the IrO ₂ film. Well, by using polycrystalline silicon as the floating gate, the interface state of the gate SiO ₂ is improved, and the manufacturing yield and reproducibility are improved (Electronic Material, p27-32, 199).
See August 4).

The two-terminal switch element in the fourth and fifth embodiments is an MIM element composed of the Ta electrode 36, the Ta ₂ O ₅ thin film 37, and the Ta electrode 38. Not limited to materials, other MI
Various materials known as the constituent material of the M element can be used, and further, it is not necessary to be the MIM element, and any switch element having a characteristic of connecting a diode in anti-series may be used.

Further, in each of the above embodiments, a silicon substrate or a polycrystalline silicon film is provided as a semiconductor, but the invention is not limited to silicon, and other group IV semiconductors such as SiGe mixed crystal or GaAs or the like. The III-V group compound semiconductor may be used.

[0181]

According to the present invention, a memory cell is composed of one MISFET having a ferroelectric gate insulating film, and the erase voltage and the write voltage are unbalanced during information erasing and information writing. Since it is a driving method that eliminates the above, it is possible to provide a 1Tr type ferroelectric memory device and a driving method thereof, in which the degree of integration is improved, the driving operation is stable, and a reliable memory operation is possible. A stable RAM (Andam access memory) can be provided by adding the MIM element.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a principle configuration of the present invention.

FIG. 2 is an explanatory diagram of a cell structure according to the first embodiment of this invention.

FIG. 3 is an explanatory diagram of operating characteristics according to the first embodiment of this invention.

FIG. 4 is an explanatory diagram of a write operation according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram of a read operation according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram of a cell structure according to a second embodiment of this invention.

FIG. 7 is an explanatory diagram of a third embodiment of the present invention.

FIG. 8 is an explanatory diagram of problems in the first to third embodiments of the present invention.

FIG. 9 is an explanatory diagram of a cell structure according to a fourth embodiment of this invention.

FIG. 10 is an explanatory diagram of a cell structure according to a fifth embodiment of the present invention.

FIG. 11 is an explanatory diagram of a conventional 1Tr type ferroelectric memory cell.

FIG. 12 is an explanatory diagram of another conventional 1Tr type ferroelectric memory cell.

FIG. 13 is an explanatory diagram of a conventional MFMIS type ferroelectric memory cell.

FIG. 14 is an explanatory diagram of a conventional improved ferroelectric memory cell.

FIG. 15 is an explanatory diagram of another conventional improved ferroelectric memory cell.

[Explanation of symbols]

1 semiconductor substrate 2 well region 3 source / drain region 4 source / drain region 5 insulating film 6 floating gate 7 ferroelectric film 8 gate electrode 9 plate line 10 bit line 11 word line 12 drive line 21 n-type silicon substrate 22 p-type Well region 23 n-type drain region 24 n-type source region 25 SiO ₂ film 26 Pt film 27 PZT thin film 28 gate electrode 29 plate line 30 bit line 31 word line 32 drive line 33 transistor 34 row multiplexer 35 column multiplexer 36 sense amplifier 37 detecting resistor 41 a quartz substrate 42 SiO ₂ film 43 word lines 44 PZT thin film 45 floating gate 46 insulating film 47 i-type polycrystalline silicon region 48 channel protective film 49 n ⁺ -type source region 50 n ⁺ -type drain region 51 of polycrystalline Shirikonpa De 52 polysilicon pad 53 bit lines 54 drive lines 61 Ta film 62 Ta ₂ O ₅ thin film 63 Ta film 64 CVD oxide film 65 Pt film 81 p-type well region 82 n ⁺ -type drain region 83 n ⁺ -type source region 84 Strong Dielectric thin film 85 Gate electrode 86 Bit line 87 Word line 88 Plate line 89 Ferroelectric memory cell 90 Word selection decoder / driver 91 Plate selection decoder / driver 92 Sense amplifier 93 Reference line 94 Source extraction electrode 95 SiO ₂ film 96 Floating Gate 97 Drive line 98 2-terminal switch element

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 29/792

Claims (25)

[Claims] 1. In a ferroelectric memory device in which one field effect transistor type ferroelectric memory cell having a ferroelectric film on a part of a gate insulating film is arranged in a matrix, common source / drain regions are provided. In the well region, and connecting the well region to the plate line,
Row selection means is provided using the gate electrode as a word line, and one of the source / drain regions is commonly connected to the bit line, and the other of the source / drain regions is a drive line extending in the bit line direction. A ferroelectric memory device characterized by being commonly connected. 2. The ferroelectric memory device according to claim 1, wherein the gate insulating film has a laminated structure of insulating film / floating gate / ferroelectric film. 3. A third semiconductor device provided with a polycrystalline semiconductor fuse in each chip so that a third potential for writing information in the ferroelectric memory cell can be trimmed chip by chip.
2. A potential trimming means is provided, wherein
Alternatively, the ferroelectric memory device according to item 2. 4. The method for driving a ferroelectric memory device according to claim 1, wherein an erase voltage is applied between the plate line and the gate electrode, and the erase voltage is opposed to the gate electrode. By setting the surface of the semiconductor layer to be in a storage state, all the ferroelectric memory cells are polarized so as to be non-conductive and correspond to data "0", thereby erasing information. Driving method for dielectric memory device. 5. The method for driving a ferroelectric memory device according to claim 1, wherein the plate line is set to the ground potential, the selected word line is set to the third potential, and selected. By setting the bit line and the drive line to the ground potential and setting the unselected word line, bit line, and drive line to the second potential, the ferroelectric memory cell is read when the selected ferroelectric memory cell is read. A method of driving a ferroelectric memory device, wherein information is written by polarization so that the body memory cell becomes conductive and corresponding to data "1". 6. The method of driving a ferroelectric memory device according to claim 1, wherein the plate line and the drive line are set to a ground potential, and the selected word line is set to a first potential. At the same time, the selected bit line is set to the first potential side, and data of the dielectric memory cell is read by detecting conduction / non-conduction of the selected ferroelectric memory cell. Driving method. 7. The method of driving a ferroelectric memory device according to claim 1, wherein the plate line is set to a ground potential and the drive line is set to a first potential, and the selected word is selected. The data is read from the dielectric memory cell by detecting the conduction / non-conduction of the selected ferroelectric memory cell by setting the line to the first potential and setting the selected bit line to the ground potential side. Method for driving a ferroelectric memory device. 8. A ferroelectric memory device in which one field effect transistor type ferroelectric memory cell having a ferroelectric film as a part of a gate insulating film is arranged in a matrix, wherein each of the ferroelectric memories is a ferroelectric memory device. The source / drain region of the cell is provided in a common well region extending in the bit line direction, one of the well region and the source / drain region is short-circuited, and the well region is used as a drive line, and
A ferroelectric memory device characterized in that row selection means is provided with the gate electrode as a word line, and the other of the source / drain regions is commonly connected to a bit line. 9. The ferroelectric memory device according to claim 8, wherein the gate insulating film has a laminated structure of insulating film / floating gate / ferroelectric film. 10. A third semiconductor device provided with a polycrystalline semiconductor fuse in each chip so that the third potential for writing information in the ferroelectric memory cell can be trimmed chip by chip.
The potential trimming means is provided, and the potential trimming means is provided.
Alternatively, the ferroelectric memory device according to item 9. 11. The two-terminal switch element having a metal / dielectric / metal structure is provided between the gate insulating film and the word line, as described in any one of claims 8 to 10. Ferroelectric memory device. 12. The method for driving a ferroelectric memory device according to claim 8, wherein all the bit lines and drive lines have the same potential, and the bit lines and all gate electrodes. An erase voltage is applied between the gate electrode and the gate electrode to bring the surface of the semiconductor layer facing the gate electrode into an accumulated state, so that all the ferroelectric memory cells are polarized so as to be non-conductive and data "0" is stored. A method for driving a ferroelectric memory device, characterized in that information is erased by corresponding to the above. 13. The method of driving a ferroelectric memory device according to claim 8, wherein the bit line and a drive line corresponding to the bit line have the same potential, and the selected bit line is By setting the selected word line to the third potential and the non-selected word lines and bit lines to the second potential as well as the ground potential, the ferroelectric memory cell is read when the selected ferroelectric memory cell is read out. A method of driving a ferroelectric memory device, wherein information is written by polarization so that the body memory cell becomes conductive and corresponding to data "1". 14. The method for driving a ferroelectric memory device according to claim 8, wherein the drive line is set to the ground potential, the selected word line is set to the first potential, and the selected word line is selected. Set the bit line to the first potential side,
A method for driving a ferroelectric memory device, comprising reading data from a dielectric memory cell by detecting conduction / non-conduction of a selected ferroelectric memory cell. 15. The method of driving a ferroelectric memory device according to claim 11, wherein a positive write voltage or a negative write voltage is applied to a selected cell, and “1” or “1” is assigned to the positive or negative voltage, respectively. A method for driving a ferroelectric memory device, characterized by operating as a random access memory by writing "0". 16. In a ferroelectric memory device in which one field effect transistor type ferroelectric memory cell having a ferroelectric film in a part of a gate insulating film is arranged in a matrix, the field effect transistor is a thin film transistor. The thin film transistor is a word line that becomes a gate electrode extending in a row direction on an insulating substrate, a gate insulating film provided on the word line, and a recrystallized polycrystal provided on the gate insulating film. A semiconductor layer and a source / drain region provided in the polycrystalline semiconductor layer,
One of the drain regions is commonly connected to the bit line,
A ferroelectric memory device, wherein the other one of the source / drain regions is commonly connected to a drive line extending in a bit line direction. 17. The overlap capacitance between the gate electrode and the other of the source / drain regions commonly connected to the drive line is calculated from the overlap capacitance between one of the source / drain regions commonly connected to the bit line and the gate electrode. 17. The ferroelectric memory device according to claim 16, wherein the size is also increased. 18. The ferroelectric memory device according to claim 16, wherein the gate insulating film has a laminated structure of a ferroelectric film / floating gate / insulating film. 19. A third semiconductor device provided with a polycrystalline semiconductor fuse in each chip so that the third potential for writing information in the ferroelectric memory cell can be trimmed chip by chip.
2. A potential trimming means is provided, wherein
19. The ferroelectric memory device according to any one of 6 to 18. 20. A two-terminal switch element having a metal / dielectric / metal structure is provided between the gate insulating film and the word line, according to any one of claims 16 to 19.
2. A ferroelectric memory device according to item. 21. The method of driving a ferroelectric memory device according to claim 16, wherein all the word lines are set to the ground potential, and all the bit lines and drive lines are erased. A method of driving a ferroelectric memory device, characterized in that all of the above ferroelectric memory cells are polarized so as to be non-conductive by setting a potential, and information is erased by corresponding to data "0". .. 22. The method of driving a ferroelectric memory device according to claim 16, wherein the bit line and a drive line corresponding to the bit line have the same potential, and the selected bit line is selected. Is set to the ground potential, the selected word line is set to the third potential, and the non-selected word lines and bit lines are set to the second potential, so that the ferroelectric memory cell is read when the selected ferroelectric memory cell is read. A method of driving a ferroelectric memory device, characterized in that information is written by polarization so that the dielectric memory cell is conductive and corresponding to data "1". 23. The method of driving a ferroelectric memory device according to claim 16, wherein all the drive lines are set to a first potential and selected word lines are set to a first potential. A ferroelectric memory device is characterized in that the selected bit line is set to the ground potential side and data of the dielectric memory cell is read by detecting conduction / non-conduction of the selected ferroelectric memory cell. Driving method. 24. The method of driving a ferroelectric memory device according to claim 16, wherein the drive line is set to the ground potential, the selected word line is set to the first potential, and the selected word line is selected. A method of driving a ferroelectric memory device, characterized in that the bit line is set to the first potential side and the data of the dielectric memory cell is read by detecting conduction / non-conduction of the selected ferroelectric memory cell. 25. The method of driving a ferroelectric memory device according to claim 20, wherein a positive write voltage or a negative write voltage is applied to a selected cell, and “1” or “1” is assigned to the positive or negative voltage, respectively. A method for driving a ferroelectric memory device, characterized by operating as a random access memory by writing "0".