JPH09148458A - Manufacture of semiconductor element with floating gate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method allowing the cell size to be reduced by reducing the size of contact holes. SOLUTION: An element isolation region, first insulation film and first conductive film are formed on a semiconductor substrate 20, this conductive film is patterned to form a floating gate primary pattern and ion-implanted to form a diffused region. A second insulation film is formed and etched back to form side wall spacers 25 and third insulation film is formed. A second conductive film and fourth insulation film are formed and patterned to form control gates 26 with large spacings at a contact-hole forming area and narrow spacings at other area, the primary pattern is etched to form floating gates 30' and ion-implanted to form a source and drain regions. A fifth insulation film is formed and anisotropically etched to form contact holes, and third conductive film is formed and patterned to form an interconnection film 34.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EPROM (Erasable Programmable Read Only Memory) having a floating gate.
(Rewritable read-only memory)), particularly in a photo-etching step when forming a contact hole connected to a peripheral circuit section,
Manufacture of a nonvolatile semiconductor memory device having a floating gate in which a contact hole region is defined using one mask, a contact hole is formed by self-aligning, and the size of a cell can be reduced. Regarding the method.

[0002]

2. Description of the Related Art Among semiconductor memory devices, a semiconductor element having a floating gate, particularly a non-volatile semiconductor memory device, includes a memory cell having a floating gate and a control gate,
And a peripheral circuit section. The gate of the memory cell is formed of polycrystalline silicon doped with phosphorus or the like as an impurity element.

The floating gate is separated from the semiconductor substrate by a gate oxide film, and the semiconductor substrate includes a source and a drain forming a cell transistor.
The floating gate and the control gate are insulated from each other by an insulating film such as SiO ₂ .

The operation principle of a semiconductor element using a floating gate, especially a nonvolatile semiconductor memory device is as follows.
That is, by applying a positive high voltage to the gate electrode and the drain, electrons having high energy (hot electrons) generated in the vicinity of the drain are caused to cross the potential barrier of the gate oxide film, and Inject electrons into the floating gate. As described above, the threshold value of the cell transistor is changed and programmed by the charge amount of the electrons injected into the floating gate electrode. On the other hand, when ultraviolet light having energy higher than the potential barrier of the gate oxide film is irradiated, the electrons accumulated in the floating gate are returned to the substrate and the programming is erased. To erase programming of a semiconductor device having some kind of floating gate, a high positive voltage is applied to the source and the drain and a negative voltage is applied to the control gate electrode.
Then, the electrons accumulated in the floating gate are returned to the substrate and the programming is erased.

In a semiconductor element using such a floating gate, particularly in a nonvolatile semiconductor memory device, a cell portion having a floating gate and a peripheral circuit portion related thereto are formed on the same chip, and these are subjected to a wafer process. The process proceeds so as to form at the same time. In addition, designing these layouts is an important step in the manufacturing process. A typical process example for forming these will be described below.

13 to 14 show examples of typical steps for simultaneously forming a semiconductor element having a conventional floating gate, particularly a memory cell of a nonvolatile semiconductor memory device and a MOS transistor constituting a peripheral circuit.

13A shows a memory cell forming portion and a peripheral circuit forming portion, respectively. The memory cell formation portion A includes a semiconductor element using a floating gate, particularly a cell element of a nonvolatile semiconductor memory device. On the other hand, the peripheral circuit forming portion B typically includes a MOS transistor.

In such a conventional method of manufacturing a semiconductor device having a floating gate, first, as shown in FIG. 13A, an element isolation region 2 for partitioning a memory cell forming portion A and a peripheral circuit forming portion B is formed. Are formed on the semiconductor substrate 1.

Next, after the insulating film 10 is formed on the semiconductor substrate 1, the first polycrystalline silicon film 3 for forming the floating gate of the cell element of the nonvolatile semiconductor memory device is formed on the entire surface.

Since the peripheral circuit forming portion does not require a two-layer structure for the gate electrode, as shown in FIG. 13B, the first polycrystalline silicon film 3 in the corresponding region is removed by photoetching. Further, since an insulating film is required on the floating gate of the memory cell, the insulating film 11 which also functions as a dielectric film is formed as shown in the figure.

Next, as shown in FIG. 13 (C), the second polycrystalline silicon, which becomes the control gate of the memory cell and the gate electrode of the MOS element in the peripheral circuit forming portion, is formed on the entire surface of the semiconductor substrate 1 which has undergone the above steps. The film 4 is formed. Of course, these are used as word lines. In order to form these elements, an oxide film 5 is formed on the second polycrystalline silicon film 4 as shown in FIG. 13 (C). Next, as shown in FIG. 13D, the oxide film 5 and the second polycrystalline silicon film 4 are patterned to form the gate electrode 13 and the control gate 14.

Next, as shown in FIG. 14E, the peripheral circuit forming portion is masked with a photoresist film 6 and the portion of the insulating film 11 which also functions as a dielectric film is exposed at the memory cell forming portion. Remove. Therefore, using the photoresist film 6 and the oxide film 5 on the control gate 14 as an etching barrier, the exposed portion of the first polycrystalline silicon film 3 is etched and removed. As a result, the floating gate 15 is formed as shown in FIG. After that, the photoresist film 6 is removed, and ion implantation is performed to form a source region and a drain region (both not shown).

Thus, the MO having the floating gate
A semiconductor element using an S transistor, particularly a nonvolatile semiconductor memory device is formed. Next, as shown in FIG. 14G, a BPSG (Boro-Phospho-Silicate-Glass) film 16 is formed, and a contact hole 8 is formed using a photoresist mask 7. Next, as shown in FIG. 14H, a metal wiring film 9 is formed in the contact hole to complete a semiconductor element using a MOS transistor having a floating gate, particularly a nonvolatile semiconductor memory device.

[0014]

Since as many cells as possible can be formed in the same chip area to obtain many advantages, it is necessary to use the cell area as efficiently as possible. However, in the above-mentioned conventional technique, one cell has one or more contacts, and when the memory cells are arranged in a matrix array, many contact regions must be included in the memory cell region. In order to use the cell area efficiently, it is necessary to improve the contact structure.

An object of the present invention is to solve the above problems of the prior art.

That is, the object of the present invention is to utilize the fact that the contacts in the cell region are arranged periodically and the fact that the surface topography of the cell is not flat, using only one mask. The contact area of the peripheral circuit part is formed by the photo-etching process, and the self-alignment method (se
By forming fine contacts in the memory cell element formation region in a lf aligning manner, the area of each cell can be reduced and the cell size can be reduced. To provide a method for manufacturing a conductive semiconductor memory device.

[0017]

In order to achieve the above object, a method of manufacturing a semiconductor device having a floating gate according to the present invention comprises: (1) forming an element isolation region on a semiconductor substrate,
A step of forming a first insulating film and forming a first conductive film on the first insulating film; and (2) patterning the first conductive film into a band shape to form a floating gate primary pattern and impurities. A step of implanting ions to form a diffusion region on the surface portion of the semiconductor substrate; and (3) forming a second insulating film on the entire surface of the semiconductor substrate that has undergone the above steps and etching back the floating gate Filling a side surface of the next pattern with a sidewall spacer made of the second insulating film, and then forming a third insulating film on the entire surface of the semiconductor substrate that has undergone the above steps, and (4)
A second conductive film is formed on the third insulating film, a fourth insulating film is formed on the second conductive film, and then the fourth insulating film and the second insulating film are formed.
The control gate is formed by patterning the conductive film, and at that time, the control gates are widened in the region where the contact is to be formed later, and the control gates are narrowed in the other regions. (5) The fourth step on the control gate
The floating gate primary pattern is etched by using the insulating film as a mask to form a floating gate, and impurity ions are implanted to form a source region and a drain region. (6) The semiconductor substrate after the above process Forming a thick fifth insulating film on the entire surface, and then anisotropically etching the fifth insulating film to form a contact hole at a portion where the control gate is widely spaced; (7) A step of forming a third conductive film on the entire surface of the semiconductor substrate that has undergone the above steps and filling the contact holes, and then patterning the third conductive film to form a wiring film. And

In this case, the thickness of the second insulating film in the step (3) is formed to be 1/2 or more of the interval between the floating gate primary patterns.

Further, in this case, the thickness of the fifth insulating film in the step (6) is thicker than half of the narrow width between the control gates and thinner than half of the wide width. .

Further, in this case, when the contact hole is formed in the step (6), the memory cell forming portion is exposed, and the peripheral circuit forming portion is formed with a photoresist mask exposing only the contact hole portion. The upper surface of the fifth insulating film is removed, and the side surface of the fifth insulating film is etched so as to remain.

In this case, in the step (2),
After forming a photoresist mask covering the peripheral circuit formation portion, the impurity ions are implanted into the memory cell formation portion.

In this case, the first to fifth insulating films are S
It is characterized in that it is formed of iO ₂ or Si ₃ N ₄ , and the first to third conductive films are formed of polycrystalline silicon.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

1 to 12 show steps of simultaneously forming a semiconductor element having a floating gate according to the present invention, particularly a cell element of a nonvolatile semiconductor memory device and a MOS transistor forming a peripheral circuit.

FIG. 2 is a partial plan view of a semiconductor element having a floating gate according to the present invention, in particular, a cell element of a nonvolatile semiconductor memory device and a MOS transistor constituting a peripheral circuit. A is a memory cell forming portion, and B is a memory cell forming portion. Indicate peripheral circuit forming portions, respectively. A case where a semiconductor element using a floating gate, particularly a cell element of a nonvolatile semiconductor memory device, is formed in the memory cell formation portion A, and a MOS transistor is typically formed in the peripheral circuit formation portion B is shown.

FIGS. 1A to 1D respectively show a of FIG.
It is sectional drawing in the -a line, the bb line, the cc line, and the dd line.

The manufacturing process of the present invention is as follows.

First, in the first step, as shown in FIGS. 1 and 2, a field oxide film 21 is formed as an element isolation region in order to separate the semiconductor substrate 20 into an active region and a field region. First insulating film 2 on 20
2 is formed, and a polycrystalline silicon film is formed thereon as a first conductive film.

Next, a photo-etching process is performed to etch the polycrystalline silicon film to form a strip-shaped floating gate primary pattern 30. At this time, since the polycrystalline silicon film is not required in the peripheral circuit forming portion B, all the polycrystalline silicon film in the peripheral circuit forming portion B is removed.

Next, as shown in FIG. 3 (a sectional view taken along the line aa in FIG. 2), after the photoresist mask 24 is formed in the peripheral circuit forming portion B, the semiconductor substrate 20 in the memory cell forming portion A is formed. N-type impurity ions are implanted over the entire surface of.
In this way, ions are implanted into the portion of the semiconductor substrate 20 that is covered only by the first insulating film 22 and is not covered by the photoresist mask 24 or the floating gate primary pattern 30. After that, the photoresist mask 24 is removed. Although not shown, the doped regions are connected to the source and drain regions which will be formed later. The impurity region is formed by the ion implantation method based on the conventional technique, but this step may be performed later.

FIG. 4 shows the third insulating film 41 and the sidewall spacers 2.
5 shows the manufacturing process of FIGS. 4A to 4D are manufacturing process cross-sectional views taken along lines aa, bb, cc, and dd of FIG. 2, respectively.

As shown in FIG. 4, Si is formed on the entire surface of the semiconductor substrate 20 which has undergone the above steps by a chemical vapor deposition method.
A second insulating film made of O ₂ or Si ₃ N ₄ is deposited.
Then, the second insulating film is etched back by an anisotropic etching method to form a sidewall spacer 25 made of the second insulating film filling the space between the floating gate primary patterns 30. The thickness of the second insulating film forming the sidewall spacers 25 is set to ½ or more of the distance between the floating gate primary patterns 30.

Next, a silicon oxide film is formed as the third insulating film 41 on the floating gate primary pattern 30 and the remaining surface. The third insulating film 41 also functions as a dielectric film.

FIG. 5 is a sectional view of the manufacturing process taken along the line aa in FIG.

FIG. 7 is a partial plan view of the memory cell formation portion A and the peripheral circuit formation portion B corresponding to FIG.

FIGS. 6A to 6D respectively show a of FIG.
It is sectional drawing in the -a line, the bb line, the cc line, and the dd line.

As shown in FIGS. 5 and 6, a polycrystalline silicon film is formed as a second conductive film on the entire surface of the third insulating film 41 on the semiconductor substrate 20 which has undergone the above steps, and a fourth insulating film is formed on the polycrystalline silicon film. The film 28 is formed. Next, the fourth insulating film 28 and the second conductive film are photo-etched to form the control gate 26 for the memory cell and the gate electrode 27 for the MOS element in the peripheral circuit forming portion B. These correspond to word lines. That is, a second conductive film made of polycrystalline silicon is formed on the third insulating film 41, and a fourth conductive film is formed thereon.
A silicon oxide film is formed as the insulating film 28, and the second conductive film and the fourth insulating film 28 are patterned to form the gate electrode 27.
And the control gate 26 are formed.

In this case, the mask for patterning the gate electrode 27 and the control gate 26 is provided with a wide space in a portion where a contact hole will be formed later by self-aligning, and the contact hole is not formed. Make sure that the parts have a narrow space.

8A to 9E are views for explaining the meaning of the above steps in more detail. Figure 9 (E)
FIG. 8 is a plan view of a portion indicated by “P” in FIG. 7,
8A and 8C are cross-sectional views taken along the line aa of FIG. 9E, and FIGS. 8B and 9D are each shown in FIG.
It is sectional drawing in the bb line of (E).

When the fifth insulating film 31 is vapor-deposited in the state where the control gate 26 is formed as shown in FIG. 9E, the sectional views become as shown in FIGS. 8A and 8B. In this state, when anisotropic etching is applied to the fifth insulating film 31 and etching back is performed, cross-sectional views are shown in FIGS. 8C and 9D.
The form shown in is obtained.

As can be seen from FIG. 8C, contact holes are not formed if the distance between the control gates is narrowed, but if the distance between the control gates is widened as shown in FIG. 9D, sidewall insulation is achieved. Spacers 31 'are formed and contact holes are formed between them.

Returning to FIG. 6 again, the peripheral circuit forming portion B is masked with the photoresist film 29, and the memory cell forming portion A is removed.
The exposed portion of the third insulating film 41, which is also the dielectric film, is removed by etching. Then, the photoresist film 2
9 and the fourth insulating film 28 on the control gate 26 are used as etching barriers to expose the exposed floating gate 1.
The next pattern 30 is etched away to form the floating gate 30 '. Then, impurity ions are implanted, and heat treatment is performed in a subsequent process to form a source region and a drain region (neither is shown). At this time, an impurity region connecting the field oxide films 21 and the floating gates 30 'is formed. Then, the photoresist film 29 is removed.

10 to 12 are sectional views taken along the line yy of FIG.

As the next step, as shown in FIG.
A BPSG film is applied as a fifth insulating film 31 to the entire surface of the semiconductor substrate 20 that has undergone the above steps, and a photoresist pattern 39 for forming a contact hole is formed. The photoresist pattern 39 covers the remaining area of the peripheral circuit formation portion B excluding the contact hole formation area and the memory cell formation portion A. In other words, the photoresist pattern 39 has openings in the contact hole formation region of the peripheral circuit formation portion B and the memory cell formation portion A. That is, in FIG. 10, the exposed portion of the peripheral circuit formation portion B corresponds to the contact hole formation region of the peripheral circuit formation portion B.

Next, as shown in FIG. 11, dry etching is applied to the exposed portion of the fifth insulating film 31 made of the BPSG film. Thus, in the memory cell formation portion A, the sidewall insulating spacer 31 'is formed on the sidewall of the gate, and the semiconductor region exposed between the sidewall insulating spacers 31' becomes a fine contact hole 32. In the peripheral circuit forming portion B, the contact hole 33 is formed by the mask pattern.

That is, as shown in FIG. 9D, in the memory cell forming section A, when the photoetching for forming the contact hole 33 in the peripheral circuit forming section B is performed, the sidewall is formed without using the mask pattern. By adjusting the width of the gate electrode with the insulating spacer 31 ', the fine contact hole 32 can be formed in a self-aligned manner. Therefore, the size of the cell area can be reduced.

After the contact holes 32 and 33 necessary for the MOS element and the semiconductor element using the floating gate, especially the memory cell of the nonvolatile semiconductor memory device are formed in this way, the photoresist pattern 39 is removed. Next, as shown in FIG. 12, a conductive material is formed as a third conductive film to fill the inside of the contact hole, and patterning is performed to form a wiring film 34 in the contact hole. A nonvolatile semiconductor memory device is completed.

[0048]

According to the present invention, the contact hole of the peripheral circuit forming portion is formed using only one mask in the photolithography process at the time of forming the contact hole,
On the other hand, in the memory cell element formation region, since a contact hole of a fine size can be formed in a self-aligning manner, the area occupied by one cell can be reduced, and a semiconductor element having a floating gate with a reduced cell size can be formed. In particular, it becomes possible to form a nonvolatile semiconductor memory device.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view in a manufacturing process of the present invention.

FIG. 2 is a partial plan view in the manufacturing process of the present invention.

3 is a sectional view taken along line aa of FIG.

FIG. 4 is a partial cross-sectional view in the manufacturing process of the present invention.

FIG. 5 is a partial cross-sectional view in the manufacturing process of the present invention.

FIG. 6 is a partial cross-sectional view in the manufacturing process of the present invention.

FIG. 7 is a partial plan view in the manufacturing process of the present invention.

FIG. 8 is a cross-sectional view showing details of a “P” portion in FIG.

9 (D) is a cross-sectional view showing details of the "P" portion of FIG. 8, and (E) is a plan view showing details of the "P" portion of FIG.

FIG. 10 is a partial cross-sectional view in the manufacturing process of the present invention.

FIG. 11 is a partial cross-sectional view in the manufacturing process of the present invention.

FIG. 12 is a partial cross-sectional view in the manufacturing process of the present invention.

FIG. 13 is a partial cross-sectional view of a manufacturing process of a conventional semiconductor device having a floating gate.

FIG. 14 is a partial cross-sectional view of a manufacturing process of a conventional semiconductor device having a floating gate.

[Explanation of symbols]

 20 ... Semiconductor substrate, 21 ... Field oxide film, 22 ... First insulating film, 24 ... Photoresist mask, 25 ... Side wall spacer, 26 ... Control gate, 27 ... Gate electrode, 28 ... Fourth insulating film, 29 ... Photoresist film, 30 ... Floating gate primary pattern, 30 '... Floating gate, 31 ... Fifth insulating film, 31' ... Side wall insulating spacer, 32, 33 ... Contact hole, 34 ... Wiring film, 39 ... Photoresist pattern, 41 ... Third insulating film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 27/115

Claims (6)

[Claims] 1. A step of: (1) forming an element isolation region on a semiconductor substrate, then forming a first insulating film, and forming a first conductive film on the first insulating film; (1) forming a floating gate primary pattern by patterning a conductive film into a strip shape and implanting impurity ions to form a diffusion region on the surface of the semiconductor substrate; and (3) the semiconductor substrate after the above steps. A second insulating film is formed on the entire surface and is etched back to form the floating gate 1
Filling the side surface of the next pattern with a sidewall spacer made of the second insulating film, and then forming a third insulating film on the entire surface of the semiconductor substrate that has undergone the above steps, and (4) forming a third insulating film on the third insulating film. 2 Conductive film is formed, and the second
After forming a fourth insulating film on the conductive film, the fourth insulating film and the second conductive film are patterned to form a control gate, and at the time of forming a contact, the above control A step of widening the gate interval and a narrow interval of the control gate in the other regions; and (5) etching the floating gate primary pattern using the fourth insulating film on the control gate as a mask. Forming a floating gate, implanting impurity ions to form a source region and a drain region, and (6) forming a thick fifth insulating film on the entire surface of the semiconductor substrate after the above process, A step of anisotropically etching the fifth insulating film to form a contact hole in a region where the control gate is widely spaced; (7) the semiconductor substrate after the above step A step of forming a third conductive film on the entire surface and filling the contact hole, and then patterning the third conductive film to form a wiring film. Manufacturing method. 2. The method of manufacturing a semiconductor device having a floating gate according to claim 1, wherein the thickness of the second insulating film in the step (3) is 1 / th of an interval between the floating gate primary patterns. A method of manufacturing a semiconductor device having a floating gate, which is characterized in that the number of the gate electrodes is two or more. 3. The method of manufacturing a semiconductor device having a floating gate according to claim 1, wherein the thickness of the fifth insulating film in the step (6) is thicker than half the narrow width between the control gates. A method of manufacturing a semiconductor device having a floating gate, characterized in that the semiconductor device is formed thinner than a half of a wide width. 4. The method of manufacturing a semiconductor device having a floating gate according to claim 1, wherein the memory cell formation portion is exposed and the peripheral circuit formation portion is contacted when the contact hole is formed in the step (6). After forming the photoresist mask exposing only the hole portion, the upper surface portion of the fifth insulating film is removed, and the side surface portion of the fifth insulating film is etched so that the floating gate has a floating gate. Manufacturing method of semiconductor device. 5. A method of manufacturing a semiconductor device having a floating gate according to claim 1, wherein in the step (2),
A method of manufacturing a semiconductor device having a floating gate, comprising forming a photoresist mask covering a peripheral circuit formation portion and then implanting the impurity ions into the memory cell formation portion. 6. The method of manufacturing a semiconductor device having a floating gate according to claim 1, wherein the first to fifth insulating films are S.
A method for manufacturing a semiconductor device having a floating gate, which is formed of iO ₂ or Si ₃ N ₄ , and the first to third conductive films are formed of polycrystalline silicon.