JPH09135240A - Digital phase synchronization circuit for multi-rate signal receiving circuit - Google Patents

Abstract

(57) Abstract: A digital PLL for generating a symbol clock of a multi-rate signal receiving circuit in which a data transmission rate changes during transmission is generated between a symbol clock generated at the time of rate switching and a reception baseband signal. Try to eliminate the gap. The output of the A digital VCO5 controlled by the control voltage of the loop filter 3 2,4, and N-bit counter 6 to output an N number of divided frequency ... 2 ^N division to correspond to the switched rate transmission Then, an adder 9 is provided between the selector 7 and the selector 7 which switches the frequency-divided output to be a symbol clock. At the time of rate switching, the phase offset value P set in advance corresponding to a plurality of transmission rates is input from the switch 10 to the adder 9, and the phase-corrected frequency division output is given to the selector 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention receives a multi-rate signal whose data transmission rate (rate) changes during transmission, and switches the initial phase of the clock every time the rate is switched to stably reproduce the data. The present invention relates to a multi-rate signal receiving circuit, and particularly to a digital phase locked loop (DPLL) used in the receiving circuit.

[0002]

2. Description of the Related Art FIG. 3 shows a timing chart for explaining the structure of a multi-rate signal. The multi-rate signal is composed of frames whose time T is one frame length.
A frame is composed of a sync signal and an information signal at time T1, and the sync signal is composed of a sync signal (1), frame information and a sync signal (2). In this example, the synchronization signal (1)
And frame information is transmitted at rate A, and the synchronization signal (2)
And the information signal is transmitted at rate B. Sync signal (1)
Shows a pattern for clock synchronization, speed information of a rate B to be changed next, and a frame synchronizing signal. The frame information describes the structure of the information signal. The synchronization signal (1) and the section T2 of the frame information are transmitted at the rate A. The synchronization signal (2) is a synchronization signal for detecting the beginning of the information signal, and the same synchronization code is used regardless of the transmission rate, and the entire synchronization signal has a constant time regardless of the transmission rate. A pattern for clock synchronization is inserted in an empty space to reach T1. The sync signal (2) and the information signal are transmitted at rate B.

The relationship between the rate A and the rate B has a constant proportional relationship such that the ratio is 1: 2, 1: 4.
There are various kinds of information per symbol, such as binary code and quaternary code, but the description is omitted because it basically does not affect the symbol clock timing itself.

FIG. 4 is a block diagram of a multirate signal receiving circuit for receiving a multirate signal to which the present invention is applied. The multi-rate signal reception circuit shown in FIG. 4 includes a reception demodulation circuit 11 that demodulates a multi-rate reception signal and outputs it as a baseband signal, a detection pulse that detects a synchronization signal from the baseband signal, and a transmission that detects from the synchronization signal. A frame synchronization signal detection circuit 12 that outputs a rate, a symbol counter 13 that receives a detection pulse, counts a fixed number of symbols at the timing of a symbol clock, and outputs a rate switching timing, and a digital phase synchronization (DLLL) by inputting a baseband signal. The DPLL 14 which operates to input the transmission rate and the rate switching timing, changes the transmission rate to the symbol clock of the transmission rate input at the rate switching timing, and maintains and outputs the symbol clock of the transmission rate until the next rate switching timing.
And a reproduction circuit 1 for reproducing data from a baseband signal
5 is comprised.

The operation for each frame is as follows. First, the frame synchronization signal detection circuit 12 includes the reception demodulation circuit 1
From the baseband signal demodulated in 1, the sync signal (1) including the speed information is detected, the detection pulse of the sync signal and the transmission rate information of the rate B which changes next are output. The symbol counter 13 inputs a detection pulse, counts a fixed number of symbols in a period corresponding to frame information, and outputs a rate switching timing for switching to the rate B. DPLL
Reference numeral 14 generates a symbol clock synchronized with the baseband signal based on the input baseband signal, and switches the speed to the rate B according to the transmission rate information from the frame synchronization signal detection circuit 12 at the rate switching timing from the symbol counter 13. Then, the speed is maintained until the input of the next rate switching timing.

Next, the frame synchronization signal detection circuit 12
From the baseband signal demodulated by the reception demodulation circuit 11,
The sync signal (2) is detected, and the detection pulse of the sync signal and the transmission rate information of the rate A that changes next are output. The symbol counter 13 inputs the detection pulse, counts the time corresponding to the information signal, and outputs the rate switching timing for switching to the rate A. The DPLL 14 generates a symbol clock synchronized with the baseband signal based on the input baseband signal, and at the rate switching timing from the symbol counter 13, the frame synchronization signal detection circuit 1
The speed is switched to the rate A according to the transmission rate information from 2, and the speed is maintained until the input of the next rate switching timing. The reproduction circuit 15 reproduces and outputs data from the baseband signal based on the symbol clock from the DPLL 14.

FIG. 5 shows a timing chart at the time of rate switching in the prior art. The current symbol clock operates at the rate A and is synchronized with the baseband signal, and the frame synchronization signal detection circuit 12 It detects the frame sync signal and outputs rate B as the transmission rate,
The symbol counter 13 is for switching from the rate A to the rate B while the constant symbol number is being counted.

FIG. 6 shows an example of the configuration of a conventional DPLL 14 used in a multi-rate receiving / receiving circuit. The DPLL 14 shown in FIG. 6 includes a symbol change point detector 1 that inputs a baseband signal of a multi-rate signal, detects a symbol change point, and outputs a detection pulse, and a detection pulse from the symbol change point detector 1. A symbol clock from a selector 7, which will be described later, is input, the phase of the symbol clock at the change point of the symbol is detected, and based on the detection result, a binary decision is made as to whether the symbol clock is leading or lagging, and the result is output. Value quantization phase comparator 2, loop filter 3 that receives the determination result from binary quantization phase comparator 2 and smoothes it, fixed frequency oscillator 4, and receives the output of loop filter 3 as a control voltage A digital voltage controlled oscillator (VCO) 5 that adds / removes pulses based on The reference clock from 2,4, ..., the N-bit counter 6 to output an N number of divided frequency by 2 ^N division, in response to receiving the transmission rate of N subharmonic from N-bit counter 6 It is composed of a selector 7 which selects one of the N clocks and outputs it as a symbol clock, and a gate 8 which receives the transmission rate and the rate switching timing and controls the selector 7 in good timing at the change point of the symbol. With this configuration, it is possible to immediately switch the symbol clock in response to the transmission rate that changes by 2 times or 4 times.

[0009]

However, the low-pass filter (hereinafter referred to as LP) used in the reception demodulation circuit 11 is used.
Parts such as F) are often used in common regardless of the transmission speed because of the volume and the like. Therefore, the delay time of the LPF or the like is slightly different depending on the transmission speed. As shown in the figure, the delay time is slightly different between the baseband signal before rate switching and the baseband signal after rate switching, and the phase of the symbol clock and the baseband signal deviates with the conventional DPLL. This is not a problem in a noise-free environment unless the phase is completely deviated, but in a noisy environment, the phase is deviated, so that the data reproduced by the reproduction circuit 15 may have an error. Is higher than when not switched. In particular, the sync signal (2) immediately after the rate is switched
Is likely to be falsely detected.

As described above, in the conventional technique as described above, there is a possibility that a phase shift occurs between the symbol clock and the baseband signal immediately after the rate switching, and there is a possibility of making an error in a noisy environment. Get higher

An object of the present invention is to eliminate the problems that occur in the prior art and to prevent the phase difference between the symbol clock and the baseband signal immediately after the rate switching from occurring. It is to provide a synchronous circuit.

[0012]

A digital phase synchronization circuit for a multi-rate signal receiving circuit according to the present invention inputs a base band signal obtained by demodulating a multi-rate signal whose data transmission rate changes during transmission and inputs a change point of a symbol. A symbol change point detector that detects and outputs a detection pulse, and inputs the detection pulse and the symbol clock for reproduction, detects the phase of the symbol clock at the change point of the symbol,
Based on the detection result, a binary quantized phase comparator for binary-determining and outputting whether the symbol clock is advanced or delayed, and a loop for smoothing the determination result from the binary quantized phase comparator A filter, a fixed oscillator that generates a fixed frequency signal, and a pulse added based on the fixed frequency signal that receives the output of the loop filter as a control voltage.
A digital voltage controlled oscillator that removes and then outputs as a reference clock;
An N-bit counter that divides by 2 ^N and outputs N divided frequencies, a gate that outputs a switching control signal when the transmission rate and rate switching timing to be switched next are input, and a switching control signal from the gate In a digital phase synchronization circuit for a multi-rate signal receiving circuit, which is provided with a selector for selecting one of the N divided frequencies from the N-bit counter and outputting it as a symbol clock corresponding to the transmission rate switched to Connected between the N-bit counter and the selector, and a switch for switching and outputting a plurality of phase offset values set in advance corresponding to a plurality of transmission rates in accordance with a switching control signal of the gate. N output from the bit counter
It is characterized by comprising an adder that adds each of the divided frequencies and the phase offset value output from the switch and outputs the added result to the selector.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

(Structure) In order to solve the above problems, the DPLL in the multi-rate signal receiving circuit has the following structure. The structure of the present invention is shown in FIG. In FIG. 1, a portion from the symbol change point detector 1 to the gate 8 is a DPLL according to a conventional technique.
Since it is the same part as the part from the symbol change point detector 1 to the gate 8 of the circuit of FIG.

The adder 9 regards the received N divided frequencies as binary values (that is, with respect to the output value of the N-bit counter 6 itself), and sets the phase offset set value P from the switch 10 corresponding to the transmission rate. (0 ≦ P ≦ 2 ^N −1) is added, and the addition result is N
Output in the state of individual divided frequencies. The switch 10 uses a plurality of phase offset values P set in advance corresponding to the transmission rate.
At the same time that the selector 7 is switched, the selected signal is output to the adder 9.

(Operation) With the configuration as shown in FIG. 1, the phase offset (or the initial phase) of the symbol clock to be output can be set and switched at the same time when the transmission rate is switched. That is, the expected phase shift between the symbol clock and the received baseband signal before and after the transmission rate switching can be corrected to some extent by the phase offset value.

Next, the operation of the present invention will be described using a specific example. In FIG. 1, N = 3, the phase offset setting value P _A = 0 corresponding to the transmission rate A, and the phase offset setting value P _B = 1 corresponding to the transmission rate B are set. FIG. 2 shows a timing chart at the time of rate switching in the present invention at that time. In the figure, the output of the adder 9 is the data flow when the output of the adder 9 is regarded as a binary value. When the transmission rate is not switched, the output of the adder 9 is
It is equal to the output of a 3-bit counter that counts up one by one with 0, 1, 2, ..., 7 = 2 ³ −1 as one cycle.

Therefore, in the example of FIG. 2, assuming that the MSB (most significant digit) of the output of the adder 9 is the first bit, an inverted version of the first bit is output as the symbol clock at the rate A, and the rate B is output. At this time, the inverted second bit is output as the symbol clock. Where the counter output before and after switching from the rate A to the rate B should be 6 → 7 → 0 → 1 → 2 in the prior art, the present invention sets the phase offset value P _B = 1 to 6 → 7
→ 1 → 2 → 3 As a result, the phase of the symbol clock is shifted by π / 2 as seen in FIG. 2, and the phase shift between the symbol clock and the received baseband signal can be corrected to some extent.

In the example of FIG. 2, the possible values of the set value P of the phase offset are 0, 1 (π / 2), 2 (π), 3 (3π
/ 2), and the accuracy is low and the correction is not sufficient, the accuracy of the correction value can be increased by increasing N and setting P of an appropriate value corresponding thereto.

[0019]

As described above, according to the present invention, even if the components such as the LPF used in the multi-rate receiving / demodulating circuit 11 are slightly different in delay time depending on the transmission speed,
Since it is possible to correct the phase shift between the symbol clock and the baseband signal immediately after the rate switching, it is possible to use a multi-rate compatible that performs stable synchronization holding operation for the multi-rate signal whose data transmission rate is switched midway. DPL
L can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of the present invention.

FIG. 2 is a timing chart when switching rates according to the present invention.

FIG. 3 is a diagram illustrating a configuration example of a multi-rate signal.

FIG. 4 is a diagram illustrating a configuration example of a multi-rate receiving circuit.

FIG. 5 is a timing chart when switching rates according to the conventional technique.

FIG. 6 is a diagram showing a configuration example of a conventional DPLL.

[Explanation of symbols]

 1 Symbol Change Point Detector 2 Binary Quantization Phase Comparator 3 Loop Filter 4 Oscillator 5 Digital VCO 6 N-bit Counter 7 Selector 8 Gate 9 Adder 10 Switcher 11 Reception Demodulation Circuit 12 Frame Synchronization Signal Detection Circuit 13 Symbol Counter 14 DPLL 15 playback circuit

Claims (1)

[Claims] 1. A symbol change point detector which receives a base band signal obtained by receiving and demodulating a multi-rate signal whose data transmission rate changes during transmission, detects a symbol change point and outputs a detection pulse, and the detection pulse. A binary quantum that inputs a symbol clock for reproduction, detects the phase of the symbol clock at the change point of the symbol, and makes a binary decision as to whether the symbol clock is advancing or lagging based on the detection result and outputs. A phased phase comparator, a loop filter for smoothing the determination result from the binary quantized phase comparator,
A fixed oscillator that generates a fixed frequency signal, a digital voltage control oscillator that receives the output of the loop filter as a control voltage, adds and removes pulses based on the fixed frequency signal, and then outputs the reference clock, and the reference An N-bit counter that divides the clock by 2, 4,-, 2 ^N to output N divided frequencies, a gate that inputs a transmission rate and a rate switching timing to be switched next, and outputs a switching control signal, A multirate signal provided with a selector for selecting one of the N divided frequencies from the N-bit counter and outputting it as a symbol clock corresponding to a transmission rate to be changed next by a switching control signal from the gate. In the digital phase-locked loop circuit for the receiver circuit, there are multiple preset values that are set for the multiple transmission rates. A switcher for switching and outputting an offset value according to a switching control signal of the gate; and each of the N sub-frequency signals output from the N-bit counter and the switcher connected between the N-bit counter and the selector. A digital phase synchronization circuit for a multi-rate signal receiving circuit, comprising: an adder for adding the phase offset value output from the output to the selector.