JPH09128960A - Ferroelectric memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of the data destruction caused by the cross talk generated by a writing.reading which applies a voltage to a non-selected memory cell. SOLUTION: The device is a ferroelectric memory device and is made by orthogonally sandwitching a ferroelectric film 3 by first and second stripe electrodes 18 and 19. First, arbitrary electrodes in the electrodes 18 and 19 are specified to select a desired storage cell. Then, a voltage V is applied to the specified first stripe electrode 18 and a voltage V/n (where n is a real number) is applied to a non-specified electrode. Moreover, a voltage 0(v) is applied to the specified second stripe electrode 19 and a voltage (n-1)V/n is applied to a non-specified electrode. Thus, a data reading or a data writing against a desired cell is selectively conducted and the ferroelectric memory device and its driving method are realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simple matrix type ferroelectric memory device using a ferroelectric thin film,
In particular, it relates to a ferroelectric memory device that reduces crosstalk during writing and reading of information.

[0002]

2. Description of the Related Art Generally, with the development of computers and image devices, high density and high performance memory devices are required.
As a conventional memory device, an external memory device such as a magnetic tape, a floppy disk, a magneto-optical disk, or a semiconductor memory device, that is, a DRAM or an SRA is used.
M, EPROM, EEPROM, flash memory, etc. have been used.

When the multimedia and the computer are integrated, the memory device is firstly nonvolatile, secondly driven at high speed and low voltage, and thirdly a driveless solid-state memory. Higher performance and more compact memory is needed. However, there are cases in which the technology of the conventional recording device cannot cope.

As a memory device which meets this requirement, for example,
USP 4,873,664 (S. Sheffield Eaton Jr., C
Ferroelectric memories such as those disclosed in Olorado Springs, CO).

The structure of this ferroelectric memory is shown in FIG. The ferroelectric thin film capacitor 302 in the memory cell 301 is a switching element, and the DRAM type storage capacitor driven by the FET 303 is changed to the ferroelectric capacitor. The driving to the memory cell is connected to the word line 304, the plate line 305, and the bit line 308, and the reading is performed by the sense amplifier 307.

In this structure, the sense amplifier 307 is made of Si.
Since it is formed on the device, the degree of integration and cost are about the same as those of semiconductor memory DRAM and FLASH memory, which is inconvenient when a card of several 100 Mbytes is made, for example.

In contrast, USP 5,060,191
11 is a method of forming a simple matrix structure with a ferroelectric material 313 and detecting signals with the read drive circuits 314 and 315, as shown in FIG.

A major problem of the memory configured with such a simple matrix is that the cells are arranged adjacent to each other and the selected cell and the non-selected cell interfere with each other. For example, when a voltage Va is applied when a certain cell is selected and writing / reading is performed, the voltage is also applied to an unselected cell that is not selected. In particular, as the number of cells increases, Va / 2 is applied to the non-selected cells connected to the input / output side electrode lines of the selected cells.

Therefore, in the above USP 5,060,191, for example, with respect to the applied voltage Va to the selected cell,
The write operation is performed by devising that Va / 3 is applied to the non-selected cells. Further, in reading, a low impedance voltage is read to cut noise from non-selected cells.

Further, in Japanese Unexamined Patent Publication No. 7-9992, a simple matrix system as shown in FIG. 11 is used, and the storage state of the cell is completely polarized state X or Z as shown in FIGS. 12 (a) and (b). Is set to "0" in the memory state, a voltage 0.3 to 2 times the coercive voltage of the ferroelectric thin film is applied, and the partially polarized state Y in which the domains are mixed is set to "1" in the memory state and "0". Reading "1" is a ferroelectric memory device that detects the difference in capacitance value by an appropriate method. To a memory cell in which "0" information has already been written, a write voltage Vw is applied to a selected cell and Vw / 3 is applied to a non-selected cell, and "1" is applied only to a desired memory cell. Information is selectively written and information is read.

[0011]

However, as a drawback of the above-mentioned prior art, first, USP 4,87 shown in FIG.
In the case of No. 3,664, combination with a semiconductor is relatively easy to realize, but by using Si devices, that is, switching elements and FETs, the degree of integration and cost are the same as those of DRAM.

USP-50601 shown in FIG.
In the writing method disclosed in No. 91, when the polarization-voltage (PV) hysteresis characteristic of the ferroelectric capacitor is asymmetric, the positive coercive voltage and the negative coercive voltage values are different, and the unselected cell Even if the applied voltage is ⅓Va, the applied voltage to the non-selected cells becomes higher than the coercive voltage, and there is a risk of destruction. In the writing method disclosed in Japanese Patent Laid-Open No. 7-9992, when the capacity-partial polarization forming voltage (Cp-Vp) characteristic shown in FIG. 12B is asymmetrical depending on the voltage application direction to the cell, Even if the applied voltage to the non-selected cell is 1/3 Vw, it may be destroyed depending on the voltage application direction. Here, the capacity-partial polarization forming voltage characteristic means the relationship between the capacity and the forming voltage measured after the partial polarization state is formed by applying a reverse voltage to the ferroelectric capacitor in the saturated polarization state. doing. There is a correlation between the polarization-voltage (PV) hysteresis characteristics of ferroelectric capacitors and the capacitance-partial polarization formation voltage (Cp-Vp) characteristics.
When the PV characteristic is asymmetrical, the Cp-Vp characteristic is also asymmetrical depending on the voltage application direction. Therefore, an object of the present invention is to provide a ferroelectric memory device suitable for high integration and capable of writing / reading information while reducing crosstalk.

[0013]

In order to achieve the above object, the present invention provides a first stripe electrode composed of a plurality of stripe electrodes arranged in parallel and an arrangement surface of the first stripe electrode. , The array planes are separated in parallel,
Further, a second stripe electrode formed by arranging a plurality of stripe electrodes in parallel with the first stripe electrode in a direction orthogonal to the first stripe electrode arrangement direction, and the first and second stripe electrodes.
Ferroelectric memory in which memory cells are arranged in a matrix, which is composed of a ferroelectric thin film disposed between both electrodes at the intersection of the stripe electrodes, and information is selectively stored in the memory cells of this ferroelectric memory. In a ferroelectric memory device having a driving means for writing or reading, the ferroelectric thin film has an asymmetric polarization-electrode (PV) hysteresis characteristic, and the driving means is arranged in the first stripe electrode. And memory cell selecting means for selecting a desired memory cell by designating a striped electrode in the second striped electrode, and applying a voltage V to the designated striped electrode in the first striped electrode, The voltage V / n (n
Is a finite real number, which is in the range of 2 <n <3 or n> 3), and a voltage of 0 (V) is applied to a designated striped electrode in the second striped electrode, A dielectric memory device having an applied voltage control means for applying a voltage (n-1) V / n to a non-designated striped electrode in the second striped electrode.

According to the ferroelectric memory device of the present invention as described above, a memory cell in which a ferroelectric film is sandwiched by first and second stripe electrodes at right angles is arranged in a simple matrix, After selecting a desired memory cell by designating an arbitrary electrode in the first and second stripe electrodes, a voltage of magnitude V is applied to the designated electrode of the first stripe electrode, and V / is applied to the non-designated electrode. n (n is a real number) is applied,
By applying 0 (v) to the designated second stripe electrode and (n-1) V / n to the non-designated electrode, data writing or reading is selectively performed with respect to a desired cell. I do.

Therefore, the voltages applied to the non-selected cells are made non-uniform, and the amount of destruction applied to the non-selected cells Cy and Cx by applying a voltage from the lower electrode direction or the upper electrode direction and the non-selected cells Cxy. By making the amount of destruction that is destroyed by applying a voltage from the direction of the upper electrode or the direction of the lower electrode close to the same amount, the amount of destruction of non-selected cells in the matrix cell as a whole is reduced.

[0016]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 2 shows a cross-sectional structure of a memory cell of a ferroelectric memory device used to explain the ferroelectric memory device of the present invention, and the outline thereof will be described.

In this ferroelectric memory device, for example, Sr sandwiched by upper and lower electrodes 1 and 2 made of platinum or the like is used.
In the ferroelectric thin film 3 made of Bi ₂ Ta ₂ O _9, when a voltage is applied from both electrodes, the polarization amount changes non-linearly with respect to the applied voltage, and the hysteresis characteristic as shown in FIG. Actual measurement data). This hysteresis characteristic is usually measured using a continuous sine wave or a triangular wave of about 1 kHz, and Pr1 and Pr2 are the residual polarization amount, Vc1 ',
Vc2 'is called a coercive voltage. The positive side coercive voltage Vc
The absolute value of 1'does not match the absolute value of the coercive voltage Vc2 'on the negative side, and although there is a slight amount, the hysteresis characteristic is asymmetric.

A process for producing a ferroelectric cell 4 in which a ferroelectric thin film 3 is sandwiched between a pair of electrodes will be described below. Here, using a wet coating method called a so-called MOD method,
Ferroelectric thin film 3 made of SrBi ₂ Ta ₂ O ₉ described above
The case of forming the ferroelectric cell 4 using is described in detail.

First, as a precursor solution, Sr, Bi, T
Using the xylene solution of each ethylhexanoate of a, B
i is added in 10% excess with respect to the stoichiometric ratio. Then, the coating density is set to 0.15M, and the shake-off speed is 2000r.
A film was formed on a silicon substrate provided with a lower electrode 1 made of platinum having a thickness of 2000 angstroms.

Thereafter, the coating film is dried at 250 ° C. for 5 minutes, and further heated to 800 ° C. at a temperature rising rate of 125 ° C./second using an annealing device, and rapidly heated in an oxygen atmosphere for 30 seconds. Bake. The process from coating film formation to baking is repeated 3 times to form a multilayer film,
Anneal at 60 ° C. for 60 minutes. As a result, the film thickness 240
A 0 angstrom SrBi ₂ Ta ₂ O ₉ film thickness was obtained.

Subsequently, an upper electrode 2 made of upper platinum having a film thickness of 2000 angstrom is sputter-deposited on the ferroelectric thin film 3 and etched by using an ion mill. Finally, the entire substrate is 800 in an oxygen stream. Secondary annealing is performed at 30 ° C. for 30 minutes to form the ferroelectric memory cell 4. By this manufacturing process, a ferroelectric memory cell array in which ferroelectric memory cells are arranged in a simple matrix is configured.

Although the MOD method is used in the above-mentioned manufacturing process, the ferroelectric thin film may be formed similarly by a physical vapor deposition method (PVD) such as sputtering or a chemical vapor deposition method such as MOCVD. You can

Since the lower electrode 1, the ferroelectric thin film 3 and the upper electrode 2 are laminated while including the heat treatment process, various causes such as crystal defects at the interface of each layer to be joined by being exposed to plasma or heat. May occur, which may affect the electrical properties of the interface between the respective layers or in the vicinity thereof, and make the specific electrical characteristics asymmetric. However, the above-mentioned reason is one of the interpretations.

The asymmetry of the hysteresis characteristic is not specific to the SrBi ₂ Ta ₂ O ₉ ferroelectric thin film 3 and also occurs in a PZT film known as a ferroelectric material, for example.

FIG. 4 shows the relationship between the polarization breakdown amount ΔP and the magnitude Va of the applied pulse when a single pulse is applied. This figure shows the ferroelectric thin film 3 of SrBi ₂ Ta ₂ O _9.
Is the actual measurement data for. Here, the polarization breakdown amount ΔP represents how much the polarization amount of the ferroelectric thin film 3 has changed by applying a pulse of Va, that is, the breakdown.

Although defined by the coercive voltage Vc in FIG. 4, the coercive voltage shown in FIG. 3 evaluated while applying a continuous wave and FIG. 4 evaluated while applying a single pulse is Generally different, Vc ≠ Vc ′.

In the figure, the [I] region is a region where the polarization state set in the first direction does not change even if a pulse having a voltage of the region is applied. In the present embodiment, the first polarization state is the negative point with respect to the origin in FIG. Then, it is defined as "0" of digital data. Considering the read margin between the first polarization state and the partial polarization state which is one of the memory states, it is better to make the electrical characteristics of the first polarization state as large as possible. Is preferably in a completely polarized state, but conversely, it is not necessary to be in a completely polarized state as long as the read margin can secure an amount capable of distinguishing the data "1" and "0".

On the other hand, the partially polarized state is defined as "1".
This is defined for ease of explanation,
Even if "1" and "0" are defined in reverse, there is no problem in implementing.

In the figure, the region [III] is a region in which the first polarization state is inverted to the second polarization state by the applied pulse. Since the first polarization state is defined by point A in FIG. 3, the second polarization state is, for example, point A on the positive side of the origin. The [II] region shows a region in the partially polarized state. This partial polarization means the first
Is a mixed state of the second polarization and the second polarization, that is, a state in which domains of different polarizations are mixed.

As described above, the partial polarization sets the polarization state of the ferroelectric thin film 3 to the first polarization state by the first pulse having the negative direction, and then the first polarization having the positive direction. It can be formed by applying two pulses.

Next, FIG. 4 shows measured data for the SrBi ₂ Ta ₂ O ₉ ferroelectric thin film 3.
By applying a pulse having a magnitude of 2 to 2.5 times the coercive voltage Vc of the ferroelectric thin film 3, ΔP = 1 and the polarization is completely destroyed. That is, the polarization can be completely inverted.

Therefore, the coercive voltage Vc of the ferroelectric thin film 3 is 2
A negative first pulse having a magnitude of 2 to 2.5 times is applied to set the polarization state of the ferroelectric thin film 3 to the first polarization state in the negative direction, and then, the ferroelectric thin film. A partially polarized state can be formed by applying a positive second pulse having a magnitude of 0.3 to 2 times the coercive voltage Vc of 3.

It has been confirmed that this partially polarized state exists extremely stably. However, it has been confirmed that the capacitance value Cp with respect to the partial polarization forming voltage Vp shown in FIGS. The cause is not definite, but as described above, the ferroelectric thin film 3 is laminated with the lower electrode 1, the ferroelectric thin film 3, and the upper electrode 2 while including the heat treatment process. It is expected that the Cp-Vp characteristics will be asymmetric due to different electrical properties at or near the interface between the ferroelectric thin film 3 and the upper electrode 2.

For the same ferroelectric cell 4, FIG.
When a voltage is applied to the upper electrode 2 side and a signal is read from the lower electrode 1 side, conversely, FIG. 6 is a case where a voltage is applied to the lower electrode 1 side and a signal is read from the upper electrode 2 side. However, since they are asymmetric, the curves do not match as they are. However, the maximum value Cp of the capacitance Cp in the partially polarized state
max is almost the same. Further, of course, since the electrical characteristics of the same cell are used, the lower electrode 1 and the upper electrode 2 are
Needless to say, by reversing the electrodes, they match.

Therefore, the first polarization state, that is,
When "0" is set, the capacitance value Co in the first polarization state differs depending on whether the upper electrode 2 side is polarized or the lower electrode 1 side is polarized. For example, in FIGS. 5 and 6, X
When the point is "0" and the Y point is "1", the capacitance value difference ΔC between "1" and "0" is about 5%. On the other hand, if the Z point is "0" and the Y point is "1", the capacitance value difference between "1" and "0" doubles to about 10%. This is SrBi ₂
It is not unique to the Ta ₂ O ₉ ferroelectric thin film 3. For example, the same applies to PZT known as a ferroelectric material.

FIG. 1 shows, as an embodiment of the present invention, a configuration of a memory device having a ferroelectric cell 4 in a simple matrix configuration, and its operation will be described. In this ferroelectric memory device, the second stripe electrode 19 serving as a stripe-shaped upper electrode and the first stripe electrode 18 serving as a stripe-shaped lower electrode in the direction intersecting with each other are formed of the ferroelectric thin film 3.
A ferroelectric memory cell array 20 configured by sandwiching is used. In this cell array 20, cell selection circuits 23a and 23b connected to the respective electrodes to select cells, a voltage distribution circuit 33 connected to them, and the voltage distribution circuit 33.
An n control circuit 34 is provided for controlling the. Further, the cell selection circuit 23a is connected to the first, second and third pulse transmission circuits 25.26.27 via the changeover switch 28. The cell selection circuit 23b is connected to a data read circuit 32, a data write circuit 31, and a polarization setting circuit 30 via a changeover switch 29.

Next, the read operation of the ferroelectric memory device will be described. Here, either the upper electrode or the lower electrode may be the first striped electrode 18 or the second striped electrode 19, but as described above, the capacitance value difference ΔC between the capacitance in the saturated polarization state and the capacitance in the partial polarization is The larger the read margin, the better the S / N can be read, and when setting the first polarization state “0”, the saturation polarization state in which the capacitance value in the saturation state is smaller among the two saturation polarization states. Is the first polarization state.

The voltage application direction is determined so that the capacitance difference between the capacitance C ₀ and the capacitance C ₁ becomes large. In this embodiment, the capacitance C ₀ is the smallest when the voltage is applied from the first stripe electrode 18, and the capacitance difference between the capacitance C ₀ and the capacitance C ₁ is the largest. As a result, the read margin can be increased and S
/ N allows good reading.

Next, the write operation of the present ferroelectric memory device will be described. First, the first polarization state is set. In this case, one desired cell 21 is selected by the cell selection circuit 23, and the first pulse is applied only to the selected cell 21 from the first pulse sending circuit 25 that sends the first pulse. Next, the changeover switch 28 is changed over to output the second pulse to the second pulse sending circuit 26.
Thus, the second pulse is applied only to the selected memory cell.

However, in the case of the simple matrix structure shown in the figure, it is not easy to apply the voltage only to the selected memory cell 21. This is because if a voltage is applied to a selected cell due to mutual interference (crosstalk) with an adjacent cell, some voltage will be applied to the non-selected cell.

For example, referring to FIG. 7, the capacitance C is formed into an m × m matrix, Cij40 is selected,
When a voltage of Va is applied, the unselected cells 4
A voltage value as shown in FIG. 8 is applied to each cell including 0 '. By applying such a voltage, the polarization state of the non-selected cells 40 'that are not selected also changes.

In this embodiment, writing / reading is performed by the following method so as not to change the polarization state. First, the polarization setting for setting the first polarization state is switched to the first pulse transmission circuit 25 by the changeover switch 28, the cell selection circuit 23 selects all the first stripe electrodes 18 of the X lines, and
Similarly, all the second stripe electrodes 19 of the Y line are selected by the cell selection circuit 23, the changeover switch 29 is switched to the polarization setting circuit 30 side, and the first pulse is applied to all cells. By applying such a voltage, all cells are set to the first polarization state.

Next, in the writing for setting the partial polarization state, the change-over switch 28 is used for the second pulse sending circuit 2
6, and the write circuit 3 by the changeover switch 29.
Select 1.

Then, the voltage distribution circuit 33 and the cell selection circuit 23 apply voltage as follows. For example, X
Vw for the selected first stripe electrode 18 of the line, Vw / n for all the unselected first stripe electrodes 18 ', 0 (v) for the selected second stripe electrode 19 of the Y line, and all the unselected first stripe electrodes 18'. The two stripe electrodes 19 'are (n-1) Vw /
A potential of n is applied. The value of n is set by the n control circuit 34 provided in the voltage distribution circuit 33. A simple equivalent circuit at this time is shown in FIG.

Cs shown in FIG. 8 is a selected cell, Cy is a non-selected cell connected to the selected first stripe electrode of the X line and the unselected second stripe electrode of the Y line, and Cx is Y. The non-selected cell Cxy connected to the selected second stripe electrode of the line and the unselected first stripe electrode of the X line includes the unselected first stripe electrode of the X line and the unselected second stripe electrode of the Y line. It is a non-selected cell connected to the stripe electrode. Also, the * mark indicates the electrode on the lower electrode side of the cell capacitor sandwiched between the stripe electrodes shown in FIG.

As described above, data is written to the selected cell Cs by applying the voltage Vw from the direction of the lower electrode. An unselected cell Cy connected to the selected first stripe electrode of the X line, an unselected second stripe electrode of the Y line, and a selected second stripe electrode of the Y line, and an unselected first stripe electrode of the X line. The voltage Vw / n is applied from the direction of the lower electrode to the non-selected cell Cx connected to the one stripe electrode.

In addition, the unselected cell Cxy connected to the unselected first stripe electrode of the X line and the unselected second stripe electrode of the Y line has a voltage (n
-2) Vw / n is applied.

Here, when n = 3 so that the voltages applied to the respective non-selected cells become equal, the non-selected cells Cy and Cx have 1/3 Vw from the lower electrode direction as described above.
Is applied, the polarization state of the cell hardly changes, but 1/3 Vw is applied to the non-selected cell Cxy from the direction of the upper electrode. Therefore, compared with the non-selected cells Cy and Cx, A change occurs in the polarization state, that is, it is destroyed.

As described above, since non-destructiveness causes non-uniformity in non-selected cells, the matrix cell as a whole is
The destruction amount of the non-selected cell becomes large. Therefore, in the embodiment of the present invention, the value of n is set to n ≠ 3 and the voltages applied to the non-selected cells are made uneven. The value of n is the non-selected cell C
n is set so that the amount of breakdown applied to y and Cx by applying a voltage from the direction a and the amount of breakdown applied to the non-selected cell Cxy from the direction b, which is opposite to the direction a, are destroyed. The value of is set by the n control circuit 34. Here a direction,
With respect to the b direction, for example, the direction from the lower electrode to the upper electrode may be the a direction, and the opposite direction may be the b direction, or both directions may be interchanged.

In the embodiment, when setting the first polarization state, that is, "0", the saturation polarization state in which the capacitance value C ₀ in the saturation state is small among the two saturation polarization states is the first polarization state. The polarization state is 1. Further, the voltage is applied from the direction in which C ₀ is the smallest. In this embodiment, the capacitance C ₀ is minimized when a voltage is applied from the first stripe electrode 18. Therefore, by setting the value of n within the range of 2 <n <3, the unselected cells Cy, Cx, C are selected.
The voltage applied to xy can be set to V (Cy) = V (Cx)> V (Cxy), and the destruction amount of the non-selected cells can be made approximately the same.

Therefore, the destruction amount of the polarized states of Cy and Cx is slightly increased as compared with n = 1/3, but the destroyed amount of the polarized state of Cxy is decreased as compared with n = 1/3. As a whole cell, it is possible to realize the non-destructiveness by reducing the destruction amount of the non-selected cell as much as possible. That is, without changing the polarization state of the non-selected cell, the magnitude Vw of the second pulse is applied to the selected cell 21, and the polarization state is set to the intended partial polarization state. That is, data can be written to non-selected cells in a non-destructive manner. This operation is performed sequentially, and among all the cells, the cell to be set to the partially polarized state is set to the partially polarized state, whereby the write operation is completed.

Similar to the above-mentioned writing, for example, a third pulse for reading is applied as follows. First, the changeover switch 28 is changed over to select the third pulse sending circuit 27. Then, the selector switch 29 is switched to select the read circuit 32. By the voltage distribution circuit 33 and the cell selection circuit 23, for example, Vr is applied to the selected first stripe electrodes 18 of the X line, Vr / n is applied to all the unselected first stripe electrodes 18 ′, and the second selected of the Y lines is selected. By applying a voltage of 0 (v) to the stripe electrode 19 and all the unselected second stripe electrodes 19 'of (n-1) Vr / n, the selected cell Cs is supplied with V from the a direction.
Vr / n is applied to the r and non-selected cells Cy and Cx from the a direction, and (n-2) Vr / n is applied to the non-selected cell Cxy from the b direction.

Therefore, only a very small voltage of Vr / n or (n-2) Vr / n is applied to the non-selected cells, the amount of signal from the non-selected cells is very small, and the read circuit. The information flowing into 33 is mainly from the selected cell 21, and it is possible to discriminate between “0” and “1”.

Of course, if the Cp-Vp characteristics are symmetrical, n = 1/3 during writing and the voltage applied to each non-selected cell is made equal to Vw / 3, so that the matrix cell 20 as a whole has The destruction amount of the non-selected cells can be minimized, and similarly, the destruction amount at the time of reading can be minimized.

By the way, when setting the first polarization state, that is, "0", when the saturation polarization state having a large capacitance value in the saturation state among the two saturation polarization states is the first polarization state, Further, the first pulse and the first pulse having a polarity opposite to that of the first pulse so that the capacitance difference between the capacitance value C _{0 in} the first polarization state and the capacitance value C _{1 in the} partial polarization state becomes small. When the application direction of the second pulse is determined and configured, that is, the upper electrode of the ferroelectric thin film 3 is the first stripe electrode 18, and the lower electrode is the second stripe electrode 19.
In the case of configuring with, the value of n is set in the range of ∞>n> 3 to select non-selected cells Cy, Cx, C.
The voltage applied to xy can be set to V (Cy) = V (Cx) <V (Cxy), and the destruction amount of the non-selected cells can be made to be the same amount. Is
The amount of destruction of the non-selected cells can be reduced as much as possible and the non-destructiveness can be increased.

The waveform of the second pulse applied at the time of writing the data is based on the time constant determined by the resistance component R and the capacitance component C due to the first stripe electrode and the second stripe electrode, and wiring not shown. Is a pulse having a later rise time tr. That is, tr ≧ RC. As a result, as shown in FIG. 9, the voltage applied to the selected cell can be properly applied with the voltage of the magnitude Vw, and at least the excessive voltage application due to overshooting, ringing, etc. can be prevented, and the correct "1""You can write the state.

Although the description has been made based on the above embodiment, the present invention also includes the following inventions. (1) A first stripe electrode composed of a plurality of stripe-shaped electrodes arranged in parallel, and an array surface of the first stripe electrode which is spaced apart from the array surface in parallel to the array surface of the first stripe electrode. A second stripe electrode in which a plurality of stripe electrodes are arranged in parallel with each other in a direction orthogonal to the arrangement direction of the stripe electrodes, and both electrodes at the intersection of the first and second stripe electrodes. A ferroelectric memory in which memory cells are arranged in a matrix, which is composed of a ferroelectric thin film disposed between the ferroelectric memory and a driving means for selectively writing or reading information to or from the memory cells of the ferroelectric memory are provided. In the ferroelectric memory device having the ferroelectric thin film, the polarization-electrode (PV) hysteresis characteristics of the ferroelectric thin film are asymmetrical, and the driving means is arranged in the first stripe electrode and the second strike electrode. A memory cell selecting means for designating a desired memory cell by designating a striped electrode in the electrode, and a voltage V is applied to the designated striped electrode in the first striped electrode to form the first stripe. A voltage V / n (n is a finite real number and is in the range of 2 <n <3 or n> 3) is applied to a non-designated striped electrode in the electrode to designate in the second striped electrode. A voltage of 0 (v) is applied to the striped electrode formed by applying a voltage (n-1) V / n to a non-designated striped electrode in the second striped electrode. A ferroelectric memory device characterized by the above.

According to the present invention, the voltage applied to the non-designated striped electrode is made uneven between the first striped electrode and the second striped electrode, and the non-selected cell C is selected.
It is possible to make the amount of destruction caused by applying a voltage to x and Cy and the amount of destruction caused by applying a voltage to the non-selected cell Cxy in the opposite direction to approximately the same amount. It can be reduced to a minimum and crosstalk can be reduced.

The embodiment to which the present invention can be applied is, in addition to the above-described embodiment, a ferroelectric memory device of another form in which information is written in and read from a ferroelectric memory without using a partially polarized state. Can also be applied, and a crosstalk reducing effect can be obtained.

(2) In the ferroelectric memory device according to the item (1), the driving means further applies a coercive voltage V of the ferroelectric thin film to all the memory cells of the ferroelectric memory.
The voltage control means comprises a first pulse applying means for applying a voltage Ve of c or more to set one of two saturated polarization states having different polarities in the ferroelectric thin film, and the applied voltage control means. Is set to a voltage Vw having a polarity opposite to that of the voltage Ve and forming a partial polarization state in which domains of polarization states having different polarities are mixed in the ferroelectric thin film. After all the memory cells are brought to the first polarization state, which is one of the saturation polarization states, by the pulse applying means, the memory cell selected by the memory cell selecting means is applied to the voltage V by the applied voltage control means.
By applying a second pulse of w to make it a second polarization state which is a partial polarization state, information is written by two memory states of a saturated polarization state and a partial polarization state. Ferroelectric memory device.

The embodiment to which the present invention is applied corresponds to the embodiment described in the section of the embodiment of the invention. In a ferroelectric memory in which information is written in two polarization states, that is, a saturated polarization state and a partial polarization state, by reading the capacitance of each memory cell at a low potential, nondestructive reading that reads information without destroying the written information can be performed. It is possible. However, since the capacity difference between the two polarization states, the saturated polarization state and the partial polarization state, is generally as small as about 20%, the invention of (1) above is applied to destroy the information in the non-selected cell at the time of information recording. It is possible to effectively realize nondestructive reading in this information recording method by reducing

(3) In the ferroelectric memory device as described in the above item (2), of the two saturated polarization states having different polarities in the ferroelectric thin film, the saturation polarization state having the smaller capacitance value is the polarization state. The polarity of the first pulse application means is set so as to be in the first polarization state, and the value of n in the applied voltage control means is set in the range of 2 <n <3. Ferroelectric memory device.

According to the present invention, as shown in FIGS. 5 and 6, the capacitance value in the partially polarized state is larger than the capacitance values in the two saturated polarized states having different polarities. By setting the saturated polarization state to the first polarization state, the capacitance value difference ΔC between the capacitance value C0 in the saturation polarization state and the capacitance value C1 in the partial polarization state increases, so that the read margin increases. In addition, by setting the value of n within the range of 2 <n <3, the voltage applied to the non-selected cells Cx, Cy, Cxy is V (Cx) = V (Cy)> V (Cx
y), the amount of destruction of the entire non-selected cells can be reduced to a minimum, and crosstalk can be reduced. Due to these synergistic effects, reading with good S / N becomes possible.

(4) In the ferroelectric memory device as described in the above item (2), of the two saturated polarization states having different polarities in the ferroelectric thin film, the saturation polarization state having the larger capacitance value is the polarization state. The polarity of the first pulse applying means is set so as to be in the first polarization state, and the value of n in the applied voltage control means is set in the range of n> 3. Dielectric memory device.

According to the present invention, by setting the saturated polarization state of the polarity having the larger capacitance value to the first polarization state,
Even when the capacitance difference from the partially polarized state, that is, when the read margin is small, the voltage applied to the non-selected cells Cx, Cy, Cxy is set to V by setting the value of n within the range of n> 3. (Cx) = V (Cy)> V (Cx
y), the amount of destruction of the entire non-selected cells can be reduced to a minimum, and crosstalk can be reduced.

(5) In the ferroelectric memory device according to the item (3), the capacitance value C0 of the ferroelectric thin film in the first polarization state and the capacitance value C of the second polarization state in the ferroelectric thin film.
1. The ferroelectric memory device, wherein the voltage application directions of the first pulse and the second pulse are set so that the difference in capacitance value from 1 is large.

According to the present invention, as shown in FIGS. 5 and 6, the difference between the capacitance value in the partially polarized state and the capacitance values in the two saturated polarized states having different polarities is different depending on the direction of the applied voltage. Since it depends on the saturation polarization state, the difference ΔC in capacitance value between the capacitance value C0 in the saturation polarization state and the capacitance value C1 in the partial polarization state becomes large. Therefore, the read margin is further increased by setting the voltage application direction. Therefore, it is possible to read out with good S / N.

(6) In the ferroelectric memory device according to any one of the above items (2), (3), (4) or (5), the data is further recorded in the memory cell of the ferroelectric memory. The third pulse applying means for reading the stored information, and the voltage Vr of the third pulse is | Vr | <| V
A ferroelectric memory device characterized by being set in a range of w |.

According to the present invention, in a ferroelectric memory in which information is written in the memory cell in two polarization states, that is, a saturated polarization state and a partial polarization state, each memory cell has a voltage Vr lower than the partial polarization forming voltage Vw. By reading the capacity of, the nondestructive reading for reading the information without destroying the written information becomes possible.

(7) The ferroelectric memory according to any one of the above items (1), (2), (3), (4), (5) or (6). In the device, the second pulse rising time tr by the applied voltage control means is defined as R and the capacitance in the wiring portions between the first and second stripe electric electrodes and these electrodes and the voltage application means are C and C, respectively. At this time, a ferroelectric memory device is set such that tr ≧ RC.

According to the present invention, the rising time tr of the second stretched answering machine is generated by the resistance component R and the capacitance component C in the wiring portions between the first and second stripe electrodes and these electrodes and the voltage applying means. By making it slower than the time constant RC, it is possible to prevent an excessive voltage from being applied to the selected cell due to overshooting, ringing, etc., and to apply the voltage Vw accurately to the selected cell to optimize the partial polarization nourishing body. Can be formed.

(8) A memory cell in which a ferroelectric thin film is sandwiched between a second stripe electrode serving as a stripe-shaped upper electrode and a first stripe electrode serving as a stripe-shaped lower electrode in a direction crossing each other forms a simple matrix. A ferroelectric memory cell array arranged and configured;
A first cell selection circuit provided on the stripe electrode for selecting an arbitrary memory cell column; a second cell selection circuit provided on the second stripe electrode for selecting an arbitrary memory cell row; A voltage distribution circuit that distributes and outputs an arbitrary voltage to each of the first and second cell selection circuits, an n control circuit that controls the voltage distribution circuit, and a first changeover switch in the first cell selection circuit. Via the first, second, and third pulse sending circuits for outputting one of the erase pulse, the write pulse, and the write pulse, respectively, and the second cell selection circuit for the second pulse. A ferroelectric memory device comprising: a data read circuit, a data write circuit, and a polarization setting circuit which are connected via a changeover switch.

[0073]

As described above in detail, according to the present invention, a ferroelectric memory device suitable for high integration, capable of writing / reading information while reducing crosstalk, and a driving method thereof. Can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a ferroelectric memory device as an embodiment of a ferroelectric memory device and a driving method thereof according to the present invention.

FIG. 2 is a diagram showing a cross-sectional structure of a ferroelectric memory used in an embodiment according to the present invention.

FIG. 3 is a ferroelectric thin film S of the ferroelectric memory shown in FIG.
It is a diagram showing the hysteresis characteristic of rBi ₂ Ta ₂ O _9.

FIG. 4 is a diagram showing a relationship between a polarization breakdown amount ΔP and a magnitude Va of an applied pulse.

FIG. 5 is a diagram showing a relationship between a capacitance value Cp of a ferroelectric thin film SrBi ₂ Ta ₂ O ₉ and a partial polarization forming voltage Vp when a voltage is applied from an upper electrode.

FIG. 6 is a diagram showing a relationship between a capacitance value Cp of a ferroelectric thin film SrBi ₂ Ta ₂ O ₉ and a partial polarization forming voltage Vp when a voltage is applied from a lower electrode.

FIG. 7 is a diagram for explaining a relationship between cells and an applied voltage in a cell configuration of an m × m simple matrix memory.

FIG. 8 is a diagram showing a simple equivalent circuit of a matrix memory circuit at the time of writing data.

FIG. 9 is a diagram showing a waveform of a voltage applied to a selected cell.

FIG. 10 is a diagram showing a configuration of a conventional ferroelectric memory.

FIG. 11 is a diagram showing a configuration of a conventional ferroelectric memory.

12A is a diagram showing a hysteresis characteristic of a ferroelectric memory, and FIG. 12B is a diagram showing a relationship between a partial polarization forming voltage and a capacitance.

[Explanation of symbols]

1 ... Lower electrode, 2 ... Upper electrode, 3 ... Ferroelectric thin film, 4 ...
Ferroelectric cell, 18 ... First stripe electrode, 19 ... Second
Stripe electrodes, 20 ... Ferroelectric memory cell array, 2
DESCRIPTION OF SYMBOLS 1 ... Memory cell, 23a, 23b ... Cell selection circuit, 24
..., 25 ... first pulse sending circuit, 26 ... second pulse sending circuit, 27 ... third pulse sending circuit, 28, 29 ...
Changeover switch, 30 ... Polarization setting circuit, 31 ... Write circuit, 32 ... Read circuit, 33 ... Voltage distribution circuit, 34 ... N
Control circuit.

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[Procedure amendment]

[Submission date] February 26, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 1

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction contents]

[0013]

In order to achieve the above object, the present invention provides a first stripe electrode composed of a plurality of stripe electrodes arranged in parallel and an arrangement surface of the first stripe electrode. , The array planes are separated in parallel,
Further, a second stripe electrode formed by arranging a plurality of stripe electrodes in parallel with the first stripe electrode in a direction orthogonal to the first stripe electrode arrangement direction, and the first and second stripe electrodes.
Ferroelectric memory in which memory cells are arranged in a matrix, which is composed of a ferroelectric thin film disposed between both electrodes at the intersection of the stripe electrodes, and information is selectively stored in the memory cells of this ferroelectric memory. in the ferroelectric memory device and a drive means for writing or reading, the ferroelectric thin film, the polarization - a voltage (PV) hysteresis characteristic asymmetric, said drive means, said first stripe electrodes A memory cell selecting means for selecting a desired memory cell by designating a striped electrode in the first striped electrode and a striped electrode in the second striped electrode; and applying a voltage V to the striped electrode designated in the first striped electrode. , The voltage V / n (n
Is a finite real number, which is in the range of 2 <n <3 or n> 3), and a voltage of 0 (V) is applied to a designated striped electrode in the second striped electrode, A dielectric memory device having an applied voltage control means for applying a voltage (n-1) V / n to a non-designated striped electrode in the second striped electrode.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0057

[Correction method] Change

[Correction contents]

Although the description has been made based on the above embodiment, the present invention also includes the following inventions. (1) A first stripe electrode composed of a plurality of stripe-shaped electrodes arranged in parallel, and an array surface of the first stripe electrode which is spaced apart from the array surface in parallel to the array surface of the first stripe electrode. A second stripe electrode in which a plurality of stripe electrodes are arranged in parallel with each other in a direction orthogonal to the arrangement direction of the stripe electrodes, and both electrodes at the intersection of the first and second stripe electrodes. A ferroelectric memory in which memory cells are arranged in a matrix, which is composed of a ferroelectric thin film disposed between the ferroelectric memory and a driving means for selectively writing or reading information to or from the memory cells of the ferroelectric memory are provided. in the ferroelectric memory device having the ferroelectric thin film, the polarization - a voltage (PV) hysteresis characteristic asymmetric, said drive means, said first stripe electrode and the second stripe A memory cell selecting means for designating a desired memory cell by designating a striped electrode in the electrode, and a voltage V is applied to the designated striped electrode in the first striped electrode to form the first stripe. A voltage V / n (n is a finite real number and is in the range of 2 <n <3 or n> 3) is applied to a non-designated striped electrode in the electrode to designate the striped electrode in the second striped electrode. A voltage of 0 (v) is applied to the striped electrode formed by applying a voltage (n-1) V / n to a non-designated striped electrode in the second striped electrode. A ferroelectric memory device characterized by the above.

Claims (4)

[Claims] 1. A first stripe electrode composed of a plurality of stripe-shaped electrodes arranged in parallel, and an array surface of the first stripe electrode which is spaced apart from the array surface in parallel to the array surface of the first stripe electrode. One stripe electrode is arranged orthogonally to the arrangement direction, and a second stripe electrode is formed by arranging a plurality of stripe-shaped electrodes in parallel, and an intersection of the first and second stripe electrodes. Ferroelectric memory in which memory cells are arranged in a matrix, comprising a ferroelectric thin film arranged between both electrodes, and driving means for selectively writing or reading information to or from the memory cells of this ferroelectric memory In the ferroelectric memory device having: a ferroelectric thin film, the polarization-electrode (PV) hysteresis characteristics of the ferroelectric thin film are asymmetrical, and the driving means is arranged in the first stripe electrode and the second stripe electrode. Memory cell selecting means for designating a desired memory cell by designating a striped electrode in the leip electrode, and applying a voltage V to the designated striped electrode in the first striped electrode, A voltage V / n (n is a finite real number in the range of 2 <n <3 or n> 3) is applied to an undesignated striped electrode in the striped electrode, An applied voltage control means for applying a voltage of 0 (V) to the designated striped electrode and a voltage (n-1) V / n to the non-designated striped electrode in the second striped electrode. A ferroelectric memory device comprising. 2. The ferroelectric memory device according to claim 1, wherein the driving unit further applies a voltage Ve equal to or higher than a coercive voltage Vc of the ferroelectric thin film to all memory cells of the ferroelectric memory.
Is applied to set one of the two saturated polarization states having different polarities in the ferroelectric thin film, and the voltage V in the applied voltage control means is: The voltage Ve
Is set to a voltage Vw that forms a partial polarization state in which domains of polarization states having different polarities are mixed in the ferroelectric thin film, and all the memory cells are set by the first pulse applying means. After the first polarization state, which is one of the saturation polarization states, is set, the memory cell selected by the memory cell selection means is applied with the second pulse of the voltage Vw by the applied voltage control means to be in the partially polarization state. A ferroelectric memory device characterized in that information is written in two storage states, a saturated polarization state and a partial polarization state, by setting a certain second polarization state. 3. The ferroelectric memory device according to claim 2, wherein, of the two saturated polarization states having different polarities in the ferroelectric thin film, the saturation polarization state having the smaller capacitance value is the first polarization state. The polarity of the first pulse applying means is set so as to be in a polarized state, and the value of n in the applied voltage control means is set in the range of 2 <n <3. Body memory device. 4. The ferroelectric memory device according to claim 2, wherein, of the two saturation polarization states having different polarities in the ferroelectric thin film, the saturation polarization state having the larger capacitance value is the first polarization state. The ferroelectric memory is characterized in that the polarity of the first pulse application means is set so as to be in a polarized state, and the value of n in the applied voltage control means is set in the range of n> 3. apparatus.