JPH09128412A - Element library preparing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the man-hour and shorten the period for preparation by simultaneously preparing element libraries for screening and pre-layout/post- layout simulation. SOLUTION: When processing is judged as the processing for automatic element library generation and processing selected by the operation of an operator or the like is judged as the processing for automatic generation based on the circuit analyzed result, the circuit analyzed result file of a circuit simulator is read in. Then, element data are found and these data are written in the element library. Besides, when processing is judged as automatic generation by an IBIS, an IBIS file is read in and element data are found. Further, when processing is judged as element library editing, a window menu is displayed and a register editing is performed. Then, the propriety of inputted element data is checked and when the data are normal, these editing data are written in the element library. Thus, the element libraries for screening and pre-layout/ post-layout simulation are simultaneously prepared.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of creating an element library having electric characteristic data necessary for noise analysis of a printed circuit board design, and more particularly to automatic generation and editing of the element library.

[0002]

2. Description of the Related Art In a conventional element library creating method, a parameter required for noise analysis is manually read from a circuit simulation result such as SPICE of a logic element transistor circuit or an experimental graph, and as shown in FIG. The TEXT editor provided by the OS (for example,
The device data file was created by registering and editing the electrical characteristic data using a UNIX vi editor or the like).

As shown in FIG. 13, there are two types of device data files, one for screening and one for pre / post layout simulation, depending on the purpose of noise simulation.

[0004]

However, in the conventional device library creating method, two kinds of device data files have to be created depending on the purpose of the simulation even though the same device data is used. However, there was a problem that a period was required.
In addition, since the element data file is created by manually converting the electrical characteristics obtained from the analysis results of the circuit simulator into human data, the rate of human error increases, the edited data lacks validity, and many There was a problem that the number of man-hours and the period required were required.

[0005]

A device library creating method according to the present invention is a device library creating method for creating a device library required for screening and pre / post layout simulation in a printed circuit board and noise analysis. Data or industry standard format data is read, and two device libraries for screening and pre / post layout simulation are automatically created simultaneously based on the read data.

[0006]

1 is a flowchart showing a device library creating method according to an embodiment of the present invention. In the figure, 10 is automatic generation of element library, 11
Is an element library edit, and the element library automatic generation 10 performs generation from circuit analysis data and generation from an industry standard format (hereinafter referred to as IBIS) file.

Here, in the generation from the circuit analysis data of the element library automatic generation 10, the element library is automatically generated from the file in which the waveform data of the analysis result of the circuit simulator is described. In the generation from the IBIS file, the element library is automatically generated from the device model of the IBIS file. In addition, in the device library edit 11, in order to add circuit analysis data and data that cannot be obtained from the IBIS file, and to register the library from the data book, edits such as registration, change and deletion of the device library from the window menu. It is carried out.

Next, the operation of this embodiment will be described. First, the device library is read (S100), and the process selected by the operator or the like is
It is determined whether the device library is automatically generated or the device library is edited (S101). Then, each processing is performed according to the determination result of S101.

First, when it is determined in S101 that the device library automatic generation process 10 is performed, it is determined whether the process selected by the operator or the like is the automatic generation process based on the circuit analysis result or the IBIS process. Yes (S102). Then, when it is determined in S102 that the automatic generation processing is performed based on the circuit analysis result, the circuit analysis result file of the circuit simulator is read (S103).

Then, based on the read circuit analysis data, element data (High / Low level input voltage, Hi
gh / Low level output voltage, rise / fall time, High / Low level input impedance, H
High / Low level output impedance) is obtained (S104).

Here, a concrete example of how to obtain these element data will be described. (A) High / Low level input voltage FIG. 2 is a diagram showing the input / output voltage characteristics on the receiver side based on the data of the circuit analysis result file (for example, SPICE data file) of the circuit simulator. The High / Low level input voltage is obtained from the DC analysis result data on the receiver side of the element obtained by the circuit simulator as shown in FIG.

First, 20% of the output voltage is generally low.
The threshold voltage of the level is 80%, and the threshold voltage of the High level is 80%. The input voltage corresponding to the output voltage (80%) corresponds to the minimum value of the High level input voltage and the output voltage (20%). The input voltage is the maximum value of the low level input voltage. However, the percentage of the output voltage in the threshold voltage can be changed by the parameter.

An example based on the input / output voltage characteristic on the receiver side shown in FIG. 2 will be shown. First, 20% of output voltage-8
We ask for 0%. Output voltage (20) = 3.3 [V] × 0.2 = 0.66 [V] Output voltage (80) = 3.3 [V] × 0.8 = 2.64 [V] Therefore, The corresponding input voltage is obtained as Low level input voltage = 0.90 [V] High level input voltage = 2.40 [V].

Similarly, the High / Low level output voltage is also obtained from the DC analysis result data on the driver side of the element obtained by the circuit simulator. If the corresponding voltage does not exist in the data, the corresponding voltage is obtained using spline interpolation. For example, a 90% output voltage value is 2.97.
In the case of [V], the input voltage is obtained using spline interpolation.

(B) Rise / fall time FIG. 3 is a diagram showing time-voltage characteristics based on the data of the circuit analysis result file (for example, SPICE data file) of the circuit simulator. The rise / fall time is obtained from the transient analysis result data of the time-voltage characteristic of the driver side of the element obtained by the circuit simulator as shown in FIG.

First, the rising threshold is 80% of the maximum output voltage, and the rising time (Tr) is from the rising start time to the threshold voltage. Further, the falling threshold is 20% of the maximum output voltage, and the falling time (Tf) is from the falling start time to the reaching of this threshold voltage. However, the voltage percentage can be changed by a parameter. If the corresponding time does not exist on the data, the corresponding time is obtained using spline interpolation.

Here, an example based on the time-voltage characteristic shown in FIG. 3 will be shown. First, 20% -80% of the voltage is obtained.
(Threshold voltage) Voltage (20) = 3.3 [V] × 0.2 = 0.66 [V] Voltage (80) = 3.3 [V] × 0.8 = 2.64 [V] Therefore From these corresponding times, rise time = 13.0-5.0 = 8.0 [ns] fall time = 43.0-35.0 = 8.0 [ns].

(C) Input / output impedance <for pre / post layout Sim> FIG. 4 shows a current-voltage characteristic (I) based on the data of the circuit analysis result file (for example, SPICE data file) of the circuit simulator.
It is a figure showing -V characteristic). From the IV characteristic data on the receiver side of the element obtained by the circuit simulator as shown in FIG. 4, the polygonal line approximation of the IV curve is approximated by the least square method (a combination of m data is approximated to one straight line). The I-V curve is divided into a plurality of straight lines by approximation, and the impedance model is calculated from the voltage Xi [V] to Xi [V].
The range (slope) of +1 [V] is defined as the impedance of Yi [Ω], and this is repeated to automatically generate the input impedance model of the element.

Similarly, High and Low IV on the output side
An output impedance model is generated according to the characteristics. An example of the input / output impedance model thus generated is shown in FIG.

<For Screening Sim> FIG. 6 is a circuit analysis result file (for example, SPIC) of a circuit simulator.
It is the figure which showed the electric current-voltage characteristic (IV characteristic) based on the data of E data file. From the result on the receiver side of the element obtained by the circuit simulator as shown in FIG.
Specified voltage (Voltage specified by the user in a certain section)
Find the current corresponding to. However, if the corresponding current does not exist in the data, the corresponding current is obtained using spline interpolation. Then, the slope of this current voltage is used as the input impedance.

Here, an example based on the current-voltage characteristics shown in FIG. 6 will be shown. First, the designated voltage is set to voltage (s) = 0.68 [V] voltage (e) = 1.00 [V].

The currents corresponding to these are: current (s) = 15.0 [mA] current (e) = 18.5 [mA]

Therefore, the input impedance is (1.00-0.68) / (0.0185-0.01).
5), which is approximately 91.43 [Ω]. Similarly, the output impedance is created by the High and Low IV characteristics of the output side.

When element data is obtained in S104, the data is written in the element library (S20).
0). Here, the configuration of the element library will be described. The element library consists of two element data for screening and pre / post layout simulation depending on the purpose of simulation.
An example of the device library is shown below.

<For Pre / Post Layout Sim> FIG. 7
Is obtained from the input buffer model and the output buffer model generated as shown in FIG. The contents of the model are as follows.

GC_NETCLASS = LS32 GC_VOL = 2.50000E-01 GC_VOH = 3.80000E + 00 GC_TR = 6.00000E-09 GC_TF = 6.00000E-09 ::

<For Screening Sim> MODELNAME: Model name VOLTAGE_OUT_LO: Maximum / minimum value of Low level output voltage VOLTAGE_OUT_HI: Maximum / minimum value of High level output voltage VOLTAGE_IN_LO: Maximum / minimum value of Low level input voltage VOLTAGE_IN_INH level of maximum input voltage: Minimum value RISETIME: rise time FALLTIME: fall time ROUT: output impedance The contents of each model are as follows.

MODELNAME = LS32 VOLTAGE_OUT_LO = 0.0000 mV, 500.00 mV VOLTAGE_OUT_HI = 2700.0 mV, 5000.0 mV VOLTAGE_IN_LO = 0.0000 mV, 800.00 mV VOLTAGE_IN_HI = 2000.0 mV, 0.00.0 mV, 2000.0 mV. 0000nS FALLTIME = 4.0000nS, 8.0000nS ROUT = 91.43Ω ::

If it is determined in S102 that the process is automatic generation by IBIS, the IBIS file is read (S105). Then, based on the electrical characteristic data of the IBIS file, element data (High / Low level input voltage, High / Low level output voltage, rising /
Calculate the fall time and input / output impedance (S
106).

Here, a specific example of how to obtain these element data will be described. (A) High / Low Level Input Voltage FIG. 8 is a diagram showing the input / output voltage characteristics on the receiver side stored in the IBIS file. From the input / output voltage data on the receiver side as shown in FIG. 8, the minimum and maximum values of the High / Low level input voltage are obtained as in the case of generation by circuit analysis. Similarly, the High / Low level output voltage is also obtained from the input / output voltage data on the driver side.

(B) Rise / fall time FIG. 9 is a diagram showing rise / fall time data stored in the IBIS file. The rise / fall time of the IBIS file as shown in FIG. 9 is used as it is.

(C) Input / Output Impedance FIG. 10 is a diagram showing current-voltage data stored in the IBIS file. From the current-voltage data of the IBIS file as shown in FIG. 10, the minimum and maximum values of the input / output impedance are obtained similarly to the generation from the circuit analysis.

When the element data is obtained in S106, the data is written in the element library (S20).
0).

Further, in step S101, the device library is edited 11
If it is determined that the process is performed, the window menu as shown in FIG. 11 is displayed, and the data registration from the data book or the device data already registered in the library is input by keying in the input field of the window menu. The registration is edited by (S107). Then, the validity of the input element data is checked to confirm whether it is normal data (S108).

Here, an example of the contents of the validity check will be described. 1. Existence check of data Check if essential data such as model name is keyed in. 2. Check usable characters of data Check whether there is any illegal character in each data.
For example, it is checked whether there are any characters other than numbers (excluding "." And "-") in the voltage value and the like. 3. Check the magnitude of each element data value Check whether the magnitude relationship of each element data (minimum, standard, maximum) is not incorrect. For example, it is checked whether the minimum value is smaller than the maximum value. 4. Data duplication check Checks if the same data exists.

If all of these checks are judged to be valid in S108, the edited data is written in the element library (S200).

In this embodiment, the device libraries for screening and pre / post layout simulation are created at the same time, and the device library is automatically generated from the circuit analysis result data and the industry standard format (IBIS etc.). The occurrence rate of human error is reduced, the validity of element data is excellent, and the number of preparation steps and the period can be shortened. Further, since the element library is edited by the window menu, it becomes possible to improve the easiness of changing the element data and improve the validity of the element data as compared with the TEXT editor of the OS.

[0038]

As described above, according to the present invention, circuit analysis result data or industry standard format data is read, and two device libraries for screening and pre / post layout simulation are simultaneously read based on the read data. Since it is automatically created,
Device libraries for screening and pre / post layout simulation can be created at the same time,
This has an effect that the number of preparation steps and the period can be shortened. Can be expected.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a device library creating method according to an embodiment of the present invention.

FIG. 2 is a diagram showing input / output voltage characteristics on the receiver side.

FIG. 3 is a diagram showing time-voltage characteristics.

FIG. 4 is a diagram showing current-voltage characteristics (IV characteristics).

FIG. 5 is a diagram showing an example of an input / output impedance model.

FIG. 6 is a diagram showing current-voltage characteristics (IV characteristics).

FIG. 7 is an explanatory diagram illustrating element data for pre / post layout Sim.

FIG. 8 is a diagram showing input / output voltage characteristics.

FIG. 9 is a diagram showing rise / fall time data.

FIG. 10 is a diagram showing current-voltage data.

FIG. 11 is an explanatory diagram illustrating a window menu.

FIG. 12 is an explanatory diagram for explaining a conventional element library creating method.

FIG. 13 is an explanatory diagram for explaining types of simulations.

[Explanation of symbols]

 10 Element library automatic generation 11 Element library edit

Claims (2)

[Claims] 1. A device library creating method for creating a device library required for screening and pre / post layout simulation in a printed circuit board and noise analysis, wherein circuit analysis result data or industry standard format data is read, and the read data is read. An element library creating method characterized by automatically creating two element libraries for screening and pre / post layout simulation simultaneously. 2. The element library creating method according to claim 1, wherein a window menu for element library editing is displayed at the time of editing the element library, and edit data is input based on the window menu. .