JPH09121210A - Virtual terminal - Google Patents

Abstract

A virtual terminal device in an ATM network for executing an ABR service is realized with a relatively simple configuration. A cell storage unit 1 for storing a data cell DT.
And the VPI / VCI according to the header information of the data cell DT.
VPI / VCI identification section 3 for identifying the
Cell interval table 4 for storing cell interval information for sending
And the cell interval table 4 according to the control information of the B-RM cell.
B-RM cell processing unit 5 that rewrites the cell interval information of
And an F-RM cell generation unit 6 that generates an F-RM cell to be inserted for each predetermined number of data cells DT read from the cell storage unit 1, and control of writing the received data cells DT into the cell storage unit 1. , Control for reading out and transmitting the data cells DT from the cell storage unit 1 at the cell intervals according to the cell interval information of the cell interval table 4 and for sending the F-RM cells from the F-RM cell generating unit 6. And part 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a virtual terminal device in an ATM network for executing an available bit rate (ABR) service. AT
AB in M (Asynchronous Transfer Mode) network
R (Available Bit Rate) service is known. This ABR service declares the minimum cell rate (MCR; Minimum Cell Rate) and the peak cell rate (PCR; Peak Cell Rate) at the time of call setup, and the AT
In the M network, communication quality is guaranteed for traffic below the minimum cell rate MCR, and communication quality is guaranteed as much as possible for traffic above it. Also, the terminal device controls the transmission cell rate so as not to exceed the peak cell rate PCR.

In this ABR service, an F-RM (Forward Resource Management) cell is transmitted as a control cell for each predetermined number of data cells transmitted from a transmitting terminal device, and a switch (ATM switch) in an ATM network is transmitted.
Transfers congestion occurrence and the like as control information of this F-RM cell. Further, when the receiving terminal device receives the F-RM cell of the control cell in the forward direction via the ATM network, the receiving terminal device loops back the B-RM (Backward Res.
ource Management) Send as a cell. This BR
Since the congestion occurrence information of the F-RM cell is added as the control information of the M cell, the transmitting terminal device receives the B-RM cell to identify the presence or absence of the congestion occurrence,
The outgoing cell rate can be controlled.

Since the function of the RM cell of the transmitting terminal device and the receiving terminal device in this ABR service is added to the switch (ATM switch) of the ATM network, and this switch performs the same operation as the terminal device, This is called a virtual terminal device, and the present invention relates to this virtual terminal device.

[0004]

2. Description of the Related Art FIG. 8 is an explanatory view of a conventional example. FIG. 8A shows an ATM between a transmission terminal device 51 and a reception terminal device 52.
A connection is formed through the switches (SW) 53 to 55 (ATM switch) that form the network, and the transmission terminal device 5
The data cells (user cells) sent from the cell No. 1 and the F-RM cells sent every predetermined number of the data cells are transferred to the receiving terminal device 52 via the switches 53 to 55. The receiving terminal device 52 loops back this F-RM cell and sends it out as a B-RM cell. Therefore, for the RM cell, a control loop including the transmitting terminal device 51, the receiving terminal device 52, and the switches 53 to 55 is formed as shown by a solid arrow.

FIG. 9 is a diagram for explaining the format of the RM cell. GFC / VPI in the header of 5 bytes is
General flow control GFC or network node in case of user network interface (UNI)
Virtual path identifier VPI for interface (NNI)
Is shown. Therefore, the virtual path identifier VPI has an 8-bit or 12-bit configuration. Further, VCI is a virtual channel identifier having a 16-bit structure, and PT is a payload type having a 3-bit structure. For example, "000" indicates a user cell without congestion, and "110" indicates an RM cell. CL again
P indicates cell loss priority display of 1-bit structure, and CRC indicates header error control of 8-bit structure.

[0006] The 48-byte payload of the RM cell is a 1-byte RM protocol identifier RM PRO.
TOCOL ID and DIR (Direction) are direction indication bits. In the RM cell, "0" indicates an F-RM cell and "1" indicates a B-RM cell. Also BN (Backwards
Explicit Congestion Notification) is an ATM
B-RM generated at switches 53-55 in the network
Reverse congestion notification bit indicating cell, CI (Congestion)
Indication) is a congestion indication bit, NI (NoIncrease)
) Is a cell rate non-increasing bit, RA (Request Ackn
owledge) indicates a request acknowledge bit that is not used in the ABR service, and Res indicates an unused bit.

ER (Explicit Cell Rate) is an allowable cell rate of 2 bytes, CCR (Current Cell Rate).
Rate) is the current cell rate of 2 bytes, MCR (Min
imumCellRate) is the minimum cell rate of 2 bytes,
QL (Queue Length) has a 4-byte structure and a queue length, SN (S, which is not used in the ABR service.
Sequence Number) is a 4-byte sequence number. Also, unused bit Re consisting of 30 bytes + 6 bits
s, and finally includes a CRC (cyclic code check bit) of 10 bits.

In FIG. 8A, each of the switches 53 to 55 passes through the VPI / VCI compatible F-R when a congestion corresponding to the VPI / VCI occurs in its own switch.
The congestion indicator bit CI of the M cell indicates that there is congestion and transfers it. When the receiving terminal device 52 receives this F-RM cell, it rewrites the direction indicating bit DIR and the like, and the B-RM.
Send it back as a cell. In the switches 53 to 55 through which this B-RM cell passes, the congestion indication bit CI
If there is congestion, the VPI / VC
The cell rate of the cell flow rate control corresponding to I is controlled to be lowered.

Further, the transmission terminal device 51 which has received this B-RM cell controls so as to reduce the transmission cell rate when congestion is indicated by the congestion indication bit CI.
Further, when there is no congestion, the transmission cell rate can be increased within a range not exceeding the peak cell rate PCR.

However, the transmission cell rate in the transmission terminal device 51 is controlled by receiving the B-RM cell which is returned and transmitted in the reception terminal device 52,
Since the transmission cell rate is controlled after the transmission time of a long control loop, the time required for congestion recovery increases.

Therefore, the function of the virtual terminal device shown in FIG. 8B was proposed. That is, the transmission virtual terminal function VS is provided to the switches 63 to 65 (SW) of the ATM network forming the connection between the transmission terminal device 61 and the reception terminal device 62.
(Virtual Source) and reception virtual terminal function VD (Virtual Source)
(Tual Destination) and the RM cell is turned back at each of the switches 63 to 65, the control loop can be shortened compared to the case shown in (A). Therefore, the transmission cell rate in the transmission terminal device 61 is reduced. This makes it possible to quickly follow the occurrence of congestion in the ATM network, and a stable ATM system can be constructed.

FIG. 8C shows a main part when the switches 63 to 65 are virtual terminal devices. 71 is a reception virtual terminal function VD, 72 is a transmission virtual terminal function, 73 is a buffer memory, and 74 is F. -RM generation unit, and 75 indicates a B-RM cell processing unit.

The data cell D is received by the reception virtual terminal function 71.
T and F-RM cells for each predetermined number of the data cells DT are received, and the F-RM cells are folded back as B-RM cells, and the data cells DT are temporarily stored in the buffer memory 73 and received. The data cell DT is read from the buffer memory 73 and transmitted at the transmission cell rate according to the control information of the B-RM cell. Further, the F-RM cells from the F-RM cell generation unit 74 are inserted and transmitted for every predetermined number of the data cells DT.

[0014]

The virtual terminal device in the ABR service needs to have the functions of the transmitting terminal device and the receiving terminal device, and controls the sending cell rate by V.
Since it is necessary to support PI / VCI, for example, as shown in FIG.
It is obvious that the buffer memory 73 or the like for temporarily storing the received data cell DT is required as shown in (C) of FIG. However, no specific configuration has been proposed. The present invention has a relatively simple structure and is AB
It is an object to provide a virtual terminal device that executes an R service.

[0015]

The virtual terminal device of the present invention comprises (1) a cell storage unit 1 for storing a received data cell DT in a virtual terminal device in an ATM network for executing an ABR service, VP for identifying the virtual path identifier / virtual channel identifier by the header information of the received data cell DT
The I / VCI identification unit 3, the cell interval table 4 storing the cell interval information for transmitting the data cell DT, and the control cell (B-RM cell) in the reverse direction are received, and the control information of this control cell is received. Then, the allowable transmission rate is calculated by calculating the cell interval corresponding to the allowable transmission rate and rewriting the cell interval information in the cell interval table 4 (B-
(RM cell) processing unit 5 and a control cell (F-R cell) for generating a forward control cell (F-RM cell) to be inserted into every predetermined number of data cells DT read and transmitted from the cell storage unit 1.
M cell) generation unit 6 and data cell DT to cell storage unit 1
Of the transmission data cell DT with reference to the cell interval table 4, and the forward control cell (F-RM) from the control cell (F-RM cell) generation section 6. Control unit 2 for controlling the transmission of cells).

(2) The received data cell DT is stored in the cell storage unit 1
The address written in is stored according to the identification information by the VPI / VCI identification unit 3, and the address is stored in the data cell DT.
A cell address storage unit which is a read address when reading
An empty address storage unit that stores an address of an empty area of the cell storage unit 1 and reads the address as a write address of the reception data cell DT, and an interval of the transmission data cell DT according to the cell interval information read from the cell interval table 4. Can be provided and a counter for notifying the control unit 2 can be provided.

(3) Further, the cell address storage unit is set to VPI / V.
The CI identification unit 3 can be configured by a FIFO memory corresponding to the identification information, and the empty address storage unit can be configured by one FIFO memory.

(4) Also, an empty address part indicating the start address and the end address of the empty area of the cell storage part 1, and VP.
A control memory including a head address and a cell address portion indicating a tail address of the data cell DT stored in the cell storage portion 1 corresponding to the identification information by the I / VCI discriminating portion, and head addresses of an empty address portion and a cell address portion A chain memory that indicates an address chain between the end address and the last address, and controls the writing and reading of the data cell DT to and from the cell storage unit 1 by referring to the control memory, and the forward direction from the control cell generation unit. A control unit for controlling transmission of a control cell (F-RM cell) can be provided.

[0019]

1 is an explanatory view of a first embodiment of the present invention, in which 1 is a cell storage unit, 2 is a control unit, and 3 is a VPI / VC.
I identification unit, 4 is a cell interval table, 5 is a B-RM cell processing unit as a processing unit for control cells in the reverse direction, 6 is an F-RM cell generation unit as a generation unit for control cells in the forward direction, 7
Is a selector. This embodiment shows a portion of a transmission virtual terminal function, and a portion of a reception virtual terminal function of receiving an F-RM cell and sending it back as a B-RM cell is omitted, but a receiving terminal of a conventional example is omitted. The B-RM cell sending means in the device can be applied.

The received data cell DT (user cell)
Is added to the cell storage unit 1 and the VPI / VCI identifying unit 3, and the virtual path identifier VPI / virtual channel identifier VCI is identified in the VPI / VCI identifying unit 3 by the header information of the data cell DT, and the control unit 2 Added to. Based on this VPI / VCI information, the control unit 2 writes the received data cell DT in the cell storage unit 1.

The cell interval table 4 is a VPI / VCI.
Correspondingly, the cell interval information is stored, and the control unit 2 reads out this cell interval information and reads out and sends out the data cell DT from the cell storage unit 1 corresponding to VPI / VCI. In addition, the F-RM cell generation unit 6 is provided for each predetermined number of data cells DT.
Then, the F-RM cell to which the transmission cell rate or the like at that time is added as control information is transmitted. The data cell DT and the F-RM cell are switched by controlling the selector 7,
Send as shown as + (F-RM).

The B-RM cell processing unit 5 receives the received B-
Congestion indication bit CI of RM cell (control cell in the opposite direction)
The allowable transmission rate ACR is calculated based on control information such as the allowable cell rate ER and the cell interval (1 / ACR) is calculated based on the allowable transmission rate ACR. Rewrite.

Therefore, the F-RM cell is transmitted between the switches (ATM exchanges), and the F-RM cell is transmitted to the B-R.
A control loop for sending back as M cells is formed, and when congestion occurs, the sending cell rate can be controlled by updating the cell interval table 4 in each switch.
Congestion in the ATM network that executes services can be quickly recovered, and stable ATM cell transmission can be made possible.

FIG. 2 is an explanatory view of the second embodiment of the present invention, in which 11 is a cell storage unit, 12 is a control unit, and 13 is VPI /.
VCI identifier, 14 is a cell interval table, 15 is B-R
An M cell processing unit, 16 is an F-RM cell generation unit, 17 is a selector, 18 is a cell address storage unit, 19 is an empty address storage unit, and 20 is a counter.

The empty address storage unit 19 is used for the cell storage unit 11
Of the empty address, and the cell address storage unit 18 stores
The address of the data cell DT stored in the cell storage unit 11 is stored in correspondence with VPI / VCI. The counter 20 is configured to support VPI / VCI, and the VPI / VC from the cell interval table 14 is controlled by the control unit 12.
The cell interval corresponding to I is set, the clock signal (not shown) is started to count up or count down, the cell interval time is measured, and when the measured time is reached, the control unit 12 is interrupted.

The control unit 12 sets one of the empty addresses stored in the empty address storage unit 19 as a write address, writes the received data cell DT to the write address, and outputs VPI / V.
For VPI / VCI correspondence identified by the CI identification unit 13,
The address where the received data cell DT is written is stored in the cell address storage unit 18.

The cell interval table 14 updates the cell interval corresponding to VPI / VCI by the B-RM cell reception processing by the B-RM cell processing unit 15 as in the above-mentioned embodiment. The controller 12 reads the VPI / VCI-compatible data cell DT read from the cell storage 11 and sends it out from the cell interval table 14 every time the data cell DT is read and sent.
The cell interval information corresponding to the VCI is read out and the VPI / VCI is read.
The corresponding counter 20 is set and the cell interval is counted by the counting operation.

When the time for measuring the cell interval by the counter 20 is reached, the control unit 12 is interrupted.
Identifies the VPI / VCI compliant interrupt, reads the address from the cell address storage unit 18, and
The data cell DT is read with the read address of 1. Regarding the control of the F-RM cell generation unit 16 and the selector 17, F-RM cells are inserted and transmitted for every predetermined number of data cells DT, as in the above-described embodiment.

FIG. 3 is a diagram for explaining the operation of the second embodiment of the present invention. The same symbols as those in FIG. 3 indicate the same parts, and the cell address storage unit 18 is a FIFO corresponding to virtual connections VC1 to VCn by VPI / VCI. (First-in-first-out) memory is used, and the empty address storage unit 19 is provided as one FIF.
The case where the O-memory is used is shown. The empty address storage unit 19 stores the address of the data cell DT when it is read from the cell storage unit 11.

Further, the control unit 12 reads the oldest address of the empty address storage unit 19 and uses it as the write address WA of the cell storage unit 11, and the oldest address corresponding to the virtual connections VC1 to VCn of the cell address storage unit 18. The data is read and used as the read address RA of the cell storage unit 11. The counter 20 also has virtual connections VC1 to VCn.
The cell interval corresponding to the virtual connections VC1 to VCn from the cell interval table 14 is set.

The counter 20 corresponding to the virtual connection is
At the cell interval measurement time, the control unit 12 is interrupted, the control unit 12 identifies the interrupt corresponding to the virtual connection, reads the address from the cell address storage unit 18, and reads the address from the cell storage unit 11. The data cell DT is read out with RA. When the F-RM cell is transmitted after reading and transmitting the predetermined number of data cells DT, the control unit 12 causes the F-RM cell generation unit 16 and the selector 17 to operate.
Is controlled to transmit the F-RM cell.

Since the cell address storage unit 18 is composed of the FIFO memory corresponding to the virtual connection, the data from the cell storage unit 11 can be stored in accordance with the transmission cell rate corresponding to the virtual connection without changing the order of the received data cells DT corresponding to the virtual connection. The cell DT can be read and sent out.

FIG. 4 is an explanatory view of the third embodiment of the present invention, in which 21 is a cell storage unit, 22 is a control unit, and 23 is VPI /.
VCI identification unit, 24 cell interval table, 25 BR
M cell processing unit, 26 F-RM cell generation unit, 27 selector, 28 chain memory, 29 control memory, 30
Is a counter.

The control memory 29 stores an empty address part indicating a start address and an end address of an empty area of the cell storage part 21, and an start address and an end address storing data cells corresponding to VPI / VCI. The chain memory unit 28 includes an empty address chain part that indicates a chain address between the start address and the end address of the empty address part, and VPI / V.
It includes a cell address chain portion indicating a chain address between a CI-addressed start address and a CI end address.

The control unit 22 writes a data cell at the start address of the empty address part of the control memory 29, and updates the start address according to the contents of the empty address chain part. Further, the address where the data cell is written is written in the cell address portion of the control memory 29 as the last address corresponding to VPI / VCI, and the contents of the cell address chain portion of the chain memory 28 are updated.

VPI / VCI of the cell interval table 24
The cell interval is measured by the VPI / VCI compatible counter 30 on the basis of the corresponding cell interval information, and at the cell transmission timing, the control unit 22 determines from the cell address part of the control memory 29 that the VPI / VCI compatible head is present. Based on the address, the data cell is read from the cell storage unit 21 and transmitted. Then, the start address is updated to be the end address of the empty address portion of the control memory 29. Further, the head address of the cell address portion of the control memory 29 is updated according to the VPI / VCI compatible address chain of the chain memory 28. Further, the control unit 22 controls the VPI / VC
Every time a predetermined number of I-compatible data cells are transmitted, the F-RM cell is transmitted from the F-RM cell generation unit 26.

FIG. 5 is an explanatory diagram of an address chain according to the third embodiment of the present invention. In a memory configuration having a cell buffer section for storing data cells and a chain section, the next cell buffer is added to the chain section. By writing the addresses of the sections, it is possible to sequentially form the address chains of the cell buffer section, as indicated by solid arrows.

Therefore, the control memory 29 is replaced by the cell storage unit 2
An empty address portion 29a including the start address FLH (free list head) and the end address FLT (free list tail) of the empty area of 1 and the start address H corresponding to the virtual connections VC1 to VCn based on VPI / VCI.
The cell address portion 29b includes D, the last address TL, and the mark MK.

Further, the chain memory 28 is provided with an empty address chain portion showing an address chain between the head address FLH and the tail address FLT of the empty area, and VC1 to VC1.
A cell address chain section showing an address chain between the head address HD and the tail address TL corresponding to Cn is included. Mark MK is VC
It indicates whether or not a data cell is stored in the cell storage unit corresponding to 1 to VCn.

FIG. 6 is an explanatory diagram of the operation at the time of writing the data cell. In the state (A), the empty address portion 29a of the control memory 29 is set to 9 as the leading address FLH of the empty area of the cell storage portion 21. Address, 6 as the last address FLT
The address is shown, and the cell address section 29b shows the case where the head address HD and the tail address TL are stored in correspondence with VPI / VCI, and the empty address chain section 28a of the chain memory 28 has FLH = 9, FLT = 6
CH

By [9] = 2, CH [2] = **, the start address FLH is address 9, the end address FLT is address 6,
It indicates that the chain address of the address is address 2, and the chain address of this address is **.

Further, the cell address chain section 28b is a HD
[4] = 3, TL [4] = 5, HD [8] = 1, TL
By [8] = 1, CH [3] = 5, VPC / VCI =
The head address HD in which the data cell of 4 is written is the address 3,
It shows that the last address TL is 5, the head address HD in which the data cell of VPI / VCI = 8 is written is 1, the last address TL is 1, and the chain address of address 3 is 5. ing.

In this state (A), VPI / VC
When a data cell of I = 4 is received and written in the cell storage unit 21, the control unit 22 controls the cell storage unit 21 because the start address FLH by the empty address unit 29a indicates address 9 as shown in (B). The received data cell DT is written to the address 9 of the control memory 29, and the address 9 is no longer a free area. Therefore, the start address FLH of the empty address part 29a of the control memory 29 is set to

According to the address chain of [9] = 2, FLH =
Update to 2. Accordingly, the empty address chain unit 2
The contents of 8a are FLH = 2, FLT = 6, CH [2] =
Updated to **.

Further, since the data cell of VPI / VCI = 4 is written in the address 9 of the cell storage unit 21, the cell address unit 29b of the control memory 29 causes the end address TL.
Is updated from No. 5 to No. 9. Then, the cell address chain unit 28b of the chain memory 28 is VPI / V
HD [4] = 3, TL [4] = 9 for CI = 4 correspondence
To the address chain of CH [5] = 9.

In this state, for example, VPI / VCI = 8
When receiving the data cell of and writing to the cell storage unit 21,
Start address F of empty address section 29a of control memory 29
With LH = 2, the data is written into the address 2 of the cell storage unit 21, and its head address FLH is set to F according to CH [2] = ** of the empty address chain unit 28a of the chain memory 28.
Update to LH = **. Further, the last address TL of the cell address part 29b of the control memory 29 is set to the second address, and the cell address chain part 28b of the chain memory 28 is set to H
Updated to D [8] = 1, TL [8] = 2, and CH [1]
= 2 chain address is added.

FIG. 7 is an explanatory diagram of the operation at the time of reading the data cell, and the state (A) is the same as the state (A) of FIG. In this state, when the data cell of VPI / VCI = 4 is read from the cell storage unit 21, the head address HD corresponding to VPI / VCI = 4 of the cell address unit 29b of the control memory 29 indicates the address 3, 3 of cell storage unit 21
The data cell DT is read from the address and transmitted.

Then, as shown in (B), the head address FLH of the empty address portion 29a of the control memory 29 remains unchanged, but the tail address FLT is the data cell D.
T indicates the read third address. Therefore, the empty address chain unit 28a of the chain memory 28 is FL
H = 9, FLT = 3, CH

[9] = 2, CH [2] = *
*, CH [6] = 3 is updated. Also chain memory 2
The cell address chain unit 28b of No. 8 uses the above CH [3]
= 5, the chain address of the address 3 is the address 5, so that HD [4] = 5 is updated, and the start address HD and the end address TL of the cell address portion 28b of the control memory 29 both indicate the address 5. Becomes

As described above, the control unit 22 refers to the chain memory 28 and the control memory 29 and the cell storage unit 21.
The writing and reading of the data cell DT to and from the data memory DT are controlled, and the update of the chain memory 28 and the control memory 29 is controlled. Of F-RM cells and F-RM cells. Also B-R
Since the cell interval information of the cell interval table can be updated according to the control information of the B-RM cell received by the M cell processing unit 25, when the congestion occurs, the cell interval can be extended and the congestion can be immediately recovered. .

[0048]

As described above, according to the present invention, the cell storage unit 1, the control unit 2, the VPI / VCI identifying unit 3 for identifying the VPI / VCI by the header information of the received data cell DT, and the cell interval. The table 4, the reverse control cell (B-RM cell) processing unit 5, and the forward control cell (F
-RM cell) generation unit 6, and writes the received data cells DT in the cell storage unit 1 in correspondence with VPI / VCI, and stores the cell storage unit 1 at intervals according to the cell interval information corresponding to VPI / VCI in the cell interval table 4. From the control cell (F-RM cell) generating section 6 for every predetermined number of data cells DT, and the control cell in the reverse direction is also transmitted. A switch (ATM switch) by receiving the (B-RM cell) and rewriting the cell interval information in the cell interval table 4 with the control information.
With a short control loop between them, there is an advantage that it is possible to provide a virtual terminal device that efficiently executes an ABR service.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a second embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the second embodiment of the present invention.

FIG. 4 is an explanatory diagram of a third embodiment of the present invention.

FIG. 5 is an explanatory diagram of an address chain according to a third embodiment of this invention.

FIG. 6 is an explanatory diagram of an operation when writing a data cell.

FIG. 7 is an explanatory diagram of an operation at the time of reading a data cell.

FIG. 8 is an explanatory diagram of a conventional example.

FIG. 9 is an explanatory diagram of a format of an RM cell.

[Explanation of symbols]

 1 Cell Storage Unit 2 Control Unit 3 VPI / VCI Identification Unit 4 Cell Interval Table 5 B-RM Cell Processing Unit 6 F-RM Cell Generation Unit 7 Selector

Claims (4)

[Claims] 1. A virtual terminal device in an ATM network for executing an available bit rate (ABR) service, a cell storage unit for storing a received data cell, and a virtual path identifier based on header information of the received data cell. / VPI / VCI identifying section for identifying a virtual channel identifier, a cell interval table for storing cell interval information for transmitting the data cell, and a control cell in the opposite direction received and permitted by the control information of the control cell A control cell processing unit that calculates a transmission rate, calculates a cell interval corresponding to the allowable transmission rate, and rewrites the cell interval information in the cell interval table; and the data that is read from the cell storage unit and sent out. A control cell generation unit that generates a control cell in the forward direction to be inserted for each predetermined number of cells, and writing the data cell to the cell storage unit, A control unit is provided, which refers to the cell interval table and controls reading of transmission data cells from the cell storage unit and transmission of the control cells in the forward direction from the control cell generation unit. A virtual terminal device characterized by the above. 2. A cell address storage unit that stores an address in which the received data cell is written in the cell storage unit according to identification information by the VPI / VCI identification unit, and uses the address as a read address when reading a data cell. An empty address storage unit that stores an address of an empty area of the cell storage unit and reads the address as a write address of the reception data cell, and a transmission data cell of the transmission data cell according to the cell interval information read from the cell interval table. The virtual terminal device according to claim 1, further comprising a counter that measures an interval and notifies the control unit. 3. The cell address storage unit is provided with the VPI /
3. The virtual terminal device according to claim 2, wherein the virtual terminal device is configured by a FIFO memory corresponding to identification information by the VCI identification unit, and the empty address storage unit is configured by one FIFO memory. 4. An empty address part indicating a start address and an end address of an empty area of the cell storage part, and the VP.
A control memory including a cell address part indicating the start address and the end address of the data cell stored in the cell storage part corresponding to the identification information by the I / VCI identification part, and the start of the empty address part and the start of the cell address part A chain memory indicating an address chain between an address and a last address, and controlling the writing and reading of data cells to and from the cell storage unit by referring to the control memory, and the control cell generation unit from the control cell generation unit. The virtual terminal device according to claim 1, further comprising a control unit that controls transmission of a control cell in a forward direction.