JPH09120335A - Input device for computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform conversion to data with which the movement of a large part, etc., of the body can be recognized by tranducing the operation of a riser member connected to a support member on which a person can sit into an electric signal and transmitting it to a computer system. SOLUTION: The input device 18 consists of the riser member 200 including a right-left symmetrical main body 202 and a cross member 208 having a couple of handle members 210 and 212 at both ends and a rigid support member 206 which has a top surface 216 where a person can sits, and the riser member 200 is sized corresponding to the sitting height of an infant. The right-left symmetrical main body 202 of the riser member 202 is in tubular structure and an elastic device 218 stored in a hollow internal space 203 holds the riser member 200 at a specific position on the rigid support member 206 when the riser member 200 is applied with no external force. A transducing device consisting of plural position sensors, direction determining circuits, and interface circuits senses the operation of the riser member 200 and transmits it to the computer in the form of the electronic signal.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to pointing devices for use in digital systems, and more particularly to input devices responsive to an individual's overall physical activity.

[0002]

Video graphics computer systems are well known and popular consumer products. A typical system includes a data processing unit that connects to a conventional television set to display an image of a game or other application. The data processing unit receives control software from read only memory (ROM), which is typically packaged in the form of a cartridge. The cartridge is plugged into the data processing unit in a removable manner. The data processing unit includes a mouse, joystick, touch pad, touch screen, switch pad, light At least one pointing device, such as a gun, is also connected.

A data processing unit is typically a single central processing unit (CPU) and associated volatile and nonvolatile, including all random access memory (RAM) and bootstrap read only memory (boot ROM). A memory, a television (RF video) signal generator,
And an input / output processor for interfacing to various pointing devices. These devices are in circuit communication. One of the distinctive features of such a system is the use of a motherboard or system planar to electrically connect these components together.

A joystick is a directional type pointing device used to enter directional data into a computer system. A joystick typically includes a base and an elongated "stick" or upstanding member, which is generally held in the user's hand. Generally, a "stick" swings from one point on the base,
It has a default position perpendicular to the base. The pivoting movement of the stick from the default vertical position is interpreted as a directional input parallel to the base in the direction required to displace the stick from the default vertical position. Generally, a button is located on the top of the stick. Computer based on swiveling movement of stick
For applications running on the system,
Input is customarily made from a position sensor.

[0005]

Generally, the use of joysticks and other input devices requires precise muscle movements of the hand and / or wrist, ie,
It requires a precise movement system. However, young children do not have enough precision movements to allow the use of typical joystick input devices. However, even young children can move large parts of the body, such as arms, legs and torso. Therefore, there is a need for an input device suitable for young children that translates movements of a large body part or parts of the body into data recognizable by a computer system.

[0006]

SUMMARY OF THE INVENTION The present invention provides an input device for converting movement of a large body part or parts of a body into data recognizable by a computer system. The input device includes a rigid support member having a size sufficient to be used by a human for sitting purpose, a rising member, a connecting device for connecting the rising member to the supporting member, and a movement of the rising member. A converter in physical communication with the riser member for transmitting its motion to the computer system in the form of a typical electrical signal, and a support member for the riser member when the riser member is not subject to external forces. An elastic device in physical communication with the riser member to maintain it in place relative to the riser member.

The rising member includes a left-right symmetrical body and a cross member. The cross member can be of various designs, including a straight cross member or a syncline cross member. Further, the cross member may include handle members at both ends thereof. Alternate embodiment riser members may include tactile spheres or wheels instead of cross members. You can also rotate and twist the rising member,
As a result, the rising member and the elastic device are fixed to the support member so that a plurality of different degrees of movement are possible.

The converter includes a plurality of position sensors, which can be analog or digital in nature, a direction determining circuit, and an interface circuit. The direction determining circuit interprets analog or digital signals from the position sensor and converts such signals into direction data. The interface circuit transmits directional data, as well as other data, including device characteristics and chaining order, among others.

Thus, when a child interacts with the stand-up member by a large body part or parts of the body, such movement is detected by the position sensor and communicated to the computer system. In general, children grip a cross member or tactile sphere and move it by the action of any part of the body or parts of the body to interact with the rising member.

Accordingly, one of the advantages of the present invention is to provide an input device that translates movements of a large body part or parts of the body of a child into data recognizable by a computer system.

Another advantage of the present invention is that a computer is capable of calculating a plurality of different degrees of motion that represent movements of a body part of a child.
It is to provide an input device for converting into a system.

The above and other advantages of the invention will be more apparent from the detailed description of the invention.

The accompanying drawings, which are incorporated in and constitute a part of this specification, show an embodiment of the present invention. This embodiment, together with the above-described outline description of the present invention, will be described in detail below. It serves to illustrate the principles of the present invention.

[0014]

1 and 2, a computer system 10 of the present invention is shown. As shown in FIG. 1, the system 10 includes a program cartridge 14 detachably connected thereto.
And a data processing unit 12 with. The data processing unit 12 also includes a standard television receiver (TV) 1
6 and the input device 18 are also connected. Input device 18
Sends to the data processing unit 12 directional type data corresponding to the movement of the rising member 200 of the input device.
Although not shown in FIG. 1, the standard TV 16 can be replaced with a pair of speakers and a display device that accepts the composite video signal. The input device 18 is connected to the data processing unit 12 via a serial data link 22. TV 16 has an RF video line 24
It is connected to the data processing unit 12 via.

Cartridge 14 has an edge card connector, generally designated 26, which is a cartridge
Connect to connector 28, thereby allowing cartridge 14
The devices therein are electrically connected to the devices within the data processing unit 12.

The processing unit 12 has a SY associated with it.
Central processing unit (CPU) having STEM bus 31
30, an audio / video (A / V) controller / auxiliary processor 32, and a SYS generated by the A / V controller / auxiliary processor 32 from the SYSTEM bus 31.
A system memory 33 connected to the TEM bus 34,
First and second decoder chips (not shown), an I / O coprocessor 36, two cartridge connectors (one shown at 28, the other not shown),
It includes additional circuitry 38 needed to generate audio and video signals, and expansion connector 39. These devices are connected in circuit connection as shown. The additional circuit 38 is shown in FIG. 2 and described in more detail in the text accompanying FIG.

The CPU 30 is a DATA bus, ADDRESS bus, CONTROL, as is well known in the art.
A plurality of buses called L buses are generated. These three buses are collectively called the SYSTEM bus 31. In the preferred embodiment, CPU 30 is an Intel Corporation (3065 Bowers Av
e., Santa Clara, California, 95051) 80376
It is. The 80376 is well known in the art and is also known from the Intel Corp. 80386SX.
Is a variation of. The 80376 differs from the 80386SX in that the 80376 starts up in 32-bit mode instead of 16-bit mode. Specifically, the CR0 register is forced to 0011H (hexadecimal notation of 0011)
State, bit 0 forced to logic 1 and 376
Effectively operate in 32-bit memory mode.
Paging is enabled to allow virtual 386 operation.

The A / V controller / auxiliary processor 32
Three spare general-purpose I / O decoder lines (GPIO1, GPIO2, GPIO3) are generated from the SYSTEM bus 31 and each of them is set to 1 within the 32-bit I / O address range.
Performs 6-bit address decoding. A general purpose decoder can be used to provide three active low chip enables to devices external to the A / V controller / coprocessor 32. The data processing unit 12 uses this general-purpose decoder to input / output auxiliary processor 36 (GPIO).
1) and decode the address range to the two cartridge connectors (GPIO2 and GPIO3). For the remaining circuitry of the A / V controller / coprocessor 32,
This will be described below.

The system memory 33 includes a screen RAM and
It includes system RAM and bootstrap ROM (neither shown). On-board screen RAM and system RAM are 1 megabyte of 32-bit DRAM. One suitable DRAM is 256 kilobytes from Toshiba configured to provide 32-bit memory.
6-bit memory chip TCS14170BJ
There is. A portion of the CPU 30 address space consists of several 8-bit blocks in the A / V controller / coprocessor 32.
Decoded in register. All internal locations are on even address boundaries, and word-wise I / O read / write can be performed at appropriate locations. In this particular example,
It is not possible to write byte-wise on a word-wise register, nor can I / O cycles be used to access odd addresses.

The bootstrap ROM is always 16 bits wide. The bootstrap ROM includes two 27C512 erase / programmable read-only memories manufactured by many manufacturers, thereby providing a 128K bootstrap ROM. After reset, 1 in the range of F20000H to FFFFFFH including ROM and internal memory
The megabyte window is repeated over the 16 megabyte address range.

The system memory 33 is shared by a plurality of devices. The A / V controller / auxiliary processor 32
Arbitrator for system memory 33 (arbitrato
r). Therefore, the SYSTEM bus 31 is
/ V controller / auxiliary processor 32
M bus 34 (DATA bus not shown, AD
(Including a DRESS bus and a CONTROL bus). As a result, the system memory 33 is
It is accessed via the TEM bus 34.

The input / output auxiliary processor 36 is the input device 1
8, a keyboard (not shown), various control devices (not shown), a mouse (not shown), an optional device such as a printer (not shown), and the like, and an interface between the CPU 30 and a large number of input / output devices. take. In the preferred embodiment, this I / O coprocessor 36 is a Motorola preprogrammed MC68HC705C8 (hereinafter "68HC705") operating at 2 MHz. 68HC705
The I / O coprocessor 36 uses the 68HC70 as follows.
By configuring 5 as a peripheral device, it interfaces with the CPU 30. That is, (1) PA0
~ PA7 is connected to D0 to D7 of the DATA bus,
(2) PB7, PB1, and PB2 are GPIO1 of the ADDRESS bus and the CONTROL bus (A as described later).
/ V controller / 32-byte address range decoded by auxiliary processor 32), A1 and A2, respectively, and (3) PB3, PB4, and PB5 are CONTR.
It is connected to ADS, READY, and W / R of the OL bus, respectively. The I / O coprocessor 36 has four 16-bit addresses (hereinafter, AS0, AS2,
AS4, AS6)) to be decoded by the A / V controller / coprocessor.

The program in the 68HC705 interfaces with the CPU 30 as follows. 68HC7
05 is directly connected to the processor bus and is designed to operate as an input / output port to the CPU 30.
A pair of internal latches store data to and from each processor until the remaining processors are ready to receive. The status bits for each processor are
Indicates the state of the data latch. Each processor can check its status bit to determine if the previous data was read and if it is waiting for new data to be read.

I / O coprocessor 36 is, among other things,
(1) 50 ms timer, (2) serial controller link for receiving communication packets from input device, (3) cartridge 14 in each cartridge connector
There are various functions such as a cartridge / expansion sense for discriminating the presence or absence of an expansion device or a CD drive in the expansion connector, (4) system reset, (5) I ² C non-volatile RAM (NVRAM) interface. To be realized. The I / O coprocessor 36 also implements an optional DSA compact disc control serial line to enable communication with an optional CD drive.

The 50ms timer is implemented by configuring the watchdog timer of the 68HC705 I / O coprocessor 36 to time out at 50 millisecond intervals. Each time the watchdog timer expires, the I / O coprocessor 36 uses the analog interrupt 0 (AI0) of the A / V controller / coprocessor 32 to interrupt the CPU 30 (A / V controller / The auxillary processor interrupts the CPU via the IRQ line in response to the I / O auxillary processor pulling AI0 low). The CPU enables and disables the 50 ms timer by writing either byte 0F0H or byte 00H to I / O port AS0, respectively. This timer is enabled by default.

During the CPU interrupt acknowledge cycle, A /
The VController / Auxiliary Processor asserts the address of the interrupt handling routine. By the interrupt processing routine,
The CPU 30 reads one byte or a plurality of bytes from the 16-bit input / output port AS0 corresponding to the input / output auxiliary processor. During each read of the I / O port AS0, the A / V controller / coprocessor 32 selects the I / O processor 36, which enables data transfer between the CPU 30 and the I / O coprocessor 36.

The input / output auxiliary processor 36 always prepares one byte to be transferred to the CPU in response to the 50 ms interrupt. The lower 4 bits of this byte contain the number of 50 ms time outs since the last interrupt acknowledge cycle, and the upper 4 bits of this byte contain the number of I / O device messages to be transferred to the CPU. 50 ms
If the timer is disabled, the lower 4 bits of this byte will be zero. If more than 16 messages are received, 15 will be sent in the upper 4 bits and the remaining messages will be sent on the next transfer. Depending on the contents of this first byte, the CPU will send the following bytes to the I / O coprocessor 3
6 can be read, and for the most part they will be packets of data from the input device. Generally, the input device will send messages only when their respective states change, thereby keeping the message transmission frequency very low.

Input device 18 and all other input devices are connected to input / output coprocessor 36 via serial data link 22. An individual input device (eg, input device 18) serializes the movement of the controller.
Convert to a format suitable for transmission by link 22. The input device 18 sends data packets to the system unit 12 via the serial data link 22. As described below, the structure of the data packet depends on the type of input device. Coordinate type devices (mouse, analog joystick, touchpad, etc.)
Has a different data packet structure than switch closed type devices (keyboards, digital joysticks, switch pads, etc.).

The serial controller link 22 is composed of three lines: a data receiving line, a VCC (+ 5VDC) line, and a ground line. 68HC705 is the 68HC705
The PD0 / RDI pin of is used to implement the data receive line of the controller serial link. This pin is designed to be used as an interface to serial devices using the well known asynchronous format. Serial transmission uses the format of 4800 bits per second, no parity, 8 data bits, 1 stop bit. In an alternative embodiment, a clocked synchronous format could be used. The serial controller link 22 is connected to an external device known in the art by a 6 wire mini DIN plug connector (not shown). The input devices are daisy chained, thus physically a single device is connected to the data processing unit 12. For example, if a so-called mouse pointing device is added to the system 10, the mouse is connected to the input device 18 and the input device 18 is connected to the processing unit 12.

The cartridge sense and expansion sense are for determining the presence or absence of the cartridge 14 in the respective cartridge connector or expansion connector, and have the I / O coprocessor 36 poll the pins of the cartridge connector 28. Is realized by This pin is pulled to a logic one by an appropriate pull-up resistor (not shown) on the system planar, and when the cartridge 14 is properly connected, the cartridge pulls the pin to a logic zero.
Therefore, a 1 in each cartridge sense means that there is no cartridge 14, and a 0 means that there is a cartridge 14. Similarly, an expansion sense of 1 means that there is no expansion device such as an optional CD drive, and 0 means that there is an expansion device.

Reset is achieved by giving the I / O coprocessor 36 control over the reset signal of the A / V controller / coprocessor 32, and then the A / V coprocessor 36.
V controller / coprocessor 32 controls the reset signal of CPU 30. CPU 30 may instruct I / O coprocessor 36 to reset system 10 by causing I / O coprocessor 36 to reset the A / V controller / coprocessor.
The V Controller / Auxiliary Processor resets the CPU 30. The CPU causes the I / O controller to generate a system reset by writing byte 0FFH to I / O port AS0. Further, the input / output auxiliary processor 36
Monitors an optional reset switch (not shown) for the system and resets the system at power up and when it detects switch closure.

Finally, the I / O coprocessor is 512
To read, write, and test the contents of a byte of non-volatile system RAM, an I ² C non-volatile RAM (NVR)
AM) is realized. NVRAM (not shown) is Philip
s Semiconductor PCF8594, which is in circuit communication with the I / O coprocessor through the I ² C interface. Multiple PCF8594s can be cascaded to provide more NVRAM capacity. A 3-byte sequence is used to access NVRAM. All three bytes are accessed via the input / output port AS0. The first byte written by the CPU to the I / O coprocessor indicates whether the transfer is a read or a write and provides the I / O coprocessor with a segment address. The lower 4 bits of this byte indicate the type of transfer, 01H is NVRAM
02H indicates a read from NVRAM and 02H indicates a read from NVRAM. The upper 4 bits of this byte are 2 of NVRAM
It is a 4-bit segment number corresponding to a 56-byte segment. In 512 bytes of NVRAM, only the bottom two segments (0 and 1) are used. The next byte will be the same for both reads and writes, and the next byte will be written by the CPU and will be the address of the byte accessed in that segment. The last byte becomes a data byte that is written to or read from the I / O coprocessor by the CPU and read from or written to NVRAM.

In alternative embodiments, the I / O coprocessor can be implemented in other ways. For example, a tri-state readable shift register should be able to properly receive information from serial data link 22. In that case, the CPU 30 periodically reads the shift register to access the data packet from the input device.

The first decoding chip (not shown) is
CPU 30, A / V control device / auxiliary processor 32, 2
In electrical circuit communication with one cartridge connector 28 (the other not shown). The first decode chip accepts the two address lines at the top of the SYSTEM bus 31 as inputs and puts the 16 megabyte address space of the 80376 CPU 30 into four 4 megabyte areas represented by the three chip select lines. Decrypt. Of these chip selection lines, two are cartridge connectors 28
One is for the A / V controller / auxiliary processor 32 (the other is not shown). The upper 4 bytes and the lower 4 bytes are decoded into an A / V controller / auxiliary processor chip select and the remaining two 4 megabyte areas are decoded into two cartridge connector chip selects.

The second decoder chip (not shown) is
Used to implement chip selection for expansion connector 39. The second decode chip is the SYSTEM bus 3
4 in circuit communication with the A / V controller / auxiliary processor 32 and expansion connector 39. The second decode chip allows the A / V controller / coprocessor 32
128 of system ROM starting from F20000H
K blocks can be decoded. F40000H
The range ~ FFFFFFH is decoded by the second decoding chip for use by expansion connector 39.
The ROM of this block, which is decoded by the second decoding chip, is transferred to the system 10 via the expansion connector 39.
Used to add ROM to.

The data processing unit 12 also includes a pair of cartridge connectors (one shown at 28 and the other not shown) for bringing the cartridge 14 into circuit communication with the CPU 30 and other system components. . The cartridge 14 is connected to a connector 28 of the data processing unit 12 via a gold-plated 62-pin (31 lines of conductive wire in two rows) edge card connector 26. The processor unit 12 is an edge
Two cartridge connectors 28 are provided to receive the edge card connections of card connector 26. The cartridge 14 includes a gold-plated card edge connection to fit the conductors of the connector 28 to allow the cartridge 14 to be pluggably connected to the processor unit 12. The following signals are sent to the external device via the cartridge connector 28 (the other one not shown). That is, the SYSTEM bus 31 signal, cartridge sense line, power supply, ground, analog interrupt 1 or 2 (each cartridge has one unique interrupt), and GPIO 2 or 3
(Each cartridge has its own chip selection) and lock lines (80376 and 80386).
(Typical signal on the SX SYSTEM bus 31)
And a cartridge selection generated by the first decoding chip. In an alternative embodiment, the signals necessary to connect to an optional CD drive can also be connected to an external device via cartridge connector 28.

In addition, the processor unit 12 has a single 112-pin (56 pins in two rows) edge card expansion connector 39. This expansion connector 39 allows the device to add more memory to the system memory 33 and various other features. The device connected to the expansion connector 39 has a gold-plated card edge to fit the expansion connector, allowing the device to be plugged into the processor unit 12. The following signals are expansion connector 3
9 to the external device. That is, SYSTE
M bus signal, expansion connector 39 sense line, power supply,
Ground, CAS and RAS lines, second decoding
An expansion connector 39 selection generated by the chip. In an alternative embodiment, the signals needed to connect to an optional CD drive can also be connected to external devices via expansion connector 39.

The program cartridge 14 includes a program ROM 40 and a decoder 42. In an alternative embodiment, the decoder 42 may be designed within the processing unit 12. Program ROM 40 contains code suitable for execution on CPU 30 in a read-only memory format. In alternative embodiments, other memory types, such as battery backed RAM, may be used as the storage device in cartridge 14. The program ROM 40 is in circuit communication with the CPU 30, as shown in FIG.

The address decoder 42 in the cartridge 14 programs the entire width of the ADDRESS bus into a program RO.
Decode to memory range suitable for M40 and chip select signal 44 required by ROM 40 as is well known in the art.
Generate Address decoder 42 is implemented in a 16V8 programmable array logic circuit (PAL),
It is well known in the art and is manufactured by numerous manufacturers such as AMD Corp. If the decoder 42 is designed in the processing unit 12, the selection 44
Are electrically connected to the ROM 40 by the connector 26.

Referring now to FIG. 2, the additional circuit 3 of FIG.
8 is shown connected to the A / V controller / auxiliary processor 32. The additional circuit 38 is a video digital analog converter (video DAC) 50, NTSC.
/ PAL ("PAL" means the well-known European television signal standard) encoder 52, audio digital
Analog converter / analog / digital converter / compressor / decompressor (ADC / DAC / CODEC) 54, R
It includes four devices, the F modulator 56. Each device is connected as shown in the accompanying drawings.

The electronics of the audio / video controller / auxiliary processor (A / V controller / auxiliary processor) 32 is called an ASIC (application specific integrated circuit) 1.
Approximately housed in one large custom logic chip. An A / V controller / coprocessor 32 compatible with the description herein is available from MSU Ltd. (270 Upper 4th Street, Wit
an Gate West, Central Milton Keynes, MK9 1DP Engla
nd). The A / V controller / auxiliary processor 32 has a processor interface 60.
A processor cache 62, a memory interface / refresh 64, a video controller 66,
It includes an interrupt controller 68, a video blitter 70, an optional CD block decoder, a digital signal processor (DSP) 74, and a DSP memory 76.
Processor interface 60, memory interface / refresh 64, and video controller 66
Collectively referred to as video / memory controller 67. The system memory 33, central processing unit 30, and other devices are external to the A / V controller / auxiliary processor 32.

The A / V controller / auxiliary processor 32
The SYSTEM bus 31 to the SYSTEM bus 34 are generated, so that the system memory 33 to the CPU 30 are generated.
Is separated. Therefore, the SYSTEM bus 34 electrically connects various devices to the system memory 33.
Memory refresh 64, video controller 66, optional CD block decoder (not shown), DSP 7
4, blitter 70, CPU 30 (by processor interface 60), 6 possible bus masters (highest to lowest priority) are SY
The STEM bus 34 is shared. SYSTEM Bus 3
Only four bus masters can control four at a time.
The arbitrator in the video / memory controller 67 controls the priority changes of the various devices and is in electrical communication with all the devices in the A / V controller / coprocessor 32 as described herein. ing. For example, CPU3
0 has the lowest priority of all bus masters until an interrupt occurs. Therefore, the arbitrator includes the CPU interface 60 and the interrupt controller 6.
8 are in circuit contact with both.

The cache 62 is not a cache in the sense of prefetching instructions for the CPU 30. Rather, the cache 62 can be used by the CPU 30 for variables, stacks, or program code to speed up program execution, F14000.
It is a static RAM of 512 × 16 bits located in H to F143FFH.

A video / memory controller 67 (processor interface 60, memory interface / refresh 64, video controller 66) controls the SYSTEM bus 34 and, as is well known in the art, a SYSST.
It provides memory timing signals (eg, CAS, RAS, writable, etc.) to memory devices connected to the EM bus 34. This suspends the operation of the bus master in the video line for a short period of time to fetch the video display data and refresh the dynamic RAM (DRAM). It also controls the interface with the CPU 30.

The video controller 66 has a flexible video timing generator that can be programmed to meet various TV standards, up to 640 x 480V.
Monitor up to GA standard. The correct video format is horizontal period in the A / V controller / auxiliary processor, horizontal sync, end of horizontal blanking, start of horizontal blanking, start of horizontal display, end of horizontal display, start of horizontal fetch, end of horizontal fetch Controlled by setting various registers: horizontal vertical sync, vertical period, vertical sync, vertical blank erase end, vertical blank erase start, vertical blank start, vertical display start, vertical display end, video interrupt, light pen register. It The video controller 66 is provided with three color resolutions: 4 bits per pixel, 8 bits per pixel, and 16 bits per pixel. The screen memory map is not bound by the video display width, but is defined independently.

The video / memory controller 67 is 8037
6 Decode the 16 megabyte address range of CPU 30 into the following memory map. That is, 1MB system RAM (000000H to 0FFFFFH),
4MB for the first cartridge ROM (400000H
~ 7FFFFFH), 4 for the second cartridge ROM
MB (800000H to BFFFFFH), 64KB internal memory (F10000H to F1FFFFH) for audio / video controller / auxiliary processor, 128K
B block system ROM (FE0000H to FFF)
FFFH). The 64 kilobytes of internal memory includes palette RAM, blitter registers, DSP registers and memory. The palette address range is as described above. The blitter register is F10400H
To F107FFH. DSP memory is F10
It ranges from 800H to F18000H.

If an optional CD drive is added to the system, another 1 MB of system RAM (100000
H ~ 1FFFFFH) and 128 KB for CD drive
The area (FC0000H to FDFFFFH) is added to the memory map.

The interrupt controller 68 has a video interrupt (highest priority), an analog interrupt 0 (AI0), an analog interrupt 1 (AI1), an analog interrupt 2 (AI2), and a C interrupt.
Interfaces the D block decoder interrupt and DSP interrupt (lowest priority) to the CPU 30 in six ways. The interrupt controller automatically clears the interrupt when the CPU 30 executes the interrupt acknowledge cycle. One mask bit is prepared for each interrupt.

The blitter 70 is a graphic processor for high-speed screen updating and animation, and operates as a hardware graphic subroutine for the CPU 30 or the DSP 74. It executes commands written to memory by CPU 30 and DSP 74. Also, by reading a new command set from system memory 33, arbitrarily long sequences of graphic operations can be performed. The blitter 70 becomes a bus master by the operation of the blitter program, and therefore
It may have exclusive control of the SYSTEM bus 34 for a considerable period of time. However, the priority for the CPU 30 is not absolute, and when an interrupt occurs,
In some cases, it may be required to give up the SYSTEM bus 34 to the CPU 30. Although CPU 30 is the lowest priority bus master at the system level, it has complete control over other hardware, and is therefore SYSTE.
The use of M-bus 34 is completely under the control of the CPU 30 program.

The blitter 70 comprises a versatile comparator for enabling sophisticated blitting operations and a logic function unit (LFU) for producing output data. The logic functional unit may combine the contents of the data registers in some useful way to produce output data, the comparator performing a given comparison on the data,
You can prohibit write operations and optionally stop blitter operations.

The logic function unit produces output data,
This data is written to the destination in system memory 33. This unit is capable of performing a logical combination of source and destination register pixels. The "source data pixel" can be selected from either the source data register or the data pattern data register. The LFU is a four Boolean minterm (A & B, of two sets of input data from the data register.

(Equation 1) Is hereinafter referred to as A bar. & B, A &

(Equation 2) Is hereinafter referred to as B bar. , A bar & B bar) to generate a logical OR of the two selected minimum terms. This allows any logical combination of the input data, so that there are 16 possible function possibilities.

The comparator can perform various comparisons on the data in the source, destination, and pattern data registers. If the comparison condition is met, the comparator produces an inhibit signal. This inhibit signal is used to inhibit the write operation as well as optionally stop the blit operation. The comparator can also be used for collision detection and system memory 33 search operations, and as an aid to character painting, to provide a pixel plane effect to provide a transparent color.

The DSP 74 is a simple and very fast processor for speech synthesis, with a maximum of 33 million instructions / second (M
IPS). It can access the SYSTEM bus 34 via a DSP DMA controller (not shown), which allows bytes or words to be read from or written to the system memory 33. Such transfers are done in short bursts and
It is under the control of the P program. The DSP 74 actually executes the program and has its own private high speed memory 76.
To store data.

The DSP74 audio coprocessor is
It is a general-purpose arithmetic auxiliary processor with sufficient capability to realize a high-performance music synthesizer. A synchronous serial output is provided to produce a stereo audio signal with 16-bit precision, providing the audio quality normally associated with compact disc technology. DSP74 is CPU3 of host
It is microprogrammable from scratch and its instruction set is flexible enough to allow the user to program the device to implement a wide variety of functions that are quite different from those of the "music synthesizer". As such application fields, algorithmic voice generation, audio analysis by a fast Fourier transform technique, and three-dimensional figure rotation can be considered. The DSP 74 uses a Harvard architecture (separate program and data buses) for maximum data throughput. Further, the DSP 74 is an arithmetic logic unit (A
LU), which features hardware 16-bit by 16-bit hardware multiplication / accumulation as well as addition, subtraction, and logical functions. Also, 1 per moment
There is also a separate serial division unit that produces one quotient bit.

The ALU in DSP 74 is a 16-bit arithmetic logic unit with the same functionality as the Texas Instruments 74181 well known in the art. General arithmetic operations are coded as instructions, but uncommon instructions are
This can be done by setting up the LU mode bits directly.

The DSP 74 has a DSP memory 76 associated with it. DSP memory 76 includes program RAM, data RAM, register / constant table, and sine ROM (all not shown). In general,
The DSP memory 76 is accessible in both the DSP internal address space as well as the system memory 33 address space. The DSP program RAM is 512 18-bit words. These positions are CPU30
It can only be written by and is program read-only as far as the DSP 74 is concerned. Program RAM
Does not appear in the DSP internal address space. The program RAM is inaccessible to the host when the DSP 74 is executing, but is accessible when the DSP is idle.

The DSP 74 also has a serial audio digital-to-analog converter (DAC) interface. D by serial DAC interface
SP74 is a synchronous serial (I ² S or similar)
It allows both driving of the DAC and data input from a synchronous serial data source such as a CD drive.

The video controller 66 of the A / V controller / auxiliary processor 32 connects to an external video DAC 50 which, as is well known in the art, has 18 bits of pixel information 78 (red) from the video controller 66. , 6 bits each for green and blue) are converted into RGB signals 80. Each color channel (R80
a, G80b, B80c) are R2 as shown in FIG.
It is realized by an R resistor tree and a 2N2222 transistor. The various devices of FIG. 3 are in circuit communication as shown. In addition, each of the resistors 86a to 86j in FIG. 3 is a 0.25 watt resistor having a value shown within an allowable range of 5%. The transistor 88 is 2N2222.

Referring again to FIG. 2, the RGB signal 8
0 is NTSC by NTSC / PAL encoder 52
It is converted into a composite video signal 90. The NTSC / PAL encoder 52 is an A / V controller / auxiliary processor 32.
Chroma Clock 92, HSYNC, VSYNC signals 94 generated by the video controller 66 of FIG.
b and blue 80c video outputs are accepted and well-known NT
It produces a composite video signal 90 in SC or baseband video format. In an alternative embodiment, the well known P
AL (European Television Signal Standard) format can be generated. The composite video signal 90 is connected to an external device with a single female RCA type phone jack (not shown), as is well known in the art. In the preferred embodiment, NTSC / PAL encoder 52 is a Sony CXA1145. In an alternative embodiment, the Motorola MC1377 can also be used.

Audio ADC / DAC / CODEC5
4 is linked to the DSP 74 by a serial link 96 compatible with the well known Phillips I ² S protocol. The ADC / DAC / CODEC 54 performs conversion from analog data to digital data and vice versa, and performs compression and decompression of digital data. The ADC / DAC / CODEC 54 interfaces external stereo analog data 97a-97b from any microphone to the A / V controller / auxiliary processor 32. The audio inputs 97a-97b are
Connects to external devices with standard stereo 1/4 "connectors. Also audio ADC / DAC / CODE
C54 is a left / right audio line output signal 98a-98b
To interface digital data from the A / V controller / coprocessor to external devices. These signals 98a-98b are connected to an external device, such as any speaker (not shown) with two female RCA phone jacks, as is known in the art. As described above, the audio line signals 98a-9
8b is also added to the RF video signal 22.

In the preferred embodiment, ADC / DAC / C
ODEC54 is CS42 made by Crystal Semiconductor
Sixteen. This part contains the microphone input with programmable gain as well as the output by the programmable attenuator. Both gain and attenuation are DSP7
Programmatically controlled by 4.

In an alternative embodiment, ADC / DAC / COD
Philips TDA1311 instead of EC54
A DAC can be used. When using this chip, the ADC function and the CODEC function cannot be used.

The RF modulator 56 outputs the composite video signal 90 and audio A from the NTSC / PAL encoder 52.
The left and right audio line output signals 98a and 98b from the DC / DAC / CODEC 54 are integrated on the carrier frequency to produce an RF video signal 22 suitable for direct input to the TV 16. Different PAL (European television signal standard)
Different RF modulators and crystals must be used to generate the formats and NTSC formats. The RF video signal 22 is connected to an external device with a single female type F coaxial connector, as is well known in the art.

Referring now to FIGS. 4-9, these figures show an embodiment of the input device 18 of the present invention. As shown in FIGS. 4 to 6, the input device 18 includes the rising member 2
00 and a rigid support member 206. Standing member 20
0 includes a left-right symmetrical body 202 and a cross member 208. The cross member includes a pair of handle members 210 and 212 attached at opposite ends thereof. The input device 18 also includes an annular sealing device 204. Rigid support member 206 provides surface 2 sufficient for human seating purposes.
Including 16 Surface 216 may be flat (as shown) or may include indentations or other suitable enhancements for a comfortable seating of an individual. The rising member 200 has a predetermined size and is based on the "sitting height" of a young child. This "sitting height" is measured from the surface of the table to the shoulders or chest when the child presses their knees against the edge of the table and stretches their backs so that their head lies in the horizontal plane connecting their eyes and ears. It can be defined as a measure of vertical distance (measured along the back). Generally, the rising member 200 is sized according to this "sitting height" of children of a specific age group.

Further, in FIG. 4, a plurality of directional arrows 209A are provided.
~ 209E is also shown. Directional arrows 209A-209
D indicates the degree of front, rear, left, and right turning motions. Directional arrow 209E indicates the degree of rotational movement, including clockwise and counterclockwise.

Referring now specifically to FIG. 6, there is shown a cross-sectional view of the input device 18 of FIGS. 4 and 5.
Rigid support member 206 is generally made of a shell-like structure with a hollow interior space 215. The hollow space 215 is
It is used to house the electronics (not shown) of the input device 18 and the rising connection device 220.

The surface 216 of the rigid support member 206 has a size and shape sufficient to accommodate human use for seating purposes. The surface 216 has in its center an aperture of sufficient size to accommodate the symmetric body 202 of the rising member 200 and an additional space for accommodating the pivoting movement of the rising member 200. The size of the aperture is the size of the symmetrical body 202 and the rising member 2
It depends on the designer's preference, such as the desired degree of swivel motion of 00. The rigid support member 206 includes an arcuate portion 205,
And a directional wave portion 207. The directional wave portion 207 provides a front direction indication so that the user can recognize his / her own orientation on the rigid support member 206. The rigid support member 206 of the illustrated embodiment is constructed of injection molded plastic that possesses fracture properties and impact resistance.

As already mentioned, the riser member 200 includes a symmetrical body 202. Symmetric body 202
Is a tubular structure with a hollow interior space 203 and an interior surface 238. The hollow internal space 203 has an elastic device 218.
Is housed. Resilient device 218 resides within interior space 203 and is in physical communication with interior surface 238. The elastic device 218 serves to maintain the rising member 200 in position with respect to the rigid support member 206 when the rising member 200 is not subject to external forces. Also, the elastic device 2
18 also provides a force that can counteract any force acting on the riser member 200. The elastic device 218 is
It also provides a counter-rotating force when the rising member 200 is receiving a rotating force. The elastic device 218 of the illustrated embodiment places the rising member 20 in a default position perpendicular to the rigid support member 206.
It is a spring that maintains 0.

Still referring to FIG. 6, elastic device 218.
The rising member 200 is fixed to the rigid support base 206 via the rising connection device 220. The upright connection device 220 is of a characteristic that allows the elastic device 218 and the upright member 200 to pivot and rotate.
Such a connecting device is provided with a rigid support base 20 with a clearance sufficient to cope with a turning motion and a rotating motion.
By firmly fixing the elastic device 218 in 6,
Can be formed. Elastic device 218 of the illustrated embodiment
Is physically connected to the connecting device 220, which is permanently connected to the rigid support member 206. Another connecting device may include a spring loaded ball and socket assembly to return the elastic device 218 and the upstanding member 200 to their home positions. In short, the elastic device 218 and the rising member 200 can be pivotally attached to the rigid support member 206 by a number of well known methods.

The riser member 200 of the illustrated embodiment includes a cross member 208. The cross member 208 includes a shell-shaped left-right symmetrical body and is constructed of the same material as the rigid support member 206. The cross member 208 can be manufactured integrally with the body 202 or separately from the body 202. If manufactured separately from body 202, cross member 208 is then secured to symmetrical body 202 by connection joint 214.

An annular sealing device 204 is attached to the rising member 200 and the rigid support member 206. The annular sealing device 204 serves two main functions. That is, (1) the rising member 200 and the rigid support member 206
To seal the physical interface with and to prevent moisture, dirt and other harmful contaminants from entering the hollow space 215, and (2) additional elasticity to resist the operation of the rising member 200. It is to provide a device. The annular sealing device 204 is preferably constructed of a resilient material.

Next, referring to FIGS. 7 and 8, there are shown sectional views showing the internal structure of the rising member 200 of the input device 18 of the present invention. The rising member 200 is
A plurality of position sensors 222-236 are included along the inner wall 238. The position sensors 222 to 236 are preferably located in a part of the symmetric body 202 of the rising member 200 in the hollow space 215 of the rigid support member 206, but any suitable sensor position can be used in the symmetric body 202. You should know that Each position sensor includes a strain gauge sensor.

Strain gauge sensors are well known in the art and operate on the well known principle that the electrical resistance of a wire changes due to physical deformation of the wire. Therefore, under constant voltage conditions, a change in the resistance of the wire causes a quantitative change in the current passing through the wire. Such a quantitative change in resistance and, consequently, a quantitative change in current is
A change in position and, consequently, a change in movement. By measuring the increase or decrease in the current passing through the strain gauge, it is possible to determine the direction component of the displacement in addition to the displacement amount.

Still referring to FIGS. 7 and 8, the position sensors 222-236 are placed in a "zig-zag" arrangement on the inner wall 238 with equal displacement angles. In the illustrated embodiment, there are eight position sensors, so the displacement angle between each position sensor is 45 degrees. Although eight position sensors are used in the illustrated embodiment, the rising member 2
More or less position sensors may be used, depending on the precision desired by the designer in measuring the 00 displacement or motion. The position sensors 222 to 23 described above
The 6 "zig-zag" physical configuration provides the input device with high position and motion resolution. Therefore, the entire range of the turning motion can be sensed, and further, the rotation motion and the direction can be sensed.

In an alternative design, the position sensors 222-236 may be located in the cross member 208 in substantially the same configuration to sense a range of motion when positioned within the symmetric body 202. Further, the designer may choose to place multiple position sensors in the handle members 210 and 212 to sense the same range of motion. In summary, the high accuracy and flexibility of the strain gauge sensor also gives the designer great flexibility in choosing the position of the position sensor.

Referring now to FIGS. 10-13, which are perspective views of alternative embodiments of the input device 18. FIG. 10 shows an alternative embodiment of the input device 18 with a simple straight cross member 240 without a handle member. FIG. 11 shows an alternative embodiment of the input device 18 with a steering wheel or disc-shaped member 242. FIG. 12 illustrates an alternative embodiment of the input device 18 including the synclinal cross member 244.
The syncline cross member 244 may be, for example, a "U" shape,
It can take on a variety of shapes and angles, such as the "V" shape (as shown) and variations thereof. FIG. 13 illustrates an alternative embodiment of the input device 18 that includes a tactile sphere 246 attached to the rising member 200. Haptic sphere 246 includes a tactile or touch sensor for determining when the surface of the sphere contacts another body. The tactile sensor can take the form of a capacitance sensor or an inductive sensor, both of which are well known.

Referring now to FIG. 14, there is shown a block diagram of the circuitry within the input device 18. The input device 18 includes position sensors 222 to 236, a direction determining circuit 302, and an interface circuit 300, all of which are connected in electrical circuit connection as shown in FIG. The direction determination circuit 206 includes position sensors 222 to 236.
And in circuit communication with the interface circuit 210.
As mentioned above, the position sensors 222-236 include strain gauge sensors. The direction determining circuit includes position sensors 222-23.
A message is generated based on the quantitative change in the current flowing through 6. The direction determining circuit includes position sensors 222 to 236.
It reads the quantitative change in the current through it and outputs a message to the interface circuit 300 indicating the digital type directional data. Therefore, the data messages sent to the interface circuit 300 and the I / O processor 36 are digital type (ie, on / off).
Similar to a data message from a joystick.

The interface circuit 210 includes a serial interface with the data processing unit 12 (via the serial data line 22) and other input devices, if any.
The data line extension 23 is in circuit communication. The interface circuit 210 accepts the direction data message generated by the direction determination circuit 206 and transmits such information to the data processing unit 12 via the serial data line 22.

All input devices are daisy chained to the processing unit 12. Therefore, the interface circuit sends packets from other input devices to the CPU 3
Must be passed to 0. As will be detailed below, each input device connected to the processing unit 12 has a unique device number. The device closest to the processing unit 12 is given the device number 0, and the farther the device is from the processing unit 12, the higher the device number. However, the input device does not know the device number of itself or other devices. Therefore, each device needs to add 1 to the device number of data packets passed from other input devices of the same type. Input devices in the chain with device numbers greater than 15 are ignored.

For example, assume that three input devices α, β, γ of the same type are connected to the processing unit 12 as follows. That is, it is assumed that α is connected to the processing unit 12, β is connected to α, and γ is connected to β. Therefore, α has the device number 0, β has the device number 1, and γ has the device number 2. No other device knows itself or any other device number. Each device sends a dedicated data packet with device number 0.

When α passes the data packet to processing unit 12, the default device number 0 is correct because α is closest to processing unit 12. However, β and γ also transmit the data packet with the device number 0.
To remedy such a situation, each device adds 1 to the device number of the passed packet. Therefore,
If β passes the data packet from γ to α, β will add 1 to the device number, thereby giving the packet from γ the device number 1. Similarly, if α passes a data packet with γ to processing unit 12, α will add 1 to the device number, thereby giving the packet from γ the correct device number 2. Therefore, each device in the chain will add 1 to the device number of each data packet passed from the same type of device to the next device.

Therefore, in addition to passing the data packet received from another input device (if any), the interface circuit 210 causes the serial data line extension 2 to
Data from the same type of device received via
Add 1 to the device number of the packet. The interface circuit 210 passes to the data processing unit 12 the data packet with the device number after the correction and the device number before the correction.

System 1 with input device 18 of the present invention
Using 0 is very simple. The input device sends the data packet to the data processing unit 12 via the serial link 22. As mentioned above, the input device interfaces to the CPU 30 via the I / O coprocessor 36. Each input device is daisy chained to the next input device. The I / O coprocessor 36 receives the data packet and stores it in a re-first in first out (FIFO) manner.

At every "moment" of 50 msec, the input / output auxiliary processor 36 interrupts the CPU 30.
In response, the CPU accesses a single byte at I / O port AS0 of auxillary processor 36, and as described above, the number of instants since the last access by the CPU,
Determine the number of device messages to transfer. The 10 types of device messages are shown in the table below.

[0085]

[Table 1]

As shown in the table, this message structure has a structure of various lengths and closely related to the input device to which it corresponds. The device message in the table is
It is the same as the data sent to the I / O coprocessor from the individual I / O devices as the data sent to the CPU by the I / O coprocessor. Each message from the I / O device to the I / O coprocessor has the structure described above plus a checksum to ensure that uncorrupted data is sent from the input device 18 to the processor unit 12. . This checksum is
A standard modulo 256 checksum such that the value required to bring the sum of all bytes to zero (ignoring carry in the sum) is the checksum value. The I / O coprocessor removes this checksum before sending the data to the CPU. Therefore, the byte stream read by the CPU will be nearly identical to the byte stream received by the I / O coprocessor. However, exceptionally, (1) the first byte read by the CPU is a special byte containing the number of instants and the number of I / O device messages, and (2) the checksum is missing.

PS / 2 mouse and keyboard devices are supported as device type 0. The keyboard has chain number 0 and the mouse has chain number 1. These devices are supported by the I / O coprocessor using the existing PS / 2 protocol over the serial data link 22.

This device type 1 is for a device having a plurality of buttons. Up to 255 bytes (8 buttons per byte) using this message type
Or 2040 buttons can be entered into the system. Open buttons are sent as logic 0, while closed buttons are sent as logic 1. This is a variable length message.

The overall motion detection controller 18 of the present invention is supported as device type 2 because it produces a data message that is representative of a data message produced by a digital type joystick. When multiple overall motion detection controllers are connected to the system, each controller has a unique chain number. The generated message is a 1-byte fixed length message. The individual bits of the message type for type 2 are: upper switch (MSB), lower switch, left switch, right switch, switch # 1, switch # 2,
The switches # 3 and # 4 (LSB) are shown.

Coordinate devices such as mice and trackballs are reported as device type 3. The first byte following the ID is for reporting the button information for that device. Up to 8 buttons can be reported.
The next byte is the Delta X value, followed by the Delta Y value. The Delta X and Delta Y values are based on the last reported device position. The application program must convert this value to absolute coordinates if necessary. The maximum movement is 255. Actual movement is 2
If more than 55, then two or more messages are sent. This is a fixed length message.

Touchpad is supported as device type 4. Other devices of this device type include analog joysticks. The first byte following the ID is used to report button information. The next byte is used to report the absolute X position. Absolutely Y
The position follows next. The absolute X value and the absolute Y value are each 1 byte, and are limited to the range of 0 to 255. This is a fixed length message.

Touchpad overlays are reported as device type 5. The touchpad overlay is sensed using a 6-bit sensor 124 within the touchpad. When the touchpad senses the overlay change, a message is generated. All overlay code is application dependent, so the application program must be aware of the code for each overlay. This message is
It is a fixed length message.

Action messages can be generated differently by multiple device types, but a common set of predefined device-independent functions that are similarly used and interpreted by system and application programs. Used to define Action messages are reported as device type 6 using variable length messages. In this particular embodiment, ST
ART (start an activity or process), PAUSE
3 (pause activity or process), SELECT (select one of multiple events or actions)
One device independent function is defined and associated with the lower 3 bits of this byte. These bits are set to report these capabilities. All other bits are reserved for future use and are reported as 0 to the CPU.

The system passthrough message type is used to handle device types that do not apply to the predefined device types. Use message type 14. This is a variable length message. Data definitions are device-dependent and application-specific. Each application must translate this type of message into the required functionality.

The first message from each device is device type 15. It is used to inform the system that a device will send an input message. This message also defines future device types used to report the input. This is a variable length message.

At system power up and 50 ms
At every interval, the I / O coprocessor scans the cartridge and extended sense lines to determine their configuration, alert the system, and sends a configuration byte to the CPU. This is the first byte that the CPU receives from the I / O coprocessor at power up. Since the I / O coprocessor only generates a module configuration interrupt when a change is sensed, a system reset occurs when the cartridge status changes, causing the I / O coprocessor to send another configuration byte to the CPU. It will be. The relevant bit set in the byte sent is set to indicate the presence of the related item. That is, bit 0 corresponds to cartridge 1, bit 1 corresponds to cartridge 2, bit 2
Corresponds to the optional CD drive. The remaining bits are set to 0.

Further, the CPU writes the information to the input / output auxiliary processor 36 to make the serial link 2
Data can be transmitted to the input / output device via the terminal 2. Data bytes are written to the I / O port AS0 with a 03H byte preceding each byte. The I / O coprocessor writes these bytes to the I / O device. This function is used, for example, to send data to a printer (not shown) or the like.

The method of providing an interface to the input / output device 18 of the present invention is also simple. System BIOS to CPU
An interrupt handler running on 30 receives data from the input device via the I / O coprocessor 36. The interrupt handler simply puts in memory 33 what was transmitted from I / O coprocessor 36. CPU
The application program executed on 30 is
Operating periodically by software interrupt
Poll the system BIOS to determine if input has been received. If received, the input is
The application program is contacted by the operating system in response to the software interrupt.

Referring now to FIGS. 7-9 and 14, during operation, an individual sits on surface 216 and cross member 2
Should grip either 08 or handle members 210 and 212. Movement of large parts of the individual's body (e.g., torso) or multiple parts of the body (e.g., arms or shoulders) causes displacement of the rising member 200 in position. The displacement of this position is detected by the position sensors 222-236.
Should be sensed by. Direction determining circuit 302
Converts the analog signals generated by the position sensors 222-236 into direction type data messages,
The data message is transmitted by the interface circuit 300 to the computer system 12 for interpretation by a running application.

While the invention has been illustrated and described in considerable detail by the description of embodiments of the invention, it is not intended by the applicant to limit or limit the scope of the claims to such details. Is not the intention of. Other advantages and modifications will be readily apparent to those skilled in the art. For example, the various cross members 208 and 240-244 and the tactile sphere 246 may be of an accessory-like nature to be removable from the rising member 200, or instead of a strain gauge sensor for sensing motion, an opto-mechanical sensor. Electronic or digital switches can also be used. As such, the invention in its broader aspects is not limited to the specific details, exemplary apparatus and methods, and examples shown and described. Accordingly, departures may be made from such details without departing from the spirit or scope of applicant's general inventive concept.

As a summary, the following matters will be disclosed regarding the configuration of the present invention.

(1) (a) A rigid support member having a size sufficient to be used by a person for seating purposes, and (b) a vertical height and an internal space, the vertical height being an individual. A rising member close to the seat height of (c), (c) a connecting device for connecting the rising member to the rigid support member, and (d) a conversion device in physical communication with the rising member. A transducer for sensing the movement of the member and transmitting the movement of the rising member to the computer in the form of a typical electrical signal; and (e) an elasticity in physical communication with the interior space of the rising member. An input device, comprising: an elastic device for maintaining the rising member in a predetermined position with respect to the rigid support member when the rising member does not receive an external force. (2) The input device according to (1), wherein the rising member includes a left-right symmetrical body and a straight cross member. (3) The input device according to (1), wherein the rising member includes a bilaterally symmetrical main body and a syncline cross member. (4) The input device according to (2), wherein the rising member further includes a swivel connection device that is in physical communication with the straight cross member and the symmetrical body. (5) In the above (1), the rising member further includes a bilaterally symmetric body, and a tactile sphere physically in communication with the bilaterally symmetric body and in circuit communication with the conversion device. The input device described. (6) The input device according to (3), wherein the rising member further includes a swivel connection device that is in physical communication with the synclinal cross member and the left-right symmetrical body. (7) The input device according to (2), wherein the rising member further includes a handle member that is in physical communication with the straight cross member. (8) The input device according to (3), wherein the rising member further includes a handle member that is in physical communication with the synclinal cross member. (9) on a video display device in (a) a central processing unit (CPU), (b) a memory circuit in circuit communication with the CPU, and (c) in circuit communication with the CPU and memory. A video circuit for generating an electrical signal corresponding to the displayed visual image, and (d) the CP
A peripheral device interface circuit in circuit communication with U for interfacing signals from an external device to the CPU; and (e) a rigid support member having a size sufficient for use by a human for seating purposes. f) a rising member having a vertical height and an internal space, the vertical height being close to an individual sitting height; (g) a connecting device for connecting the rising member to the rigid support member; ) A conversion device in physical communication with the rising member for sensing the movement of the rising member and transmitting the movement of the rising member to a computer in the form of a typical electrical signal; (i) the rising member. In physical communication with the interior space of the member,
A computer system comprising: an elastic device for maintaining the rising member in a predetermined position with respect to the rigid support member when the rising member is not subjected to an external force. (10) The computer system according to (9), wherein the rising member includes a left-right symmetrical body and a straight cross member. (11) The computer system according to (9), wherein the rising member includes a bilaterally symmetrical main body and a syncline cross member. (12) The rising member further comprises a swivel connecting device that is in physical communication with the straight cross member and the left-right symmetrical body.
A computer system according to claim 1. (13) In the above (9), the rising member further includes a bilaterally symmetric body and a tactile sphere physically in communication with the bilaterally symmetric body and in circuit communication with the conversion device. The computer system described. (14) The computer system according to (11), wherein the rising member further includes a swivel connection device that is in physical communication with the synclinal cross member and the bilaterally symmetrical body. (15) The computer according to (10) above, wherein the rising member further includes a handle member that is in physical communication with the straight cross member.
system. (16) The computer system according to (11) above, wherein the rising member further includes a handle member that is in physical communication with the synclinal cross member. (17) (a) A rigid support member having a curved outer housing having a size sufficient to be used by a person for seating, (b) a symmetric body portion, a vertical height, and an internal space. And (c) a connecting device for connecting the rising member to the rigid support member, and (d) a physical member with the rising member. A converter in communication for sensing the motion of the rising member and transmitting the rising motion to a computer in the form of a typical electrical signal;
(E) an elastic device that is in physical communication with the rising member and that maintains the rising member in a predetermined position with respect to the rigid support member when the rising member does not receive an external force. An input device comprising: (18) The rising member includes a left-right symmetrical body and a straight cross member, (17)
An input device according to claim 1. (19) The input device according to (17), wherein the rising member includes a bilaterally symmetrical body and a syncline cross member. (20) In the above (17), the rising member further includes a bilaterally symmetric body and a tactile sphere physically in communication with the bilaterally symmetric body and in circuit communication with the conversion device. The input device described.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall layout of the system of the present invention.

FIG. 2 is a block diagram showing the overall layout of the system of the present invention.

FIG. 3 is a schematic diagram showing details of a video digital-to-analog converter used in the system of the present invention.

FIG. 4 is a plan view of the input device of the present invention.

FIG. 5 is a side view of the input device according to the present invention.

FIG. 6 is a cross-sectional view taken from FIG. 4, showing the internal structure of the input device of the present invention.

FIG. 7 is a cross-sectional view taken from FIG. 5, showing the internal structure of the rising member of the input device of the present invention.

8 is a cross-sectional view taken from FIG. 7, showing the positions of a plurality of position sensors of the input device of the present invention.

FIG. 9 is a perspective view of the illustrated embodiment of the input device of the present invention.

FIG. 10 is a perspective view of an alternative embodiment of the input device of the present invention.

FIG. 11 is a perspective view of an alternative embodiment of the input device of the present invention.

FIG. 12 is a perspective view of an alternative embodiment of the input device of the present invention.

FIG. 13 is a perspective view of an alternative embodiment of the input device of the present invention.

FIG. 14 is a block diagram showing an electric circuit of the input device of the invention.

[Explanation of symbols]

10 Computer System 12 Data Processing Unit 14 Program Cartridge 16 Standard Television Receiver (TV) 18 Input Device 22 Serial Data Link 24 RF Video Line 26 Edge Card Connector 28 Cartridge Connector 30 Central Processing Unit ( CPU) 31 SYSTEM bus 32 audio / video (A / V) controller / auxiliary processor 33 system memory 34 SYSTEM bus 36 input / output auxiliary processor 38 additional circuit 39 expansion connector 40 ROM 42 decoder 200 rising member

 ─────────────────────────────────────────────────── —————————————————————————————————————————————————————————————————————————————————————————————————————————— upper | |・ Avenue 183 (72) Inventor James Alan Strosman 40509 Lexington, Kentucky Pheasant Run Road 3664

Claims (20)

[Claims] 1. A rigid support member having a size (a) sufficient for human seating purposes, and (b) having a vertical height and an internal space, the vertical height of an individual. A rising member close to a sitting height; (c) a connecting device for connecting the rising member to the rigid support member; and (d) a conversion device in physical communication with the rising member, the rising member comprising: A transducer for sensing the movement of the rising member and transmitting the movement of the rising member to the computer in the form of a typical electrical signal; (e) an elastic device in physical communication with the interior space of the rising member. An input device, comprising: an elastic device for maintaining the rising member at a predetermined position with respect to the rigid support member when the rising member does not receive an external force. 2. The rising member comprises a symmetrical body and a straight cross member.
An input device according to claim 1. 3. The input device according to claim 1, wherein the rising member includes a left-right symmetrical body and a syncline cross member. 4. The rising member further comprises a pivotal connection device in physical communication with the straight cross member and the symmetrical body.
An input device according to claim 1. 5. The rising member further comprises a symmetrical body and a tactile sphere physically in communication with the symmetrical body and in circuit communication with the converter. The input device described in. 6. The input device according to claim 3, wherein the rising member further comprises a swivel connecting device that is in physical communication with the synclinal cross member and the symmetrical body. 7. The input device of claim 2, wherein the rising member further comprises a handle member in physical communication with the straight cross member. 8. The input device according to claim 3, wherein the rising member further comprises a handle member that is in physical communication with the syncline cross member. 9. A video display device comprising: (a) a central processing unit (CPU); (b) a memory circuit in circuit communication with the CPU; and (c) a circuit in circuit communication with the CPU and memory. A video circuit for generating an electrical signal corresponding to the visual image displayed above, and (d) a peripheral device interface circuit in circuit communication with the CPU for interfacing signals from an external device to the CPU. And (e) a rigid support member having a size sufficient to be used by a person for sitting purpose, and (f) a vertical height and an internal space, the vertical height being close to an individual sitting height. A member, (g) a connecting device for connecting the rising member to the rigid support member, and (h) sensing the movement of the rising member in physical communication with the rising member. A transducing device for transmitting said rising motion to a computer in the form of a typical electrical signal; (i) said rising member being in physical communication with said internal space of said rising member, An elastic device for maintaining the rising member in a predetermined position with respect to the rigid support member when not subjected to the force of 1. 10. The computer system of claim 9, wherein the rising member comprises a bilaterally symmetrical body and a straight cross member. 11. The computer system according to claim 9, wherein the rising member comprises a bilaterally symmetrical body and a syncline cross member. 12. The computer system of claim 10, wherein the rising member further comprises a pivotal connection device in physical communication with the straight cross member and the symmetrical body. 13. The rising member further comprises a bilaterally symmetrical body and a tactile sphere physically in communication with the bilaterally symmetrical body and in circuit communication with the conversion device. The computer system described in. 14. The computer system of claim 11, wherein the rising member further comprises a pivotal connection device in physical communication with the syncline cross member and the symmetrical body. 15. The computer system of claim 10, wherein the upstanding member further comprises a handle member in physical communication with the straight cross member. 16. The computer system of claim 11, wherein the upstanding member further comprises a handle member in physical communication with the synclinal cross member. 17. A rigid support member having: (a) a curved outer housing having a size sufficient for human seating use; (b) a symmetric body portion; and a vertical height. A rising member having an internal space and having the vertical height close to the sitting height of an individual; (c) a connecting device for connecting the rising member to the rigid support member; (d) the rising member and the physics A communication device for sensing the movement of the rising member and transmitting the movement of the rising member to a computer in the form of a typical electrical signal in physical communication; (e) physical communication with the rising member. And an elastic device for maintaining the rising member at a predetermined position with respect to the rigid support member when the rising member does not receive an external force. 18. The input device according to claim 17, wherein the rising member includes a left-right symmetrical body and a straight cross member. 19. The input device according to claim 17, wherein the rising member includes a bilaterally symmetrical body and a syncline cross member. 20. The rising member further comprises a bilaterally symmetrical body and a tactile sphere in physical communication with the bilaterally symmetrical body and in circuit communication with the transducing device. The input device described in.