JPH09116419A - Level shifter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the current for standstill in a level shifter circuit which has two high and low power sources and converts a short-amplitude input signal to a long-amplitude output signal. SOLUTION: The output signal of the long-amplitude signal consists of a PMOS 11, a PMOS 12, and an NMOS 13. An inverter circuit 16 of the short- amplitude signal, an inverter circuit 17 of the long-amplitude signal, and a PMOS 14 and an NMOS 15 connected similarly to inverter circuits are provided, and drains of the PMOS 14 and the NMOS 15 are given to the gate of the PMOS 11 in commons, and the inverter circuit 17 is made function as a switching power source for the PMOS 14 and the NMOS 15, and thereby, the PMOS 11 is completely turned off when the short-amplitude input signal is in the low level, thus suppressing the current for standstill.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shifter circuit of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, as a level shifter circuit for converting a low-amplitude signal into a high-amplitude signal, there is a level shifter circuit shown in FIG. It is composed of an inverter circuit 51 for receiving and an inverter circuit 52 which is connected to a power supply of 5V and receives an output signal S52 of the inverter circuit 51 and converts the output signal S52 into a high amplitude signal of 5V amplitude and outputs the high amplitude signal. Then, the inverter circuit 52
Has a logic threshold voltage of about 1.5V, which is about half the amplitude of the signal 51.

Using the timing diagram of FIG.
To explain the operation of the level shifter circuit shown in (A), first, the input signal S51 is at H level (high level: 3V).
, The output S52 of the inverter circuit 51 becomes L level (low level: 0V), and the output signal S53 becomes H level (5V) (time t1). Next, when the input signal S51 is changed to L level, the output S of the inverter circuit 51 is changed.
52 becomes H level and the output signal S53 becomes L level (time t2). Next, when the input signal S51 is changed to H level, the output S52 of the inverter circuit 51 becomes L level and the output signal S53 becomes H level (time t3).

[0004]

However, in the circuit described above, a signal of 3V amplitude can be converted to a signal of 5V amplitude, but as shown in FIG. The output is at H level (3V), and the NMOS (not shown) of the inverter circuit 52 is O
In the N state, the PMOS (not shown) is not completely in the OFF state, that is, the output S of the inverter circuit 51.
Since 52 (3V) is smaller than the power supply potential (5V) -threshold voltage (≈0.7V) of the MOS transistor, a DC-like current Idc flows. Therefore, a stationary current flows, which is a problem.

[0005]

According to the present invention, there is provided a circuit having a circuit input terminal to which a low-amplitude input signal is input from a circuit having a first power supply and a circuit having a second power supply having a power supply voltage higher than that of the first power supply. A circuit output terminal for outputting an amplitude output signal, a source / drain path connected between the first power supply terminal and a common potential point, and an input terminal connected to the circuit input terminal.
The present invention relates to a level shifter circuit including an inverter circuit.

According to a first aspect of the present invention, the source / drain path is connected between the second power supply terminal and the common potential point, and the input terminal is connected to the circuit output terminal, and the source / drain path. Are connected in series and are connected between the second power supply terminal and the common potential point, a first conductivity type (eg P type) first MOS transistor, a first conductivity type (eg N type) second MOS transistor, and A second conductivity type third MOS transistor, a source / drain path connected in series, and a first conductivity type third MOS transistor and a second conductivity type third MOS transistor connected between the output terminal of the second inverter circuit and the common potential point. And a fourth MOS transistor.

The second MOS transistor and the third M
The gate of the OS transistor is commonly connected to the output terminal of the first inverter circuit, the drains of the second MOS transistor and the third MOS transistor are commonly connected to the circuit output terminal, and further, the fourth MOS transistor and the fifth MOS transistor are connected together. The gates are commonly connected to the circuit input terminal, and the fourth MOS transistor and the fifth MOS are connected.
The drain of the transistor is commonly connected to the gate of the first MOS transistor.

With such a configuration, when the low-amplitude input signal is at the L level, a high-amplitude (for example, 5V) H-level signal is generated by the second inverter circuit and the fourth MOS transistor and the fifth MOS transistor. It is applied to the first MOS transistor. Therefore, the source
A first drain circuit is connected in series to form an output circuit
In the third MOS transistor, the second MOS transistor is not completely turned off as in the conventional case, but the first MOS transistor is completely turned off, and the quiescent current in the first to third MOS transistors is blocked.

According to a second aspect of the present invention, the source / drain path is connected between the second power supply terminal and the common potential point, and the input / output terminal is connected to the circuit output terminal. A first conductivity type first MOS connected in series and connected between a second power supply terminal and a common potential point
A transistor and a second conductivity type second MOS transistor, and a first conductivity type whose source / drain path is connected between the gate of the first MOS transistor and the gate of the second MOS transistor and whose gate is connected to the output terminal of the second inverter circuit. -Type third MOS transistor and source
The drain path includes a fourth MOS transistor of the first conductivity type and a fifth MOS transistor of the second conductivity type, which are connected in series and are connected between the output terminal of the second inverter circuit and the common potential point.

The gate of the first MOS transistor is connected to the output terminal of the first inverter circuit and
The drains of the OS transistor and the second MOS transistor are commonly connected to the circuit output terminal, the gates of the fourth MOS transistor and the fifth MOS transistor are commonly connected to the circuit input terminal, and the drains of the fourth MOS transistor and the fifth MOS transistor are common. Common to the second MO
It is connected to the gate of the S transistor.

With such a configuration, when the low-amplitude input signal is changed to the L level, the high-amplitude H-level signal is once output to the gate of the first MOS transistor by the first inverter circuit and the third MOS transistor. To the second inverter circuit and the fourth MOS
A high-amplitude H-level signal is applied to the gate of the first MOS transistor by the transistor and the fifth MOS transistor. Therefore, in the first and second MOS transistors forming the output circuit with the source / drain paths connected in series, the first MOS transistor is a complete OF.
The state becomes F, and the quiescent current in the first and second MOS transistors is blocked. When the low-amplitude input signal is at the H level, the third MOS transistor is in the ON state and the L-level output of the first inverter circuit is the first MO transistor.
Since it is given to the gate of the S transistor, the first and second MOS transistors forming the output circuit function as an inverter circuit as in the conventional case.

[0012]

FIG. 1 shows a first embodiment of the present invention.
1 will be described with reference to the PMOS (P
Channel MOS transistor) 11, PMOS 12, N
MOS (N channel MOS transistor) 13, PMO
S14, NMOS 15, inverter circuit 16, and P
It has an inverter circuit 17 composed of a MOS 17a and an NMOS 17b, and has a configuration in which a low-amplitude signal of 3V is given from the terminal 10a and a high-amplitude signal of 5V is output from the terminal 10b.

The terminal 10a is connected to the inverter circuit 16
Is connected to the input of each and the gates of the PMOS 14 and the NMOS 15, and the output of the inverter circuit 16 is PMOS.
12 and NMOS 13 are connected to respective gates, PM
The drain of each of the OS 12 and the NMOS 13 is the terminal 10
The inverter circuit 17 has an input connected to the terminal 10b.
The output of the inverter circuit 17 is connected to the PMOS 14
Connected with the source of. Also, NMOS 13 and 1
5 source is connected to the ground potential, the inverter circuit 16 is connected to the power supply potential of 3V, and the inverter circuit 17 and P
The source of the MOS 11 is connected to the 5V power supply potential.

Next, the rising / falling operation will be described with reference to FIG. 2. First, when the low-amplitude input signal S11 is at L level, the output S12 of the inverter circuit 16 is at H level.
Level (3V), NMOS13 is ON, PM
Since the OS12 is in a state close to OFF (as described above, it is not completely OFF), the high-amplitude output signal S13 becomes L level, and therefore the output S14 of the inverter circuit 17 becomes H level, Since the PMOS 14 is in the ON state and the NMOS 15 is in the OFF state,
5V is applied to the gate of PMOS11,
1 is in a completely OFF state (time t1). Therefore,
Even if the PMOS 12 is not completely off,
PM that constitutes the output circuit because 11 is in the OFF state
No quiescent current flows in the path of the OS 11, the PMOS 12, and the NMOS 13.

Next, from this state, the low-amplitude input signal S1
When 1 is changed to the H level (3V), the output S12 of the inverter circuit 16 becomes the L level, the PMOS 12 is in the ON state, and the NMOS 13 is in the OFF state.
Since 14 is close to OFF and NMOS 15 is ON, PMOS 11 is ON, the output signal S13 is at H level (5V), and the output S14 of the inverter circuit 17 is at L level (time t2). .
In this case, the output S14 of the inverter circuit 17 is at the L level, so that no quiescent current flows in the paths of the PMOS 14 and the NMOS 15.

Next, when the input signal S11 is changed to the L level from this state, the output S1 of the inverter circuit 16 is output.
2 becomes H level (3V), the PMOS 12 is close to OFF, and the NMOS 13 is ON, so that the output signal S13 becomes L level, the output S14 of the inverter circuit 17 becomes H level (5V), and the PMOS 14 becomes ON.
State and the NMOS 15 is off, PM
The OS 12 is turned off (time t3).

As described above, according to the first embodiment, when the input voltage S11 is at the L level, the PMOS 12 is not in the completely OFF state, but the PMOS 11 is in the completely OFF state. Therefore, the PMOS 11 is in the OFF state. , PMOS1
2. DC current does not flow in the NMOS 13 path. Therefore, the quiescent current in this state can be suppressed.

A second embodiment of the present invention will be described with reference to FIG. 3. In FIG. 3, the PMOS 31 and NMO are shown.
S32, PMOS33, PMOS34, NMOS35,
Inverter circuit 36, and PMOS 37a and NMO
The inverter circuit 37 is composed of S37b, and a low-amplitude signal of 3V is given from the terminal 30a, and a high-amplitude signal of 5V is output from the terminal 30b.

The terminal 30a is connected to the inverter circuit 36.
Is connected to the input of each and the gates of the PMOS 34 and the NMOS 35, and the output of the inverter circuit 36 is an NMOS.
Connected to the gate of 32 and the drain of PMOS 33,
The drain of the NMOS 32 is connected to the terminal 30b together with the drain of the PMOS 31, the input of the inverter circuit 37 is connected to the terminal 30b and the output is connected to the gate of the PMOS 33 and the source of the PMOS 34, and the drain of the PMOS 33 is connected to the drains of the PMOS 34 and the NMOS 35 together with the PMOS 31. Is connected to the gate. Further, the inverter circuit 36 is connected to the power supply potential of 3V, and the NMO
The source of S32 is connected to the ground potential, and the source of the PMOS 31 and the inverter circuit 37 are connected to the power supply potential of 5V.

Next, the rising / falling operation will be described with reference to FIG. 4. First, when the input signal S31 is at L level, the output S32 of the inverter circuit 36 becomes H level (3V) and the NMOS 32 becomes ON state. , The output signal S33 becomes L level, the output S34 of the inverter circuit 37 becomes H level (5V), and the PMOS 34 becomes O.
Since the NMOS 35 is in the OFF state and the PMOS 33 is in the OFF state in the N state, the signal S35 at the gate of the PMOS 31 is at the H level (5V) and the PMOS 31 is in the OFF state (time t1). Thus, the PMOS
Since 5V is applied to the gate of 31, the PMOS 31 is turned off. Therefore, the PM that constitutes the output circuit
No quiescent current flows in the path of the OS 31 and the NMOS 32.

Next, when the input signal S31 is changed from this state to the H level (3V), the output S32 of the inverter circuit 36 becomes the L level, so that the NMOS 32 is OF.
In the F state, the PMOS 34 is in a state close to OFF, the NMOS 35 is in the ON state, and the signal S35 is in the L level, so that the PMOS 31 is in the ON state.
The output signal S33 becomes H level (5V), the output S34 of the inverter circuit 37 becomes L level, and PMO
S33 is turned on (time t2).

Next, when the input signal S31 is changed to the L level from this state, the output S3 of the inverter circuit 36 is generated.
2 becomes H level (3V), so NMOS 32 is ON
And the PMOS 33 is in the ON state, PM
The signal S35 at the gate of OS31 is at H level (3
V), the PMOS 31 is in a state close to OFF,
The output signal S33 becomes L level, and the inverter circuit 37
Output S34 of H level (5V), PMOS33
Turns off, the PMOS 34 turns on and N
Since the MOS 35 is in the OFF state, the signal S34 at the gate of the PMOS 31 is at the H level (5V), so that the PMOS 31 is in the OFF state (time t3).

As described above, according to the second embodiment, when the input signal S31 is at the L level, the PMOS 31 is turned off, so that no DC current flows through the path between the PMOS 31 and the NMOS 32. Therefore, the quiescent current in this state can be suppressed. Further, the configuration of the transistor for driving the output signal S33 is one PMOS between the power supply potentials,
Since there is one NMOS between the ground potentials, the driving ability can be easily changed.

[0024]

As is apparent from the above description, according to the present invention, a high-amplitude output circuit is composed of two or three MOS transistors, and further two or three MOS transistor high-amplitude inverter circuits are provided. Since these additional circuits make it possible to completely turn off one MOS that constitutes the high-amplitude output circuit when the low-amplitude input signal is at the L level, the quiescent current Can be suppressed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a level filter circuit showing a first embodiment of the present invention.

FIG. 2 is a timing diagram showing the operation of the level sillter circuit of FIG.

FIG. 3 is a circuit diagram of a level filter circuit showing a second embodiment of the present invention.

FIG. 4 is a timing diagram showing the operation of the level sillter circuit of FIG.

FIG. 5 is an explanatory view of a conventional technique.

[Explanation of symbols]

 11, 12 PMOS 13 NMOS 14, PMOS 15 NMOS 16 inverter circuit 17 inverter circuit 17a PMOS 17b NMOS

Claims (2)

[Claims] 1. A circuit for outputting a high-amplitude output signal to a circuit having an input terminal to which a low-amplitude input signal is input from a circuit having a first power supply and a circuit having a second power supply having a power supply voltage higher than that of the first power supply. A level shifter circuit comprising an output terminal and a first inverter circuit in which a source / drain path is connected between a first power supply terminal and a common potential point and an input terminal is connected to the circuit input terminal. A second inverter circuit having a path connected between the second power supply terminal and the common potential point and an input terminal connected to the circuit output terminal, and the source / drain path connected in series, and the second power supply terminal and the common potential A first conductivity type first MOS transistor, a first conductivity type second MOS transistor, and a second conductivity type third M connected to a point
A fourth MOS transistor of the first conductivity type and a fifth MOS of the second conductivity type, in which an OS transistor and a source / drain path are connected in series and are connected between the output terminal of the second inverter circuit and a common potential point. A transistor, the gates of the second MOS transistor and the third MOS transistor are commonly connected to the output terminal of the first inverter circuit, and the drains of the second MOS transistor and the third MOS transistor are common. An output terminal, the gates of the fourth MOS transistor and the fifth MOS transistor are commonly connected to the circuit input terminal,
The level shifter circuit is characterized in that the drains of the fourth MOS transistor and the fifth MOS transistor are commonly connected to the gate of the first MOS transistor. 2. A high-amplitude output signal is output to a circuit having an input terminal to which a low-amplitude input signal is input from a circuit having a first power supply terminal and a circuit having a second power supply having a power supply voltage higher than that of the first power supply terminal. A level shifter circuit having a circuit output terminal and a first inverter circuit having a source / drain path connected between a first power supply terminal and a common potential point and an input terminal connected to the circuit input terminal; A second inverter circuit in which the drain path is connected between the second power supply terminal and the common potential point and the input terminal is connected to the circuit output terminal, and the source / drain path is connected in series, and the second power supply terminal is connected. Connected between the common potential point and the first conductive type first M
An OS transistor and a second conductivity type second MOS transistor, a source / drain path is connected between a gate of the first MOS transistor and a gate of the second MOS transistor, and a gate is connected to an output terminal of the second inverter circuit. The fourth MOS transistor of the first conductivity type, in which the third MOS transistor of the first conductivity type and the source / drain path are connected in series and connected between the output terminal of the second inverter circuit and the common potential point And a second conductivity type fifth MOS transistor, the gate of the first MOS transistor is connected to the output terminal of the first inverter circuit, and the drain of the first MOS transistor and the second MOS transistor is common to the circuit. The fourth MOS transistor and the fourth MOS transistor are connected to the output terminal. The gate of the 5MOS transistor is commonly connected to the circuit input terminal,
The level shifter circuit is characterized in that the drains of the fourth MOS transistor and the fifth MOS transistor are commonly connected to the gate of the first MOS transistor.