JPH09107242A - Fm modulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve various characteristics of an FM modulation circuit by applying a modulation signal to a varactor diode, which controls the center frequency, through a resistance. SOLUTION: A control voltage IN1 to determine the center frequency of the FM modulation circuit is inputted from an input terminal 51. Meanwhile, a modulation signal IN2 applying FM modulation is inputted from an input terminal 61 to the FM modulation circuit. This modulation signal IN2 has the voltage divided by resistances 52 and 55 and is applied to an anode (a) of a varactor diode 53. When a supply voltage VCC is applied in this state, an oscillation output signal OUT can be taken out from an output terminal 73. The oscillation frequency of this FM modulation circuit is determined by the resonance frequency between the resultant capacity of varactor diodes 53 and 58 and capacitors 56, 57, 64, 70, and 71 and an inductance 63.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FM modulation circuit used in, for example, a mobile phone.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram of a conventional PLL-FM modulation circuit. This PLL-FM modulation circuit uses the modulated wave IN
Has an input terminal 1 for inputting. The input terminal 1 is connected to the anode a of the variable capacitance diode 3 via the capacitor 2.
It is connected to the. Anode a of the variable capacitance diode 3
Is connected to the ground via the capacitor 4, and
It is connected to the negative voltage generating circuit 6 via the resistor 5. On the other hand, the cathode k of the variable capacitance diode 3 is connected to the node N1 via the capacitor 7. Node N1
Is connected to the ground via the inductance 8. Further, the node N1 is connected to the node N via the capacitor 9.
2 are connected. The node N2 is connected to the ground via the resistor 10. Node N2 is transistor 1
1 and the collector of the transistor 11 via the resistor 12. The collector of the transistor 11 is connected to the power supply potential VCC. The emitter of the transistor 11 is connected to the ground via the resistor 13. Further, the emitter of the transistor 11 is connected to the transistor 1 via the capacitor 14.
1 and the ground via the capacitor 15. The collector of the transistor 11 is connected to the ground via the capacitor 16. Further, the emitter of the transistor 11 is connected to the input side of the high frequency amplifier 18 via the capacitor 17. The modulated wave OUT is output from the output side of the high frequency amplifier 18. Further, the output side of the high frequency amplifier 18 is connected to a modulated wave input terminal of a phase comparison circuit (hereinafter referred to as a PLL circuit) 19. P
The reference frequency F is input to the reference signal input terminal of the LL circuit 19. The output terminal of the PLL circuit 19 is connected to the input side of a low pass filter (hereinafter referred to as LPF) 20. The output side of the LPF 20 is connected to the cathode k of the variable capacitance diode 3 via the resistor 21. In this PLL-FM modulation circuit, the control voltage S20 applied to the cathode k of the variable capacitance diode 3 is used.
The center frequency is controlled based on (that is, the output signal of the LPF 20). When the center frequency is higher than the desired frequency, the control voltage S20 is changed to the lower side, and when the center frequency is lower than the desired frequency, the control voltage S20 is changed to the higher side. The set frequency is reached.

FIG. 3 is a characteristic diagram of control voltage versus oscillation frequency of the PLL-FM modulation circuit shown in FIG. This PLL-F
In the M modulation circuit, the negative bias voltage S6 generated by the negative voltage generation circuit 6 is applied to the anode a of the variable capacitance diode 3. As shown in FIG. 3, when the control voltage S20 from the LPF 20 in FIG. 2 is about 2V, the center frequency is set to the desired 145 MHz. Characteristic A is negative bias voltage S
6 is a characteristic of control voltage vs. oscillation frequency when 6 is not applied, and characteristic B is a negative bias voltage (-2 V in FIG. 3) S6
Is a characteristic of control voltage vs. oscillation frequency when is applied.
It is desirable for the FM modulation circuit to obtain a constant frequency deviation with respect to the input level of the modulation wave IN regardless of the magnitude of the control voltage S20. In addition, FM radio apparatuses are generally required to have a certain frequency shift at a constant input level of a modulated wave. For example, when an audio signal with a frequency of 1 KHz and 20 dBV is input, the frequency deviation is required to be within ± 3.5 KHz p-p ± 10%. Therefore, it is desired that the control sensitivity (that is, the ratio of the change in the oscillation frequency to the change in the control voltage) does not change even when the control voltage changes. From FIG. 3, by applying the negative bias voltage S6 to the anode a of the varactor diode 3, a portion having a good linearity of the applied voltage vs. the oscillation frequency is used, and compared with the case of no bias. It can be seen that the deviation of the frequency shift is greatly reduced.

FIG. 4 is a circuit diagram of another conventional PLL-FM modulation circuit. This PLL-FM modulation circuit uses the modulated wave I
It has an input terminal 31 for inputting N. Input terminal 31
Is connected to the cathode k of the variable capacitance diode 33 via the resistor 32. The anode a of the variable capacitance diode 33 is connected to the ground. Further, the cathode k of the variable capacitance diode 33 is connected to the node N11 via the capacitor 34. The node N11 is connected to the cathode k of the variable capacitance diode 36 via the capacitor 35. The anode a of the variable capacitance diode 36 is connected to the ground. Node N11
Are connected to the ground via an inductance 37. Further, the node N11 is connected to the node N22 via the capacitor 38. Node N22 is resistor 39
Connected to the ground via The node N22 is connected to the base of the transistor 40 and also has a resistor 41.
Is connected to the collector of the transistor 40 via. The collector of the transistor 40 is connected to the power supply potential VCC. The emitter of the transistor 40 is a resistor 4
2 to ground. Further, the emitter of the transistor 40 is connected to the base of the transistor 40 via the capacitor 43 and to the ground via the capacitor 44. The collector of the transistor 40 is connected to the ground via the capacitor 45. Further, the emitter of the transistor 40 is connected to the input side of the high frequency amplifier 47 via the capacitor 46. The modulated wave OUT is output from the output side of the high frequency amplifier 47.
The output side of the high frequency amplifier 47 is connected to the modulated wave input terminal of the PLL circuit 48. The reference frequency F is input to the reference signal input terminal of the PLL circuit 48. The output terminal of the PLL circuit 48 is an LPF 49
Is connected to the input side. The output side of the LPF 49 is connected to the cathode k of the variable capacitance diode 36 via the resistor 50. That is, in this PLL-FM modulation circuit, the variable capacitance diode 36 for applying the control voltage for controlling the center frequency and the variable capacitance diode 33 for applying the modulation wave IN for FM modulation are separated. FIG. 5 is FIG.
6 is a characteristic diagram of control voltage versus oscillation frequency of the PLL-FM modulation circuit shown in FIG. From FIG. 5, when the variable capacitance diode 36 for applying the control voltage for controlling the center frequency and the variable capacitance diode 33 for applying the modulation wave IN for FM modulation are separated, the change in the control sensitivity when the control voltage changes. You can see that it can be made smaller.

[0005]

However, the PLL-FM modulation circuit of FIG. 2 has the following problems.
That is, in the method of applying the negative bias S6 to the variable capacitance diode 3, it is necessary to separately prepare a bias circuit such as the negative voltage generation circuit 6 or a bias voltage. Therefore, the circuit becomes complicated, and it is difficult to reduce the size and cost. Further, the PLL-FM modulation circuit of FIG. 4 improves the characteristics of the center frequency and the degree of modulation, but sufficient characteristics can be obtained in a wide usage band of 27 MHz such as an analog type mobile phone. Sometimes there is not. Moreover, in order to obtain an FM modulated wave in an FM communication device using a method of superimposing a signal for data transmission in a frequency range lower than the voice band,
Although an L-FM modulator is used, in order to obtain stable modulation frequency characteristics, it is necessary to adjust the center frequency in order to improve the accuracy of the oscillation frequency of the voltage controlled oscillator.
It is necessary to select the source current value and the sink current value of the charge pump circuit of the PLL-IC so as to deal with them, and it is difficult to reduce the cost by unadjusting the device, and the PLL-IC.
There was a problem such as an increase in the price of IC due to the selection of characteristics.

[0006]

In order to solve the above problems, a first invention is directed to a center frequency controlling variable capacitance diode to which a control voltage for controlling the center frequency is inputted to a cathode, and the center frequency to an anode. An FM modulation circuit having a modulation variable capacitance diode to which a modulation signal to be modulated is input and generating a modulated wave having an oscillation frequency based on the control voltage and the modulation signal, takes the following means. . That is, a first resistor for setting the modulation signal at a desired level and inputting it to the anode of the center frequency controlling variable capacitance diode and a second resistor for applying a fixed bias voltage to the cathode of the modulation variable capacitance diode. And a resistor are provided. According to the first aspect of the invention, since the FM modulation circuit is configured as described above, the modulation signal set to the desired level by the first resistor is applied to the center frequency controlling variable capacitance diode. Therefore, the change in the modulation degree when the control voltage is changed becomes small. In the second invention, the first resistor of the first invention is a variable resistor. According to the second aspect of the invention, the change characteristic of the control sensitivity when the control voltage is changed is adjusted by changing the resistance value of the first resistor.

In the third invention, the phase of the modulated wave is compared with the phase of the reference signal, and a phase comparator for generating advance information or delay information based on the comparison result and the advance information or the delay information are added. A charge pump that outputs a corresponding DC voltage through a current amplification stage, a filter that removes high-frequency components contained in the output signal of the charge pump, and a modulated signal that has an oscillation frequency based on the output voltage of the filter. An FM modulation circuit provided with an oscillator for outputting a modulated wave takes the following means. That is, on the output side of the current amplification stage of the charge pump, a current increase circuit that increases the sink current flowing out of the current amplification stage based on the output signal of the phase comparator is provided. According to the third aspect of the invention, the sink current of the charge pump is increased by the current increasing circuit. As a result, stable characteristics can be obtained even with respect to temperature fluctuations and variations in the components that make up the circuit. Therefore, the above problem can be solved.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment FIG. 1 is a circuit diagram of an FM modulation circuit showing a first embodiment of the present invention. This FM modulation circuit has an input terminal 51 for inputting a control voltage IN1 for controlling the center frequency. The input terminal 51 is connected via a resistor 52 to the cathode k of a variable capacitance diode 53 for controlling the center frequency. The resistor 52 is a resistor for supplying a bias to the variable capacitance diode 53 to determine the oscillation frequency. Anode a of the variable capacitance diode 53
Is connected to the ground via a high-frequency bypass capacitor 54 and is also connected to the ground via a resistor 55. The cathode k of the variable capacitance diode 53 is connected to the node N1 via the capacitor 56. The node N1 is connected to the cathode k of the modulation variable capacitance diode 58 via the capacitor 57.
The anode a of the variable-capacitance diode 58 is connected to the ground via the high-frequency bypass capacitor 59, and is also connected to the input terminal 61 for inputting the modulation signal IN2 via the resistor 60 for varying the modulation degree. There is. Each anode a of the variable capacitance diodes 53 and 58 has a resistor 6
2 are connected. This resistor 62 and the resistor 5
5, the first resistor is configured to input the modulation signal IN2 to the anode a of the variable capacitance diode 53 at a desired level.

On the other hand, the node N1 has an inductance 63
Connected to the ground via Also, the node N1
Is connected to the base b of the transistor 65 via the capacitor 64. The base b of the transistor 65 is
The resistor 6 is connected to the ground through the resistor 66, and
It is connected to the power supply potential VCC via 7. The collector c of the transistor 65 is connected to the power supply potential VCC and also to the ground via the capacitor 68. The emitter e of the transistor 65 is connected to the ground via the resistor 69 and to the ground via the capacitor 70. The emitter e of the transistor 65 is connected to the transistor 6 via the capacitor 71.
5 is connected to the base b. Furthermore, the transistor 6
The emitter e of 5 is connected to the output terminal 7 via the capacitor 72.
Connected to 3. Further, the variable capacitance diode 5
The cathode k of No. 8 has a power supply potential V through a second resistor 74 for supplying a bias to the variable capacitance diode 58.
Connected to CC.

Next, the operation of FIG. 1 will be described. Input terminal 5
From 1, the control voltage IN1 for determining the center frequency of this FM modulation circuit is input. On the other hand, from the input terminal 61, the modulation signal IN2 for FM-modulating the FM modulation circuit is input. The modulation signal IN2 is applied to the resistor 60.
Is applied to the anode a of the variable capacitance diode 58 via. Further, the modulation signal applied to the anode a of the variable capacitance diode 58 is divided by the resistors 62 and 55 and applied to the anode a of the variable capacitance diode 53. When the power supply voltage VCC is applied in this state, the oscillation output signal OUT can be taken out from the output terminal 73. The oscillating frequency of this FM modulation circuit is variable capacitance diodes 53, 58 and capacitors 56, 57, 64, 7
It is determined by the resonance frequency of the combined capacitance of 0 and 71 and the inductance 63. FIG. 6 is a circuit diagram of an FM modulation circuit in which the modulation signal IN2 is applied to the center frequency controlling variable capacitance diode 53 in FIG. That is, this F
In the M modulation circuit, the input terminal 61 is connected to the anode a of the variable capacitance diode 53 via the resistor 60.
Further, the capacitor 57, the variable capacitance diode 58, the capacitor 59, the resistor 62, and the resistor 74 are deleted.
Other configurations are the same as those in FIG. FIG. 7 is a characteristic diagram of FIG. 6, in which the vertical axis represents the oscillation frequency and the relative modulation degree deviation, and the horizontal axis represents the control voltage.

FIG. 8 is a circuit diagram of an FM modulation circuit in which a modulation signal is applied only to the modulation variable capacitance diode 58 shown in FIG. That is, in this FM modulation circuit, the resistor 62 is removed and the anode a of the variable capacitance diode 58 is removed.
Is connected to the ground via the resistor 55A. Other configurations are the same as those in FIG. FIG. 9 is a characteristic diagram of FIG. 8, in which the oscillation frequency and the relative modulation degree deviation are plotted on the vertical axis, and the control voltage is plotted on the horizontal axis. Comparing these FIG. 7 and FIG. 9, the provision of the modulation variable capacitance diode 58
It can be seen that the change in the degree of modulation is smaller than that when the variable capacitance diode 53 for controlling the center frequency is modulated. FIG.
6 is a characteristic diagram 1 of the FM modulation circuit of FIG. 1 in which the FM modulation circuits of FIGS. 6 and 8 are combined, in which the oscillation frequency and relative modulation degree deviation are plotted on the vertical axis, and the control voltage is plotted on the horizontal axis.
From FIG. 10, it can be seen that the modulation factor with respect to the oscillation frequency is further improved.

FIG. 11 is a characteristic diagram 2 of the FM modulation circuit of FIG. 1, in which the vertical axis represents the control sensitivity and the horizontal axis represents the control voltage. From this figure, it is understood that the change characteristic of the control sensitivity when the control voltage IN1 is changed is changed by changing the resistance value of the resistor 62. As described above, in the first embodiment, by applying the modulation signal IN2 to the oscillation frequency control variable capacitance diode 53 via the resistor 62, the modulation degree when the control voltage IN1 is changed is changed. It can be extremely small. Further, the resistor 62
By varying the resistance value of, the change characteristic of the control sensitivity when the control voltage IN1 is changed can be adjusted.

Second Embodiment FIG. 12 is a circuit diagram of an FM modulation circuit showing a second embodiment of the present invention. This FM modulation circuit has a modulation signal IN3.
It has an input terminal 81 for inputting. Input terminal 81
Is connected to the modulation signal input terminal of the oscillator 82.
The output terminal of the oscillator 82 is connected to the output terminal 83 that outputs the FM wave OUT. Also, this FM modulation circuit is
LL-IC90 is provided. The PLL-IC 90 has a comparison frequency input terminal 91 connected to the output terminal 83. The input terminal 91 is the first terminal of the comparison frequency divider 92.
Is connected to the input terminal of Also, PLL-IC90
Has an input terminal 93 for inputting the reference signal S93. The input terminal 93 is connected to the first input terminal of the reference frequency divider 94. Furthermore, the PLL-IC90
It has a channel setting signal input terminal 95. The input terminal 95 is connected to the input terminal of the latch circuit 96.
The output terminal of the latch circuit 96 is connected to the second input terminal of the comparison frequency divider 92 and the second input terminal of the reference frequency divider 94. The output terminal of the comparison frequency divider 92 is connected to the comparison signal input terminal of the phase comparator 97. The output terminal of the reference frequency divider 94 is connected to the reference signal input terminal of the phase comparator 97.

The lead phase difference signal φP output terminal of the phase comparator 97 is connected to the lead phase difference signal input terminal of the charge pump 98, and the delayed phase difference signal φR output terminal of the phase comparator 97 is the delay level of the charge pump 98. It is connected to the phase difference signal input terminal. Output terminal 99 of charge pump 98
Is connected to the collector c of the transistor 100 and is also connected to the input terminal of the LPF 102 via the lag lead filter 101. The lead phase difference signal output terminal of the phase comparator 97 is connected to the output terminal T1, and the lag phase difference signal output terminal of the phase comparator 97 is the output terminal T2.
Is connected to the base b of the transistor 100 via the resistor 103. The emitter e of the transistor 100 is connected to the ground. Transistor 10
0 and the resistor 103 constitute a current increasing circuit. L
The output terminal of the PF 102 is connected to the control signal input terminal of the oscillator 82.

FIG. 13 shows a charge pump 98 shown in FIG.
FIG. The charge pump 98 has an input terminal 98a for inputting the lead phase difference signal φP. The input terminal 98a is connected to the transistor 98 via the resistor 98b.
It is connected to the base of c. The base of the transistor 98c is connected to the power supply potential VCC via the resistor 98d. The emitter of the transistor 98c is connected to the power supply potential VCC. Also, this charge pump 9
Reference numeral 8 has an input terminal 98e for inputting the delayed phase difference signal φR. The input terminal 98e is connected to the base of the transistor 98g via the resistor 98f. The base of the transistor 98g is connected to the ground G via the resistor 98h.
Connected to ND. The emitter of the transistor 98g is connected to the ground GND. The collectors of the transistors 98c and 98g are both connected to the output terminal 99. FIG. 14 shows the charge pump 9 of FIG.
8 is a diagram showing a state of the output signal of FIG.

Next, the operation of FIG. 12 will be described. Oscillator 8
The FM wave OUT output from 2 is input to the comparison frequency input terminal 91 of the PLL-IC 90. In addition, the channel setting signal S input from the channel setting signal input terminal 95
95 is input to the comparison frequency divider 92 and the reference frequency divider 94 via the latch circuit 96. The FM wave OUT input from the input terminal 91 is the channel setting signal S95.
The frequency division signal fp is divided by the frequency division number designated by and is output to the phase comparator 97. Similarly, the reference signal S93 input from the input terminal 93 is frequency-divided by the frequency division number designated by the channel setting signal S95 to become the frequency division signal fr, which is output to the phase comparator 97. The phase comparator 97 compares the phases of the two frequency-divided signals fp and fr, and outputs the output signals φP and φR to the charge pump 98 and the output terminals T1 and T2 according to the phase difference. The charge pump 98, as shown in FIG.
Lag lead filter 1 based on the output signals φP and φR of
01 and LPF 102 are driven by current. FIG. 15 is a time chart for explaining the operation of FIG. 12, in which the vertical axis represents the logic level and the horizontal axis represents time.

The operation of FIG. 12 will be described with reference to this figure. In a section where the level of the divided signal fr is higher than the level of the divided signal fp, the output signal S9 of the charge pump 98
8 is an output pulse from the high impedance state to the high level V. In a section where the level of the divided signal fr is equal to the level of the divided signal fp, the output signal S98 outputs a positive / negative symmetrical pulse from the high impedance state to the high level V and 0 volt. In the section where the level of the divided signal fr is smaller than the level of the divided signal fp, the output signal S98 outputs a negative pulse from the high impedance state to 0 volt. The output signal S98 is appropriately attenuated by the lag lead filter 101, and further, a spurious wave component generated at the output terminal 99 is removed by the LPF 102 to become a DC voltage for the frequency control required by the oscillator 82, and the modulation signal IN
3 is added and input to the frequency control terminal of the oscillator 82. Here, the transistor 100 is the charge pump 9
8 is a transistor for pulling the output signal S98 of 8 to the ground side. FIG. 16 is a time chart for explaining the operation of FIG. 13, in which the vertical axis represents the logic level and the horizontal axis represents time.

The operation of FIG. 13 will be described with reference to this figure. The output characteristics of the charge pump 98 are designed so that the source current and the sink current are balanced to some extent, but in order to eliminate the dead zone of the PLL-IC 90,
As shown in FIG. 16, the sink current is made larger than the source current, and the source side circuit and the sink side circuit are simultaneously turned on to generate an output pulse. However, the actual charge pump output waveform is the output signal S9 in FIG. 16 due to the stray capacitance of the circuit, the switching delay time of the circuit, the ambient temperature, the current difference between the source current and the sink current, and the like.
The characteristic fluctuates as shown by the broken line 8 and this variation has a great influence on the modulation frequency characteristic. Here, by adding the transistor 100 shown in the present embodiment, the waveform shown in the output signal S98A in FIG. 16 is obtained, and only the rounding of the waveform due to the stray capacitance is seen, and stable characteristics can be obtained.

FIG. 17 is a characteristic diagram of FIG. 12, in which the vertical axis represents the modulation degree deviation and the horizontal axis represents the modulation frequency. In this figure, data indicating the stability of each modulation frequency characteristic with and without the transistor 100 is shown. The transistor 100 has a cutoff frequency as high as possible in a low collector current region (for example,
Transistor with Ic = 1mA / cutoff frequency ≧ 1 GHz)
Better effect can be expected. As described above, in the second embodiment, the transistor 100 for increasing the sink current in the output portion of the charge pump 98 is used.
Since, since the modulation frequency characteristic is flattened to a low frequency range, a stable characteristic with respect to temperature fluctuations and PLL-IC variations can be obtained.

[0020]

As described above in detail, according to the first aspect of the present invention, the center frequency controlling variable capacitance diode has the first aspect.
Since the modulation signal is applied via the resistance of, the change of the modulation degree when the control voltage is changed can be reduced. According to the second invention, since the first resistor of the first invention is a variable resistor, the control sensitivity is changed when the control voltage is changed by changing the resistance value of the first resistor. The characteristics can be adjusted. According to the third aspect of the present invention, a current increasing circuit for increasing the sink current of the charge pump is added to the output section of the charge pump, so that stable characteristics can be obtained with respect to temperature fluctuations and variations in the components forming the circuit. Obtainable.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an FM modulation circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional PLL-FM modulation circuit.

FIG. 3 is a characteristic diagram of FIG.

FIG. 4 is a circuit diagram of another conventional PLL-FM modulation circuit.

FIG. 5 is a characteristic diagram of FIG.

6 is a circuit diagram of an FM modulation circuit that applies a modulation signal to a variable capacitance diode 53 in FIG.

FIG. 7 is a characteristic diagram of FIG.

FIG. 8 is a circuit diagram of an FM modulation circuit that applies a modulation signal only to a modulation variable capacitance diode 58 in FIG.

9 is a characteristic diagram of FIG.

FIG. 10 is a characteristic diagram 1 of FIG.

FIG. 11 is a characteristic diagram 2 of FIG.

FIG. 12 is a circuit diagram of an FM modulation circuit showing a second embodiment of the present invention.

13 is a circuit diagram of the charge pump 98 in FIG.

14 is a diagram showing a state of an output signal of the charge pump 98 of FIG.

FIG. 15 is a time chart of FIG.

16 is a time chart of FIG.

FIG. 17 is a characteristic diagram of FIG.

[Explanation of symbols]

53, 58 Variable capacitance diode 55, 62 First resistor 74 Second resistor 82 Oscillator 97 Phase comparator 98 Charge pump 100 Transistor (current increasing circuit) 102 Filter 103 Resistor (current increasing circuit)

Claims (3)

[Claims] 1. A center frequency controlling variable capacitance diode having a cathode to which a control voltage for controlling a center frequency is input,
An FM modulation circuit, comprising: a modulation variable-capacitance diode to which a modulation signal for modulating the center frequency is input, and generating a modulated wave having an oscillation frequency based on the control voltage and the modulation signal. A first resistor for setting the modulation signal to a desired level and inputting it to the anode of the control variable capacitance diode, and a second resistor for applying a fixed bias voltage to the cathode of the modulation variable capacitance diode are provided. An FM modulation circuit characterized by the above. 2. The FM modulation circuit according to claim 1, wherein the first resistor is a variable resistor. 3. A phase comparator that compares the phase of a modulated wave with the phase of a reference signal and generates advance information or delay information based on the comparison result, and a DC voltage corresponding to the advance information or the delay information. , A filter for removing high frequency components included in the output signal of the charge pump, and the modulated wave having an oscillation frequency based on the modulation signal and the output voltage of the filter. With an oscillator
In the modulation circuit, an FM current increasing circuit is provided on the output side of the current amplifying stage of the charge pump to increase the sink current flowing out of the current amplifying stage based on the output signal of the phase comparator. Modulation circuit.