JPH0897145A - Manufacture of semiconductor device, and manufacture of film transistor, and liquid crystal display - Google Patents

Abstract

PURPOSE: To provide a semiconductor device equipped with a polycrystalline silicon film having excellent characteristics. CONSTITUTION: An amorphous silicon film 2 is made on an insulating substrate (quartz glass) 1. Next, by annealing it at about 600 deg.C, an amorphous silicon film 2 is grown in solid phase so as to form a polycrystalline film 3. Furthermore, this polycrystalline silicon film 3 is heat-treated at about 1000 deg.C. Hereby, the gap between the crystals within the polycrystalline silicon film 3 contracts, and properties improve such that the leakage current decreases, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, a method for manufacturing a thin film transistor (Thin Film Transistor), and a liquid crystal display (LCD).
y).

[0002]

2. Description of the Related Art In recent years, active matrix LCDs
As a pixel driving element (pixel driving transistor), a thin film transistor using a polycrystalline silicon film formed on a transparent insulating substrate as an active layer (hereinafter, referred to as a polycrystalline silicon TFT).
That is) is under development.

Polycrystalline silicon TFTs have the advantage of higher mobility and higher driving capability than thin film transistors using an amorphous silicon film as an active layer. Therefore, if a polycrystalline silicon TFT is used, a high-performance LCD can be realized, and not only the pixel section (display section) but also the peripheral drive circuit (driver section) can be integrally formed on the same substrate.

In such a polycrystalline silicon TFT, as a method of forming a polycrystalline silicon film as an active layer, a method of directly depositing a polycrystalline silicon film on a substrate or an amorphous silicon film is formed on a substrate. Later, there is a method of polycrystallizing the same. Of these, the method of directly depositing the polycrystalline silicon film on the substrate is a relatively simple process of depositing at high temperature using, for example, the CVD method.

In order to polycrystallize an amorphous silicon film after depositing it, a solid phase growth method is generally used. This solid-phase growth method is a method in which an amorphous silicon film is subjected to heat treatment at about 600 ° C. for a long time to polycrystallize it in a solid state to obtain a polycrystalline silicon film. A CVD method, a vapor deposition method, a sputtering method, or the like is used for depositing amorphous silicon, and the deposition temperature is 600 ° C. in any method.
By keeping the temperature at about a low temperature, the deposited silicon film becomes amorphous.

[0006]

The former method of directly attaching a polycrystalline silicon film has a problem that it is difficult to manufacture a TFT having excellent characteristics because the formed film has a small grain size. In the latter case, in the solid phase growth method for polycrystallizing the amorphous silicon film, the particle size after solid phase growth depends on the film thickness of the amorphous silicon film. Initially, an amorphous silicon film was deposited to 2000 to 3000 liters, solid-phase growth was performed on the amorphous silicon film, and the surface of the polycrystalline silicon film was further oxidized. Then, the oxidized portion was removed to finally make the thickness about 500 liters. ing.

However, in this latter method, many defects such as dislocations are present in the crystal of the film after solid phase growth,
There is a lot of leakage current. Amorphous portions remain between the crystals of the film after solid phase growth, resulting in poor characteristics. At the time of oxidation, a part of the grain boundaries of the polycrystalline silicon film is also oxidized and the characteristics are deteriorated. The surface of the polycrystalline silicon film after the removal of the oxidized portion becomes rough.

It is difficult to control the amount of oxidation, and as a result, it is difficult to control the thickness of the polycrystalline silicon film. There are various problems. The present invention has been made to solve the above problems, and achieves the following objects.

1) A polycrystalline silicon film having excellent characteristics is obtained by a simple process. 2) To provide a method for manufacturing a semiconductor device provided with a polycrystalline silicon film having excellent characteristics. 3) To provide a method for manufacturing an excellent thin film transistor provided with a polycrystalline silicon film having excellent characteristics.

4) To provide an excellent liquid crystal display using an excellent thin film transistor as a pixel driving element.

[0011]

According to a first aspect of the present invention, a semiconductor device is manufactured by polycrystallizing an amorphous silicon film containing no microcrystals by a first heat treatment operation and then performing a second heat treatment operation. Is. In the method for manufacturing a semiconductor device according to claim 2, the amorphous silicon film containing microcrystals at least partially is polycrystallized by the first heat treatment operation, and thereafter,
The second heat treatment work is added.

According to a third aspect of the method of manufacturing a semiconductor device, a step of forming a first amorphous silicon film containing microcrystals, and a step of forming a first non-crystalline film on the first amorphous silicon film. Forming a second amorphous silicon film containing less microcrystals or less microcrystals than the amorphous silicon film; and forming a first amorphous silicon film in the first and second amorphous silicon films. A step of forming a polycrystalline silicon film by applying the heat treatment work of
A step of applying a second heat treatment operation to this polycrystalline silicon film is performed.

According to a fourth aspect of the method of manufacturing a semiconductor device, a step of forming a second amorphous silicon film and a step of forming a second amorphous silicon film on the second amorphous silicon film. Forming a first amorphous silicon film having a higher proportion of microcrystals than that of the first amorphous silicon film, and performing a first heat treatment on the first and second amorphous silicon films to form a polycrystalline silicon film. The step of forming and the step of applying a second heat treatment operation to this polycrystalline silicon film are performed.

According to a fifth aspect of the semiconductor device manufacturing method of the present invention, the second amorphous silicon film is formed on the second amorphous silicon film, and the second amorphous silicon film is formed on the second amorphous silicon film. Forming a first amorphous silicon film having a higher proportion of microcrystals than that of the first amorphous silicon film, and performing a first heat treatment on the first and second amorphous silicon films to form a polycrystalline silicon film. A step of forming, a step of applying a second heat treatment operation to the polycrystalline silicon film, and a step of oxidizing at least a portion of the polycrystalline silicon film formed by the heat treatment of the first amorphous silicon film. And a step of forming a silicon oxide film.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the first amorphous silicon film is provided at least in a part. In the method of manufacturing a semiconductor device according to claim 7, the second heat treatment step is made higher than the first heat treatment step. Further, in the method of manufacturing a semiconductor device according to claim 8, the time of the second heat treatment step is shorter than that of the first heat treatment step.

According to a ninth aspect of the method of manufacturing a semiconductor device, the total film thickness of the amorphous silicon film before the first heat treatment is set to a range usable as an active layer of a transistor. It is a thing. According to a tenth aspect of the method for manufacturing a semiconductor device, the total film thickness of the amorphous silicon film before the first heat treatment is set to 800 Å or less.

According to an eleventh aspect of the present invention, there is provided a method for producing a semiconductor device, wherein a polycrystalline silicon film is formed on a substrate by the method for producing a semiconductor device according to any one of the first to tenth aspects, and the polycrystalline film is formed. A silicon film is processed as an active layer of a transistor. The method of manufacturing a thin film transistor according to claim 12 is characterized in that:
0. A step of forming a polycrystalline silicon film by the method for manufacturing a semiconductor device according to any one of 0, a step of forming a gate insulating film on the polycrystalline silicon film, and a gate on the gate insulating film. A source region and a drain region are formed in the polycrystalline silicon film by a process of forming electrodes and a self-alignment technique using the gate electrode.

According to a thirteenth aspect of the present invention, in a method of manufacturing a thin film transistor, a step of forming a first amorphous silicon film containing microcrystals on an insulating substrate and a channel region in the first amorphous silicon film are formed. A step of removing the other portion while leaving only the corresponding portion, and the proportion of microcrystals on the insulating substrate and the first amorphous silicon film is smaller than that of the first amorphous silicon film. Second with or without microcrystals
Forming an amorphous silicon film, forming a polycrystalline silicon film by applying a first heat treatment to the first and second amorphous silicon films, and forming a polycrystalline silicon film on the polycrystalline silicon film. 2, a step of applying a heat treatment operation, a step of forming a gate insulating film on the polycrystalline silicon film, a step of forming a gate electrode on the gate insulating film, and a self-alignment technique using a gate electrode. And a step of forming a source region and a drain region in the crystalline silicon film.

According to a fourteenth aspect of the present invention, in a method of manufacturing a thin film transistor, a step of forming a second amorphous silicon film on an insulating substrate and a second amorphous silicon film on the second amorphous silicon film. First, the ratio of microcrystals is higher than that of the first silicon film
Forming an amorphous silicon film, removing the other part of the first amorphous silicon film corresponding to the channel region, and removing the first and second amorphous silicon films. A step of forming a polycrystalline silicon film by applying a first heat treatment operation to the crystalline silicon film, and removing at least a portion of the polycrystalline silicon film formed by heat-treating the first amorphous silicon film A step of applying a second heat treatment to the polycrystalline silicon film, a step of forming a gate insulating film on the polycrystalline silicon film, a step of forming a gate electrode on the gate insulating film, and a gate And a step of forming a source region and a drain region in the polycrystalline silicon film by a self-alignment technique using electrodes.

According to a fifteenth aspect of the present invention, in the method of manufacturing a thin film transistor, a step of forming a second amorphous silicon film on an insulating substrate, and a second amorphous silicon film on the second amorphous silicon film. First, the ratio of microcrystals is higher than that of the first silicon film
Forming an amorphous silicon film, removing the other part of the first amorphous silicon film corresponding to the channel region, and removing the first and second amorphous silicon films. A first heat treatment operation on the crystalline silicon film to form a polycrystalline silicon film, a second heat treatment operation on the polycrystalline silicon film, and at least the first of the polycrystalline silicon films. The step of forming a gate insulating film by oxidizing a portion of the amorphous silicon film formed by heat treatment of the above, a step of forming a gate electrode on this gate insulating film, and a self-alignment technique using the gate electrode And a step of forming a source region and a drain region in the polycrystalline silicon film.

According to a sixteenth aspect of the present invention, in the method of manufacturing a thin film transistor, the temperature of the second heat treatment step is set higher than the temperature of the first heat treatment step. In addition, claim 1
In the method of manufacturing a thin film transistor of No. 7, the time of the second heat treatment step is shorter than that of the first heat treatment step. In the method of manufacturing a thin film transistor according to an eighteenth aspect, the total film thickness of the amorphous silicon film before the first heat treatment work is set within a range usable as an active layer of the transistor.

The method of manufacturing a thin film transistor according to claim 19 is such that the total film thickness of the amorphous silicon film before the first heat treatment is applied is 800 Å or less. A liquid crystal display according to claim 20 is the liquid crystal display according to claim 1.
The thin film transistor manufactured by the method of manufacturing a thin film transistor according to any one of 1 to 18 is used as a pixel driving element.

[0023]

That is, according to the first aspect of the present invention, defects such as dislocations which occur in the crystal when polycrystallized by the first heat treatment step are repaired by the second heat treatment step thereafter. Further, an amorphous portion existing between crystals when polycrystallized by the first heat treatment step is polycrystallized by the second heat treatment step thereafter.

According to the invention described in claim 2, in addition to the effect of claim 1, during the first heat treatment step, the microcrystals in the amorphous silicon film serve as seeds to grow crystals, and Crystallization takes place. Therefore, if fine crystals are uniformly present in the amorphous silicon, the crystal grain size of the polycrystalline silicon film is substantially uniform over the whole. Further, the crystal grain size of the polycrystalline silicon film can be set to a desired size by adjusting the number of fine crystals in the amorphous silicon.

That is, as the number of fine crystals increases in the amorphous silicon film, the crystal growth occurs more densely, and the crystal grain size of the polycrystalline silicon film becomes smaller. Furthermore, since a seed for crystal growth exists in the amorphous silicon film at the time when the first heat treatment is started, crystal growth immediately starts, and the growth time is short accordingly. Further, according to the invention of claim 3 or claim 4, polycrystallization progresses from the first amorphous silicon film to the second amorphous silicon film by the same action as in claim 2. .

Further, according to the invention described in claim 5, polycrystallization progresses from the first amorphous silicon film to the second amorphous silicon film by the same action as in claim 3 or 4. To do. The crystal grain size of the silicon film obtained by polycrystallizing the first amorphous silicon film is smaller than that of the polycrystalline silicon film obtained by polycrystallizing the second amorphous silicon film. By oxidizing the polycrystalline silicon film having a small crystal grain size, a polycrystalline silicon film having a large crystal grain size remains.

Further, according to the invention as set forth in claim 6, the above-mentioned action can be obtained even if the crystal grain size of the first amorphous silicon film is smaller than that of the second amorphous silicon film. Occur.
According to the invention described in claim 7, in addition to these effects, the treatment effect in the second heat treatment step is improved. According to the invention described in claim 8, in addition to these actions, further shortening of the forming time is desired.

According to the ninth or tenth aspect of the present invention, it is not necessary to bother cutting the polycrystalline silicon film to a desired film thickness. Further, according to the invention described in claim 11, it is possible to improve the performance of the transistor having the polycrystalline silicon film as an active layer. According to the invention of claim 12, an excellent active layer can be obtained by the same operation as that of the invention of any one of the above claims. Further, the source and drain regions can be formed by the self-alignment technique. Therefore, it is possible to improve the performance of the planar type or stagger type polycrystalline silicon TFT.

According to the thirteenth to fifteenth aspects of the present invention, it is possible to improve the performance of the polycrystalline silicon TFT as in the case of the twelfth aspect. In addition, claim 1
According to the sixth aspect of the invention, similarly to the action of the seventh aspect, the treatment effect in the second heat treatment step is improved. Further, according to the invention of claim 17, like the operation of claim 8,
Further shortening of the forming time is desired.

According to the eighteenth or nineteenth aspect of the invention, it is not necessary to bother cutting the polycrystalline silicon film to a desired thickness, as in the case of the ninth and tenth aspects. According to the invention of claim 20, an excellent liquid crystal display can be obtained by using an excellent thin film transistor as a pixel driving element.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment embodying the present invention will be described with reference to FIGS. Step 1 (see FIG. 1a): Insulating substrate (eg quartz glass)
An amorphous silicon film 2 (film thickness 500Å) is formed on the surface 1. When this amorphous silicon film 2 is used as an active layer of a TFT, if the active layer is too thick, polycrystalline silicon T
Since the off current of the FT increases and the on current decreases when it is too thin, the film thickness of the amorphous silicon film 2 at this time is 40
The range of 0 to 800Å is suitable, the characteristics are good when it is set to 500 to 700Å, and the case of 500 to 600Å is most suitable.

There are the following methods for forming the amorphous silicon film 2. Method using low pressure CVD: In order to form a silicon film by the low pressure CVD method, thermal decomposition of monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used. In this case, when the processing temperature is 550 ° C. or lower, it becomes amorphous, and when it is 620 ° C. or higher, it becomes polycrystalline. Then, at 550 to 620 ° C., the amount of amorphous containing fine crystals increases, and as the temperature decreases, the amount of amorphous becomes closer to amorphous and the amount of fine crystals decreases. Therefore, the amount of fine crystals in the amorphous silicon film 2 can be adjusted only by changing the temperature condition.

Method using plasma CVD method: To form an amorphous silicon film by plasma CVD method, thermal decomposition of monosilane or disilane in plasma is used.
In the actual process, the above method is adopted, and an amorphous silicon film containing no microcrystals is formed under the conditions of gas used: monosilane and temperature: 550 ° C. Step 2 (see FIG. 1b): Temperature 6 in nitrogen (N ₂ ) atmosphere
By performing heat treatment at about 00 ° C. for about 20 hours, the amorphous silicon film 2 is solid-phase grown to form a polycrystalline silicon film 3.

The processing temperature for this solid phase growth is 580 to 700.
C. is suitable, preferably 600 to 700.degree. C., particularly preferably 600 to 650.degree. Below this range, the processing time for solid phase growth tends to be significantly longer,
If it is higher, the crystal grain size tends to be smaller. Step 3 (see FIG. 1c): In the polycrystalline silicon film 3 formed as described above, many defects such as dislocations are present in the crystals that form the film, and an amorphous portion remains between the crystals, resulting in leakage current. This is one of the reasons for increasing.

Then, the substrate is put in an electric furnace and nitrogen (N
₂ ) Heat treatment at a temperature of 1050 ° C. for about 2 hours in an atmosphere. As a result, the crystal defects of the polycrystalline silicon film 3 are repaired, and the amorphous portion is also polycrystallized. The heat treatment temperature at this time is appropriately 900 to 1150 ° C., preferably 1000 to 1100 ° C., and particularly preferably 103.
It is 0-1070 degreeC. If it is lower than this range, the effect of repairing crystal defects tends to be weakened, and if it is higher than this range, the surface of the polysilicon film tends to be roughened.

Step 4 (see FIG. 2): A planar type polycrystalline silicon TFT using the polycrystalline silicon film 3 as an active layer is formed. First, the gate insulating film 4 is formed on the polycrystalline silicon film 3. There are a high temperature process and a low temperature process as a method of forming the gate insulating film 4. In the high temperature process, a silicon oxide film as the gate insulating film 4 is formed by a high temperature thermal oxidation method of about 900 to 1050 ° C. In the low temperature process, plasma oxidation method, atmospheric pressure CVD method, reduced pressure CV
600 by D method, plasma CVD method, ECR plasma CVD method, photoexcited CVD method, vapor deposition method, sputtering method, etc.
A silicon oxide film, a silicon nitride film, or the like as the gate insulating film 4 is formed at a low temperature of about ° C.

Next, a gate electrode 5 is formed on the gate insulating film 4 and patterned into a desired shape. Gate electrode 5
Examples include polycrystalline silicon, metal silicide, polycide, refractory metal simple substance, and other metals (aluminum, gold, silver,
Copper, etc.) is used. Then, with self-alignment technology,
Source / drain regions 6 are formed in the polycrystalline silicon film 3 using the gate electrode 5 as a mask. There are a high temperature process and a low temperature process as a method of forming the source / drain region 6. In the high temperature process, high temperature heat treatment is performed after ion implantation of the impurities to activate the impurities. In the low temperature process, ion shower with phosphine (PH ₃ ) and protons (H ⁺ ) is applied to simultaneously perform the implantation and activation of impurities without providing a special heat treatment step.

In the low temperature process, there is also a method of activating the impurities by performing heat treatment at a low temperature of about 600 ° C. for several hours to several tens hours after ion implantation of the impurities. Then, the interlayer insulating film 7 is formed on the entire surface of the device. As the interlayer insulating film 7, a silicon oxide film formed by a CVD method, a plasma CVD method, a photo-excited CVD method, a vapor deposition method, a sputtering method, a silicate glass, a silicon nitride film, or the like is used.

After that, contact holes 7a contacting the source / drain regions 6 are formed in the interlayer insulating film 7 and source / drain electrodes 8 are formed to complete the polycrystalline silicon TFT. As described above, in this embodiment, the quality of the crystal of the polycrystalline silicon film 3 is improved by performing the heat treatment again after the solid phase growth, so that the characteristics of the polycrystalline silicon film are further improved. A high quality polycrystalline silicon film TFT can be formed.

And such a polycrystalline silicon TFT
Is used as a pixel driving element of an active matrix LCD, a leak current is small, so that a writing characteristic and a holding characteristic are good, and a high-quality image can be displayed. Next, a second embodiment embodying the present invention will be described with reference to FIGS. In the present embodiment, the same components as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

Step 1 (see FIG. 3a): Amorphous silicon 2a (film thickness 100Å) containing microcrystals is formed on an insulating substrate (eg, quartz glass) 1. Step 2 (see FIG. 3B): A normal amorphous silicon film 2 (film thickness 400 is formed on the amorphous silicon film 2a containing microcrystals).
Å) form. Step 3 (see FIG. 3c): The amorphous silicon films 2 and 2a are solid-phase grown to form polycrystalline silicon films 3 and 3a.
The solid-phase growth conditions and actions are the same as in the first embodiment. At this time, crystals grow using the microcrystals in the amorphous silicon film 2a as seeds. Therefore, if fine crystals are uniformly present in the amorphous silicon film 2a, the polycrystalline silicon film 3,
The crystal grain size of 3a is substantially uniform over the entire substrate 1.

By adjusting the amount of fine crystals in the amorphous silicon film 2a, the crystal grain size of the polycrystalline silicon films 3 and 3a can be set to a desired size. That is, as the number of microcrystals in the amorphous silicon film 2a increases, the crystal growth occurs more densely, so that the crystal grain size of the polycrystalline silicon films 3 and 3a becomes smaller. The processing temperature of the solid phase growth at this time is 580 to
700 ° C. is suitable, preferably 600-700 ° C.,
Particularly preferably, it is 600 to 650 ° C. If it is lower than this range, the processing time of solid phase growth tends to be significantly long, and if it is higher, the grain size of the polycrystalline silicon films 3 and 3a tends to be smaller.

Further, in order to improve the characteristics of the polycrystalline silicon films 3 and 3a formed as described above, the substrate is placed in an electric furnace and heat treatment is performed as in the first embodiment. As a result, the quality of the polycrystalline silicon films 3 and 3a is improved.
The heat treatment conditions are the same as in the first embodiment. Step 4 (see FIG. 2): Planar type polycrystalline silicon TFT using the polycrystalline silicon films 3 and 3a as active layers
To form.

As described above, according to this embodiment, since the crystal grain sizes of the polycrystalline silicon films 3 and 3a are substantially uniform, the substrate 1
It is possible to form a polycrystalline silicon TFT having no variation in device characteristics over the entire area. In addition, the characteristics as a polycrystalline silicon film are further improved by performing heat treatment again after solid phase growth. And, like the first embodiment, excellent polycrystalline silicon TFT and LCD
Can be provided.

Further, by adjusting the amount of fine crystals in the amorphous silicon film 2a to increase the crystal grain size of the polycrystalline silicon films 3 and 3a, the field effect mobility can be increased. As a result, a polycrystalline silicon TFT having improved device characteristics can be formed over the entire substrate 1, and the image quality can be improved over the entire panel surface of the LCD.

By the way, it is desirable that the thickness of the amorphous silicon film 2a containing microcrystals is 100 Å or less. The solid phase growth of each of the amorphous silicon films 2 and 2a occurs using the microcrystals in the amorphous silicon film 2a as seeds.
a is polycrystallized, then the interfaces between the amorphous silicon films 2 and 2a are polycrystallized, and then polycrystallization proceeds from the lower layer to the upper layer of the amorphous silicon film 2. Therefore, the crystal grain size of the polycrystalline silicon film 3 is larger than that of the polycrystalline silicon film 3a.

Also in the polycrystalline silicon film 3,
The crystal grain size of the upper layer is larger than that of the lower layer. The change in the crystal grain size in the polycrystalline silicon film 3 is continuous at a constant rate, and the degree of change is also very small. Therefore, it can be said that the crystal grain size in the polycrystalline silicon film 3 is almost uniform, and different crystal grain sizes are not mixed as in the conventional solid phase growth method. Therefore, according to the present embodiment, a problem is unlikely to occur if the element characteristics of the polycrystalline silicon TFT vary due to the non-uniform crystal grain size of the polycrystalline silicon film.

Since a polycrystalline silicon film having a small crystal grain size has a low electric field effect mobility, it has poor characteristics as an active layer of a polycrystalline silicon TFT. Therefore, the thinner the amorphous silicon film 2a, the better. However, if the amorphous silicon film 2a is too thin, microcrystals cannot be contained. Therefore, at least 20Å or more is required, and 50Å or more is required to uniformly contain microcrystals. That is, the film thickness of the amorphous silicon film 2a is preferably 20 to 100Å, and particularly preferably 50 to 100Å.

If the active layer is too thick, the off-current of the polycrystalline silicon TFT will increase, and if it is too thin, the on-current will decrease. Therefore, the thickness of the active layer is preferably about 500Å.
Therefore, the total thickness of the polycrystalline silicon films 3 and 3a needs to be about 500 Å, and the required film thickness of each amorphous silicon film 2 and 2a is required. next,
A third embodiment of the present invention will be described with reference to FIGS.

In the present embodiment, the same components as those in the first and second embodiments are designated by the same reference numerals and the description thereof will be omitted. Step 1 (see FIG. 4a): Insulating substrate (eg quartz glass)
A normal amorphous silicon film 2 (thickness: 500 Å) is formed on the surface 1. Step 2 (see FIG. 4B): Amorphous silicon film 2a containing microcrystals (film thickness 100
Å) form.

Step 3 (see FIG. 4c): Amorphous silicon films 2 and 2a are solid-phase grown to form polycrystalline silicon films 3 and 3a.
To form. The solid-phase growth conditions and actions are the same as in the second embodiment. At this time, crystal growth may occur also from the interface between the amorphous silicon film 2 and the substrate 1. However, since the amorphous silicon film 2a contains fine crystals, the crystal growth proceeding from the amorphous silicon film 2a to the amorphous silicon film 2 is dominant.

Step 4 (see FIG. 4d): The upper polycrystalline silicon film 3a is removed and only the lower polycrystalline silicon film 3 is left. As described above, the polycrystalline silicon film 3a is removed more actively than the polycrystalline silicon film 3 because the polycrystalline silicon film 3a obtained by solid phase growth of the amorphous silicon film 2a has a small grain size. This is because the function as a layer is inferior.
At this time, in addition to the polycrystalline silicon film 3a, the surface portion of the polycrystalline silicon film 3 may be removed.

Further, in order to improve the characteristics of the polycrystalline silicon film 3 formed as described above, the substrate is put in an electric furnace and heat-treated as in the above-mentioned embodiment. As a result, the quality of the polycrystalline silicon film 3 is improved. The heat treatment conditions are the same as those in the first and second embodiments. Step 5 (see FIG. 2): A planar type polycrystalline silicon TFT using the polycrystalline silicon film 3 as an active layer is formed.

As described above, according to this embodiment, similarly to the second embodiment, the polycrystalline silicon film 3 having a substantially uniform crystal grain size is used.
Can be obtained. Then, similar to the first and second embodiments, an excellent polycrystalline silicon TFT and LCD can be provided. Next, a fourth embodiment of the present invention
The embodiment will be described with reference to FIGS. 5 and 2. In the present embodiment, the same components as those in the first to third embodiments are designated by the same reference numerals and the description thereof will be omitted.

Step 1 (see FIG. 5a): An ordinary amorphous silicon film 2 (film thickness 9) is formed on an insulating substrate (eg, quartz glass) 1.
00 Å) is formed. Step 2 (see FIG. 5B): Amorphous silicon film 2a containing microcrystals (film thickness 100
Å) form. Step 3 (see FIG. 5c): The amorphous silicon films 2 and 2a are solid-phase grown to form polycrystalline silicon films 3 and 3a.
The solid-phase growth conditions and actions are the same as those in the above-mentioned embodiment.

Further, in order to improve the characteristics of the polycrystalline silicon film 3 formed as described above, the substrate is placed in an electric furnace and heat treated as in the above-mentioned embodiment. As a result, the crystal gap of the polycrystalline silicon film 3 is improved. The conditions of the heat treatment are the same as those in the above-mentioned embodiment. Step 4 (see FIG. 5d): The polycrystalline silicon films 3 and 3a are oxidized by 500 Å from the top (surface) to form a silicon oxide film 9 (thickness 1000 Å).

Step 5 (see FIG. 2): A planar type polycrystalline silicon TFT using the polycrystalline silicon film 3 as an active layer is formed. Here, the silicon oxide film 9 is used as the gate insulating film 4. Therefore, the silicon oxide film 9 may be formed similarly to the gate insulating film 4. As described above, the characteristics of the active layer are inferior because the crystal grain size of the polycrystalline silicon film 3a is small. However, there is no problem when it is once oxidized and used as the gate insulating film 4.

As described above, also in this embodiment, the same effect as that of the third embodiment can be obtained. Next, a fifth embodiment embodying the present invention will be described with reference to FIGS. In this embodiment, the same components as those in the first to fourth embodiments are designated by the same reference numerals, and the description thereof will be omitted.

Step 1 (see FIG. 6a): An amorphous silicon film 2a containing microcrystals on an insulating substrate (eg, quartz glass) 1
(Film thickness 100Å) is formed. Step 2 (see FIG. 6b): In the amorphous silicon film 2a containing microcrystals, unnecessary amorphous silicon film 2a is removed by etching, leaving only the portion 2b corresponding to the channel region of the polycrystalline silicon TFT. Since the amorphous silicon film 2 is thin, the etching method is not limited,
Any method such as a wet etching method, a dry etching method, or a method combining these methods may be used.

A photoresist may be used as the etching mask, and a photomask for patterning the gate electrode 5 may be used as a photomask for patterning the photoresist. Therefore, the number of photomasks does not increase as compared with the first embodiment. Step 3 (see FIG. 6): An amorphous silicon film 2 (film thickness 400Å) is formed on the entire surface of the device.

Step 4 (see FIG. 6): The amorphous silicon films 2 and 2b are solid-phase grown to form polycrystalline silicon films 3 and 3b. The solid-phase growth conditions and actions are the same as those in the above-mentioned embodiment. Further, in order to improve the characteristics of the polycrystalline silicon films 3 and 3b formed as described above, the substrate is placed in an electric furnace and heat treatment is performed as in the above-described embodiment. As a result, the quality of the polycrystalline silicon films 3 and 3b is improved. The conditions of the heat treatment are the same as those in the above-mentioned embodiment.

Step 5 (see FIG. 7): A planar type polycrystalline silicon TFT using the polycrystalline silicon films 3 and 3b as an active layer is formed. Thus, in this embodiment,
The polycrystalline silicon film 3a remains only below the channel region of the polycrystalline silicon TFT, and does not remain below the source / drain region 6. As described above, the amorphous silicon film 2
Since the crystal grain size of the polycrystalline silicon film 3a obtained by solid phase growth of a is small, the characteristics as an active layer are inferior.

However, in the channel region, the current mainly flows in the surface layer portion (that is, the portion of the polycrystalline silicon film 3), so that even if the polycrystalline silicon film 3a remains in the lower portion, the element characteristics of the polycrystalline silicon TFT are affected. Do not receive
On the other hand, since current flows through the source / drain region 6 as a whole, if the polycrystalline silicon film 3b remains in the lower portion, the element characteristics of the polycrystalline silicon TFT are deteriorated. Therefore, if the polycrystalline silicon film 3b is not left under the source / drain regions 6 as in this embodiment, a high-performance polycrystalline silicon TFT can be obtained.

In addition, solid phase growth of the amorphous silicon films 2 and 2b occurs using the microcrystals in the amorphous silicon film 2b as seeds, and the amorphous silicon film 2b is first polycrystallized.
Next, the interface between the amorphous silicon films 2 and 2b is polycrystallized,
Then, polycrystallization progresses in the amorphous silicon film 2. Therefore, in the polycrystalline silicon film 3, the crystal grain size becomes larger at a position farther from the amorphous silicon film 2b,
The change in the crystal grain size is continuous at a constant rate.

However, since the degree of change in the crystal grain size is very small, it can be said that the crystal grain size in the polycrystalline silicon film 3 is almost uniform, which is different from that in the conventional solid phase growth method. The particle sizes are not mixed. Therefore, the source / drain region 6 has a larger crystal grain size than the channel region of the polycrystalline silicon TFT. Since a current flows through the source / drain region 6 as a whole, it is desirable that the crystal grain size is large and the field effect mobility is high. Therefore, by increasing the crystal grain size of the polycrystalline silicon film 3 corresponding to the source / drain regions 6 as in this embodiment, a high-performance polycrystalline silicon TFT can be obtained.

Therefore, such a polycrystalline silicon TFT
Is used as a pixel driving element of an active matrix LCD, a high-performance LCD can be obtained.
In the first to fifth embodiments, the polycrystalline silicon film having a small crystal grain size is inferior to the active layer of the transistor because of its low mobility.
There is no particular problem in using it as a D pixel switching element.

The above embodiment may be modified as follows, and in that case, the same operation and effect can be obtained. 1) In the first embodiment, the reduced pressure CV is applied to the amorphous silicon film.
According to the method D, for example, monosilane gas is used and the temperature is set to 58.
Deposit at 0 ° C. As a result, the amorphous silicon film becomes a film containing microcrystals.

By polycrystallizing the amorphous silicon film containing microcrystals by the solid phase growth method, although the crystal grain size becomes smaller and the mobility is slightly lowered, the crystal growth can be completed in a short time. it can. 2) Instead of heat treatment by an electric furnace, the RTA (Rap
Heat treatment by id thermal annealing) or heat treatment by laser irradiation is performed.

For example, the heat treatment by the RTA method is performed at a temperature of 1
Repeat the anneal at 200 ° C. for 30 seconds 5 times. Also,
The heat treatment by laser irradiation uses a CW Ar ⁺ laser under the conditions of an output of 10 to 15 W and a substrate temperature of 450 ° C.
The irradiation. 3) The amorphous silicon films 2 and 2a are not subjected to the low pressure CVD method or the plasma CVD method, but the atmospheric pressure CVD method, the photoexcited CVD method,
Vapor deposition method, EB (Electron Beam) vapor deposition method, MBE (Molecula
It is formed by any one of a group consisting of r beam epitaxy) method and sputtering method.

4) In the manufacturing process of the polycrystalline silicon TFT, the element characteristics of the polycrystalline silicon TFT are improved by performing the hydrogenation treatment after forming the polycrystalline silicon films 3, 3a and 3b. The hydrogenation treatment is a method in which a hydrogen atom is bonded to a crystal defect portion of a polycrystalline silicon film to reduce defects, stabilize a crystal structure, and enhance an electric field effect mobility.

5) The threshold voltage (Vth) of the polycrystalline silicon TFT is controlled by doping impurities in the portions corresponding to the channel regions of the polycrystalline silicon films 3, 3a and 3b. In the polycrystalline silicon TFT formed by the solid phase growth method, the threshold voltage tends to shift in the depletion direction in the N-channel transistor and the threshold voltage tends to shift in the enhancement direction in the P-channel transistor. Further, when the hydrogenation treatment of the above 4) is performed, the tendency becomes more remarkable. To suppress the shift of the threshold voltage, the channel region may be doped with impurities.

6) Not only the planar type, but also the polycrystalline silicon TFT of any structure such as an inverted planar type, a staggered type and an inverted staggered type. 7) Applicable not only to polycrystalline silicon TFTs but also to insulated gate semiconductor devices in general. In addition, photoelectric conversion elements such as solar cells and optical sensors, bipolar transistors, static induction transistors (SIT: Static Induction Transistor).
It is applied to all semiconductor devices using a polycrystalline silicon film such as r).

8) The insulating substrate is replaced with a ceramic substrate or an insulating layer such as a silicon oxide film, and the present invention is applied to an adhesion image sensor, a three-dimensional IC or the like instead of an LCD. 9) A polycrystalline silicon TFT is used as a load element in a memory cell of a static RAM (SRAM) instead of an LCD.

[0074]

The present invention has the following excellent effects. 1) By improving the film quality of the silicon film polycrystallized by the first heat treatment step by the subsequent second heat treatment step, a high quality polycrystalline silicon film can be provided.

2) A high quality polycrystalline silicon film can be obtained by a simple process. 3) A good quality polycrystalline silicon film can be obtained in a short time. 4) It is possible to provide a semiconductor device provided with an excellent characteristic polycrystalline silicon film having a substantially uniform crystal grain size. 5) The treatment effect in the second heat treatment step can be improved.

6) By setting the thickness of the amorphous silicon film to a range that can be used as an active layer of a transistor from the beginning of deposition, a polycrystalline silicon film is formed and then cut to a desired thickness. Compared with the above, the setting control of the film thickness is easier, and the labor for such processing can be omitted. 7) It is possible to provide an excellent thin film transistor using an excellent polycrystalline silicon film as an active layer.

8) By using an excellent thin film transistor as a pixel driving element, an excellent liquid crystal display can be obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining a manufacturing process of a first embodiment embodying the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing process of first to fourth embodiments embodying the present invention.

FIG. 3 is a cross-sectional view for explaining a manufacturing process of a second embodiment which embodies the present invention.

FIG. 4 is a cross-sectional view for explaining a manufacturing process of a third embodiment which embodies the present invention.

FIG. 5 is a cross-sectional view for explaining a manufacturing process of a fourth embodiment which embodies the present invention.

FIG. 6 is a cross-sectional view for explaining a manufacturing process of a fifth embodiment of the present invention.

FIG. 7 is a sectional view for explaining the manufacturing process for the fifth embodiment.

[Explanation of symbols]

 1 Insulating Substrate 2 First Amorphous Silicon Film 2a, 2b Second Amorphous Silicon Film 3, 3a, 3b Polycrystalline Silicon Film 4 Gate Insulating Film 5 Gate Electrode 6 Source / Drain Region 7 Interlayer Insulating Film 7a Contact Hall 8 Source / drain electrode

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yoshihiro Morimoto 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Kiyoshi Yoneda 2-chome, Keihanhondori, Moriguchi-shi, Osaka No. 5 Sanyo Electric Co., Ltd.

Claims (20)

[Claims] 1. A method of manufacturing a semiconductor device, which comprises polycrystallizing an amorphous silicon film containing no microcrystals by a first heat treatment operation and then performing a second heat treatment operation. 2. A method for manufacturing a semiconductor device, which comprises polycrystallizing an amorphous silicon film containing microcrystals at least partially by a first heat treatment operation, and then performing a second heat treatment operation. 3. A step of forming a first amorphous silicon film containing microcrystals, and containing microcrystals on the first amorphous silicon film as compared to the first amorphous silicon film. A step of forming a second amorphous silicon film having a low proportion or containing no microcrystals, and a first heat treatment operation is applied to the first and second amorphous silicon films to form a polycrystalline silicon film. A method of manufacturing a semiconductor device, comprising: a forming step; and a step of applying a second heat treatment operation to the polycrystalline silicon film. 4. A step of forming a second amorphous silicon film, the second amorphous silicon film having a higher proportion of microcrystals than the second amorphous silicon film. A step of forming a first amorphous silicon film, a step of applying a first heat treatment to the first and second amorphous silicon films to form a polycrystalline silicon film, and A step of applying a second heat treatment work, and a method of manufacturing a semiconductor device. 5. A step of forming a second amorphous silicon film, the second amorphous silicon film having a higher proportion of microcrystals than the second amorphous silicon film. A step of forming a first amorphous silicon film, a step of applying a first heat treatment to the first and second amorphous silicon films to form a polycrystalline silicon film, and A step of applying a second heat treatment, a step of forming a silicon oxide film by oxidizing at least a portion of the polycrystalline silicon film formed by heat-treating the first amorphous silicon film, A method of manufacturing a semiconductor device, comprising: 6. The method of manufacturing a semiconductor device according to claim 3, wherein the first amorphous silicon film is provided on at least a part of the first amorphous silicon film. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the temperature of the second heat treatment step is higher than the temperature of the first heat treatment step. 8. The method of forming a semiconductor device according to claim 7, wherein the time of the second heat treatment step is shorter than that of the first heat treatment step. 9. The total film thickness of the amorphous silicon film before applying the first heat treatment is set within a range usable as an active layer of a transistor. The method for manufacturing a semiconductor device according to claim 1. 10. The semiconductor according to claim 1, wherein the total film thickness of the amorphous silicon film before the first heat treatment is 800 Å or less. Device manufacturing method. 11. A polycrystalline silicon film is formed on a substrate by the method for manufacturing a semiconductor device according to claim 1, and the polycrystalline silicon film is processed as an active layer of a transistor. A method for manufacturing a semiconductor device, comprising: 12. A step of forming a polycrystalline silicon film on an insulating substrate by the method for manufacturing a semiconductor device according to claim 1, and a gate insulating film on the polycrystalline silicon film. And a step of forming a gate electrode on the gate insulating film, and a source region and a drain region are formed in the polycrystalline silicon film by a self-alignment technique using the gate electrode. Method of manufacturing thin film transistor. 13. A step of forming a first amorphous silicon film containing microcrystals on an insulating substrate, and a portion other than the portion corresponding to the channel region in the first amorphous silicon film is left and other portions are left. And a second amorphous silicon film having a smaller percentage of microcrystals than the first amorphous silicon film or no second crystal on the insulating substrate and the first amorphous silicon film. A step of forming an amorphous silicon film; a step of forming a polycrystalline silicon film by applying a first heat treatment to the first and second amorphous silicon films; The step of applying a heat treatment work, the step of forming a gate insulating film on the polycrystalline silicon film, the step of forming a gate electrode on the gate insulating film, and the step of forming the polycrystalline silicon by a self-alignment technique using a gate electrode. Source region on silicon film Method for manufacturing a thin film transistor comprising the steps of: forming a drain region and a. 14. A step of forming a second amorphous silicon film on an insulating substrate, and microcrystals on the second amorphous silicon film as compared with the second amorphous silicon film. A step of forming a first amorphous silicon film having a high content ratio; a step of removing the remaining part of the first amorphous silicon film corresponding to the channel region; And a step of applying a first heat treatment operation to the second amorphous silicon film to form a polycrystalline silicon film, a step of applying a second heat treatment operation to the polycrystalline silicon film, and a step of applying a second heat treatment operation to the polycrystalline silicon film. A step of forming a gate insulating film, a step of forming a gate electrode on the gate insulating film, and a step of forming a source region and a drain region in the polycrystalline silicon film by a self-alignment technique using the gate electrode. Characterized by including A method of manufacturing the thin film transistor was. 15. A step of forming a second amorphous silicon film on an insulating substrate, and including fine crystals on the second amorphous silicon film as compared with the second amorphous silicon film. A step of forming a first amorphous silicon film having a large proportion, a step of removing the remaining portion of the first amorphous silicon film corresponding to the channel region, and the first and second portions. A step of applying a first heat treatment operation to the second amorphous silicon film to form a polycrystalline silicon film; a step of applying a second heat treatment operation to this polycrystalline silicon film; A step of oxidizing at least a portion formed by heat-treating the first amorphous silicon film to form a gate insulating film; a step of forming a gate electrode on the gate insulating film; By the self-alignment technology Method for manufacturing a thin film transistor comprising a step of forming a source region and a drain region in the crystalline silicon film. 16. The temperature of the second heat treatment step is higher than the temperature of the first heat treatment step.
16. The method of manufacturing a thin film transistor according to any one of 2 to 15. 17. The method of manufacturing a thin film transistor according to claim 16, wherein the time of the second heat treatment step is shorter than that of the first heat treatment step. 18. The total film thickness of the amorphous silicon film before the first heat treatment is applied is set within a range usable as an active layer of a transistor. The method of manufacturing a thin film transistor according to any one of items. 19. The thin film transistor according to claim 12, wherein a total film thickness of the amorphous silicon film before the first heat treatment is applied is 800 Å or less. Manufacturing method. 20. A liquid crystal display using a thin film transistor manufactured by the method of manufacturing a thin film transistor according to claim 11 as a pixel driving element.