JPH0896523A - Signal processor - Google Patents

Abstract

PURPOSE: To change equalization characteristics and to obtain the optimum equalization characteristics without injuring quality of an output signal by controlling the characteristics of an equalizing means according to a gate signal synchronized with an input signal. CONSTITUTION: A gate pulse generation circuit 13 discriminates the data in a demodulated singnal by a channel decoder 4, and generates a signal becoming 'H' in a sub-cord part to send it to a CPU 8. The CPU 8 changes a voltage of a control signal sent to an equalizer 3 through a line 9 in a large range in the period in which a gate pulse in the 'H', to change the equalization characteristics of the equalizer 3. At this time, the CPU 8 detects a point on which the number of error flags becomes the least while counting the number of error flags outputted from an error correction circuit 5. Then, the CPU 8 is made to store the value of an optimum equalizer control voltage in a RAM12, and the equalizer 3 is made to operate with the optimum control voltage in an audio part and a video part, and the suitable equalization characteristic is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device,
In particular, it relates to reproduction equalization processing of a digital signal reproduced from a recording medium.

[0002]

2. Description of the Related Art Conventionally, when a signal is transmitted, an equalization process is performed on the receiving side to control the frequency characteristic of the signal based on the transmission system to compensate for the loss and obtain a good signal.

As a transmission device of this type, for example, a digital VTR which records and reproduces a video signal as a digital signal on a magnetic tape is known.
Also in the above, the equalization processing is performed on the reproduced signal.

The equalization processing here is performed by a circuit called an equalizer, and the processing is as follows.

First, at the time of shipment, the frequency characteristics of the gain and phase of the equalizer are adjusted so that the error rate of the reproduced signal (the number of error data after error correction) is minimized by using an equalizer adjusting tape. The set value at that time is stored in the ROM in the apparatus, and the equalizer is adjusted by this set value during actual reproduction.

Also, the user changes the gain of the equalizer in the high frequency band as shown in FIG. 5 based on the error rate in the actual reproduction signal, based on the difference in the recording / reproduction characteristics due to the difference in tape type and manufacturer. Then, as shown in FIG. 6, adjustment is performed by finding the optimum point where the number of error data in the reproduction signal is the minimum.

[0007]

However, in the conventional example as described above, the characteristics of the equalizer must be changed while actually reproducing the video signal and the audio signal,
At both ends of the characteristic change range, the number of data that cannot be error-corrected increases and affects the reproduced image, resulting in deterioration of image quality.

Further, in order to prevent such deterioration of image quality, the range of change in characteristics is narrowed, and it is impossible to escape from the pseudo optimum point such as point b in FIG. 7, and the true optimum point ( There is a problem in that it cannot be adjusted to point a) in FIG.

In view of the above problems, it is an object of the present invention to provide an apparatus capable of obtaining optimum equalization characteristics without affecting the output image signal.

[0010]

SUMMARY OF THE INVENTION In order to solve the problems conventionally held and to achieve the above object, the present invention provides an equalizing means for equalizing an input signal and a gate signal phase-synchronized with the input signal. It is configured to include a gate signal generating means for generating and a control means for changing the equalization characteristic of the equalizing means according to the gate signal.

[0011]

Since the present invention is constructed as described above, the characteristics of the equalizing circuit can always be kept optimum without affecting the output signal.

[0012]

Embodiments of the present invention will be described in detail below with reference to the drawings.

In this embodiment, the case where the present invention is applied to a digital VTR will be described. FIG. 1 is a block diagram showing the structure of a reproducing system of such a digital VTR.

In FIG. 1, the digital signal reproduced from the magnetic tape 1 by the magnetic head 2 is adjusted in gain and phase frequency characteristics by an equalizer 3 as an equalizing circuit and output to a channel decoder 4.

The channel decoder 4 demodulates the equalized signal, the error correction circuit 5 and the gate pulse generation circuit 13
Output to. The error correction circuit 5 corrects error data in the demodulated signal and outputs audio data and video data to the audio reproduction circuit 6 and the video reproduction circuit 7, respectively, and outputs an error flag indicating uncorrectable data to the CPU via the bus 9.
Output to 8.

The audio reproduction circuit 6 and the video reproduction circuit 7 respectively perform predetermined processing on the audio data and the video data after error correction to restore them to the original signal form and output them.

Reference numeral 10 in FIG. 1 is an operation unit for instructing the VTR to perform operations such as recording and reproduction, and 11 is a ROM for storing the above-mentioned equalization characteristic control data at the time of shipment.

Here, the recording format of each data in this embodiment will be described. FIG. 2 is a diagram showing the state of the recording format. As shown in the figure, each data is recorded / reproduced in the order of preamble, audio, video, subcode, and postamble from the beginning on one track. Among them, the preamble and the postamble are repetitive signals called RUNUP pattern, which are constant signals regardless of the contents of audio / video data, and are used to stably generate a clock synchronized with reproduced digital data.

Audio records audio data, video records video data, and subcode records track number information for high-speed cueing. The audio, video, and subcode data are further synchronized with the sync signal (SYN).
C) has a sync block structure composed of a data part such as ID signal, video / audio and a parity part for error correction, and a sync block number is recorded in the ID part. Then, the error correction circuit 5 described above performs error correction processing in units of this sync block.

Next, the adjustment of the equalization characteristic of the equalizer 3 in this embodiment will be described.

In FIG. 1, reference numeral 13 is a gate pulse generation circuit, the output of which controls the characteristics of the equalizer 3.
Supplied to U8.

As described above, the gate pulse generation circuit 13 inputs the signal demodulated by the channel decoder 4, identifies the data in the demodulated signal, and outputs the high-level signal in the sub-code portion as shown in FIG. 3 (a). A level signal is generated and output to the CPU 8.

The CPU 8 positively changes the voltage of the control signal output to the equalizer 3 in a large range as shown in FIG. 3D while the gate pulse is at the high level. By changing the control voltage in this way,
The equalization characteristic of the equalizer 3 can be changed.

At this time, since the number of error flags output from the error correction circuit 5 increases or decreases as shown in FIGS. 3B and 3C, the CPU 8 causes the number of error flags output from the error correction circuit 5. While counting, the point where the number of error flags is the smallest is detected using hill climbing control, wobbling, and the like.

Then, the optimum equalizer control voltage value is stored in the RAM 12, and the equalizer 3 is operated by the control voltage at the optimum point in the audio or video section to obtain an appropriate equalization characteristic. .

At this time, in the subcode portion of the reproduced signal, it is conceivable that proper characteristics cannot be obtained at both ends of the characteristic change range of the equalizer 3 as shown in FIG. 6, and error data may increase. As described above, the track number information for track cueing is recorded in the subcode part, and even if error correction cannot be performed during normal reproduction, it does not affect the reproduced video and audio signals so much.
Playback image quality and sound quality are hardly deteriorated. Also,
Since the content of the subcode data is data that can be easily estimated from the data of the adjacent track, there is no problem.

As described above, in the present embodiment, the equalization characteristic of the equalizer is greatly changed during the period when the subcode data is being reproduced, so that the optimum equalization can be performed without a great influence on the reproduction signal. The characteristics can be obtained.

In the above-described embodiment, the characteristics of the equalizer 3 are changed during the reproduction period of the subcode signal, but as shown in FIG. 4, during the reproduction period of a specific sync block during the reproduction period of video data. It is also possible to change the characteristics of the equalizer.

In this case, even if the error-correctable data increases during this period, it is possible to obtain a good reproduced image by performing interpolation processing in the subsequent stage.

Further, in recent digital VTRs, a method of recording data of a distant portion on the screen in one sync block by a process called shuffling is generally used, and therefore, in a sync block. The error is dispersed on the screen in the reproduced video signal, and the error portion can be made inconspicuous by performing interpolation using the image signal around each error data.

Further, in the above-mentioned embodiment, the case where the gate signal is generated from the output signal of the channel decoder 4 has been described. However, it is sufficient if the specific period in the reproduction signal can be discriminated. (P
You may form based on G).

Further, although the case where the equalizer characteristic of the equalizer is changed has been described in the above embodiment, the present invention is not limited to this and the present invention can be applied to the case where the frequency characteristic of the reproduced signal is controlled. As a method of controlling the frequency characteristic, for example, a method of controlling the resonance frequency characteristic of the head amplifier to compensate for the loss in the transmission system, or the like can be considered.

Further, in the above-mentioned embodiment, the case where the present invention is applied to the digital VTR has been described, but the present invention is not limited to this, and a system for transmitting / recording / reproducing a digital signal, for example, radio waves or optical It is also applicable to communication by means of the like, optical disks, etc., and has the same operation and effect.

[0034]

As is apparent from the above description, in the present invention, the characteristic of the equalizing means is controlled according to the gate signal synchronized with the input signal. By selecting a period without
The equalization characteristic can be changed without deteriorating the quality of the output signal, and the optimum equivalent characteristic can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital VTR as an embodiment of the present invention.

FIG. 2 is a diagram showing a recording format in an embodiment of the present invention.

FIG. 3 is a diagram for explaining control of characteristics of the equalizer in FIG.

FIG. 4 is a diagram for explaining the operation of the gate signal generation circuit in FIG.

FIG. 5 is a diagram showing changes in equalization characteristics in the example of the present invention.

FIG. 6 is a diagram showing changes in equalization characteristics and error data according to an embodiment of the present invention.

FIG. 7 is a diagram showing a change in equalization characteristic and a state of error data according to the embodiment of the present invention.

[Explanation of symbols]

 3 Equalizer 13 Gate signal generation circuit

Claims (9)

[Claims] 1. An equalizing means for equalizing an input signal, a gate signal generating means for generating a gate signal phase-synchronized with the input signal, and an equalizing characteristic of the equalizing means according to the gate signal. A signal processing device comprising: 2. The signal processing apparatus according to claim 1, wherein the equalization means performs equalization processing on the amplitude and phase of the input signal. 3. A reproducing means for reproducing the input signal from a recording medium, and an error detecting means for detecting an error in an output signal of the equalizing means, wherein the equalizing means is based on an output of the error detecting means. The signal processing device according to claim 1, which operates. 4. The control means, during the period indicated by the gate signal, changes the equalization characteristic of the equalization means more greatly than in other periods based on the output of the error detection means. Item 5. The signal processing device according to item 3. 5. The signal processing apparatus according to claim 1, wherein the input signal is a digital signal including at least a video / audio signal section and an additional signal section. 6. The signal processing apparatus according to claim 5, wherein the gate signal generating means generates a gate signal having a period during which the additional signal is input as the gate period. 7. The input signal includes at least a sync block composed of a sync signal and the image signal or audio signal, and the gate signal generation means sets the gate period with the sync block as a minimum unit. The signal processing device according to claim 5. 8. A signal equalization apparatus comprising: an equalization unit for equalizing an input signal; and a unit for changing an equalization characteristic of the equalization unit in a specific period of the input signal more than in other periods. 9. A means for reproducing a signal, a control means for controlling a frequency characteristic of the reproduction signal, and a means for changing a control characteristic of the control means in a specific period of the reproduction signal more than in other periods. A signal processing device comprising: