JPH0888365A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE: To simplify the manufacturing process of a thin film transistor by a method wherein LDD regions and source/drain regions are formed simultaneously in a semiconductor layer. CONSTITUTION: Impurity ions (for instance P<+> , PHx<+> , etc.) 10 are introduced into a semiconductor layer 2 and, with those ions, a pair of heavily-doped source/drain regions 6 and 6 are formed in the semiconductor layer 2 outside a gate insulating film 3 and a pair of lightly-doped LDD regions 9 and 9 are formed in an offset region in the semiconductor layer 2 under the gate insulating layer 3. If the impurity profile characteristics obtained by ion shower doping are utilized, by setting the conditions suitable for the forming of the lightly-doped LDD regions, high impurity concentrations close to the peak value of the impurity concentration can be realized in regions which are to be source/drain regions 6 and 6. With this constitution, the LDD regions 9 and 9 and the source/ drain regions 6 and 6 can be formed simultaneously by one ion shower doping process.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an LDD (Lightly Dope).
The present invention relates to a method of manufacturing a thin film transistor having a d Drain) structure.

[0002]

2. Description of the Related Art Recently, also in a thin film transistor, an LDD structure is used in order to reduce a leak current due to the influence of electric field concentration near the drain. The LDD structure is composed of a relatively low-concentration impurity region, that is, an LDD region formed between a source / drain region of a relatively high-concentration impurity region and a channel.

FIG. 7 shows a source / drain forming process of an n-channel thin film transistor having an LDD structure. The conventional LDD structure is formed by two ion implantation processes. First, as shown in FIG. 7A, a polycrystalline silicon layer 2, a gate insulating film 3, and a gate electrode 4 are formed on an insulating substrate 1, and a resist 5 serving as an ion implantation mask is patterned. . In this state, for example, phosphorus (P) ions 7 are ion-implanted into the polycrystalline silicon layer 2. By this step, high-concentration source / drain regions 6 and 6 are formed in the polycrystalline silicon layer 2.

Next, as shown in FIG. 7B, after the resist 5 is removed, phosphorus ions 8 are implanted again at a dose lower than that of the above-mentioned ion implantation and at an implantation energy capable of penetrating the gate insulating film 3. Then, ions are implanted into the polycrystalline silicon layer 2. As a result, the low-concentration LDD regions 9 are self-aligned with the gate electrode 4 in the polycrystalline silicon layer 2.
9 is formed.

[0005]

However, the conventional LDD structure requires two ion implantation steps as described above. In order to improve the efficiency of the manufacturing process in consideration of mass production, the twice ion implantation process complicates the process and is not preferable. In addition, the thin film transistor used as the switching element of the liquid crystal panel has an LD.
When the D structure is applied, ion implantation must be performed on a liquid crystal panel having a large area as compared with an LSI in which the ion implantation technique is generally used. However, since ion implantation for such a large-area region is performed by scanning, it is difficult to say that this is a suitable method in terms of uniformity and controllability in large-area implantation.

The object of the present invention is to solve the above-mentioned disadvantages,
An object of the present invention is to provide an efficient manufacturing method for an LDD structure of a thin film transistor.

[0007]

In the method of manufacturing a thin film transistor according to the present invention, first, a gate insulating layer and a gate electrode layer narrower than the gate insulating layer are sequentially formed on the surface of the semiconductor layer. After that, the LDD region and the source / drain regions are simultaneously formed in the semiconductor layer by using a non-mass separation type ion doping method.

According to a limited aspect of the present invention, in the ion doping step, the dose amount of the impurity ions and the ion acceleration energy are selected so that the flat band voltage of the thin film transistor is -5V or more and 0V or less. It

[0009]

In the non-mass separation type ion doping method (hereinafter referred to as ion shower doping) used in the method of manufacturing a thin film transistor of the present invention, the impurity profile formed in the substrate is higher than that of the ion implantation method. It utilizes the characteristic that the concentration peak is formed gently. The contents will be described below.

FIG. 2 (a) shows an example of an impurity profile by ion shower, and FIG. 2 (b) shows an example of an impurity profile by ion implantation. Figure 2 (b)
As shown in, the impurity profile formed by ion implantation has a steep distribution in which the concentration distribution sharply changes in the substrate depth direction. Therefore, when the LDD structure is formed by one-time ion implantation, the impurity concentration of the LDD region formed at a deep position from the surface of the gate insulating film is, for example, 10 ¹⁷ to 10 ¹⁸ atoms / cc If the implantation is performed, the impurity concentration of the source / drain regions formed from the surface of the semiconductor layer has a peak formed at a deep position from the surface, and the concentration becomes low near the surface. On the contrary, if the ion implantation is performed so that the impurity concentration near the surface of the source / drain region is near the peak, the impurity concentration in the LDD region becomes too low. As described above, in ion implantation, it is difficult to simultaneously set the impurity concentrations of the source / drain region and the LDD region to be optimum.

However, as shown in FIG.
The impurity profile due to the ion shower has a shape in which the concentration distribution changes gently in the depth direction. Therefore, L formed at a deep position from the gate insulating film
The impurity concentration of the DD region is, for example, 10 ¹⁷ to 10 ¹⁸ atom
Even if the ion shower doping is performed under the condition of s / cc order, a concentration peak can be formed near the surface in the source / drain regions.

As described above, in the doping by the ion shower, the source / drain regions and the LDD regions can be simultaneously formed by utilizing the impurity profile having a gentle shape in the depth direction of the substrate.

In addition, in the doping process using the ion shower, the inventor has obtained the following knowledge. That is, when the LDD structure is formed by using the ion shower doping, a large amount of impurity ions (for example, phosphorus ions) are introduced into the gate insulating film (oxide film), and positive charges are generated. Then, it has been found that this positive charge affects the channel region and becomes a factor of increasing the leak current at the time of off. Such a situation causes a result that conflicts with the effect of reducing the leakage current due to the electric field relaxation of the LDD. Therefore, various studies have been made to suppress the influence of positive charges in the gate insulating film and reduce the leak current while ensuring the impurity concentration of the LDD region necessary for the electric field relaxation. As a result, it has been found that by suppressing the positive charges in the gate insulating film to a certain amount or less, the leak current can be suppressed and the desired ON / OFF ratio of the thin film transistor can be secured. Then, this range was grasped as a range in which the flat band voltage of the transistor was −5 V or higher and 0 V or lower.
Therefore, in the non-mass separation type ion doping step, the acceleration energy and the dose amount of the impurity ions are preferably selected so that the flat band voltage of the thin film transistor is −5 V or higher and 0 V or lower. As a result, it has become possible to reduce the leak current when the transistor is off.

[0014]

Embodiments of the present invention will be described in detail below with reference to the drawings. First, an outline of a manufacturing process of a thin film transistor (for example, an n-channel thin film transistor) according to an embodiment of the present invention will be described with reference to FIG. Then, the step of forming the source / drain having the LDD structure will be described in detail.

First, as shown in FIG. 1A, a CV is formed on the surface of an insulating substrate 1 such as a quartz substrate or a glass substrate.
The semiconductor layer 2 made of a polycrystalline silicon film is formed to a film thickness of 300 to 1000 Å, preferably 60 by a D (chemical vapor reaction) method.
Then, the semiconductor layer 2 is patterned into an island shape by photolithography. Further, the semiconductor layer 2
The surface is thermally oxidized to form a gate insulating film made of a silicon oxide film (SiO ₂ ) with a film thickness of 500 to 2000 Å, preferably 1
Then, 300 Å is formed and patterned by photolithography into an island shape having a width narrower than that of the semiconductor layer 2. The gate insulating film 3 may be formed by using a silicon oxide film, a silicon nitride film, or the like using a CVD method, a sputtering method, or the like.

After that, a polycrystalline silicon film having a film thickness of 1000 to 3000 Å, preferably 2000, is again formed by the CVD method.
Å The gate electrode 4 is deposited and patterned by photolithography, and the gate electrode 4 is narrower than the gate insulating film 3.
To form.

Next, as shown in FIG. 1B, impurity ions (for example, P ⁺ , PH _X ^+, etc.) 10 are introduced into the semiconductor layer 2 by using a non-mass separation type ion doping method. As a result, the semiconductor layer 2 outside the gate insulating film 3
A pair of high-concentration source / drain regions 6 and 6 are formed therein, and low-concentration LDD regions 9 and 9 are formed in the offset region in the semiconductor layer 2 below the gate insulating layer 3. Note that this step will be described later in detail.

Further, as shown in FIG. 1C, hydrogen plasma treatment is performed in order to compensate dangling bonds existing in the polycrystalline silicon film with hydrogen. Then, Figure 1
As shown in (d), a silicon oxide film or a silicon nitride film is deposited to a thickness of 2000 to 5000 Å, preferably 4000 Å by a CVD method to form an interlayer insulating film 11.
Furthermore, the interlayer insulating film 1 is formed by a photolithography process.
Then, the contact hole 12 is formed in the semiconductor device 1, the source electrode 13 and the drain electrode 14 are formed therein, and the manufacturing process of the thin film transistor is completed.

Although the manufacturing process according to the above-described embodiment is a method for manufacturing an n-type thin film transistor, a p-type thin film transistor may be manufactured in the same manner by changing the type of impurities to be doped to boron (B), for example. You can

Here, the non-mass separation type ion doping method shown in FIG. 1B will be described. As described in the "Action" section of this document, the impurity profile by ion shower doping is formed so as to have a gentle distribution in the depth direction as compared with the profile by ion implantation. If such an impurity profile characteristic is used, the source / drain regions 6 and 6 are set by setting the conditions suitable for forming the LDD region having a low impurity concentration.
In the region where the impurity concentration should be 6, it can be formed with a high impurity concentration corresponding to the vicinity of the peak of impurity concentration. Therefore, the LDD regions 9 and 9 and the source / drain regions 6 and 6 can be simultaneously formed by one-time ion shower doping.

As can be seen from FIG. 2A, high-concentration impurity (for example, phosphorus) ions are introduced into the gate insulating film 3 in the offset region. Phosphorus ions in the gate insulating film 3 form a positive charge, induce electrons on the surface of the semiconductor layer 2, and cause a leak current. This becomes clear from the following experimental results.

For example, FIG. 3 shows the relationship between the ion acceleration energy and the dose of phosphorus ions in ion shower doping and the flat band voltage V _{FB of} the thin film transistor manufactured by this method. 3, increased flat band voltage V _FB is As ion acceleration energy dose is increased in the case of constant and flat band voltage V _FB as the dose ion acceleration energy becomes large in the case of constant It has been shown to increase. This indicates that ion shower doping accumulates positive charges in the gate insulating film and increases the flat band voltage. Note that the following equation holds between the flat band voltage V _FB and the charge density Q in the gate insulating film.

Q = C _OX × V _{FB · abs} / q C _OX : capacitance per unit area of the gate insulating film q: charge (1.6E-19 coulomb) V _{FB · abs} : absolute value of V _FB The charge density Q can be calculated from the flat band voltage V _FB using the formula. For example, V _FB = -5V
The charge density Q in the case of, 7.8E11cm ^-2 (C _OX =
2.5E-8).

FIG. 4 shows the relationship between the dose of phosphorus ions and the off current (leakage current) of the thin film transistor. As shown in FIG. 4, the off-current increases as the dose amount increases.

Further, FIG. 5 shows the relationship between the dose amount of the LDD regions 9 and the off current and the on current of the thin film transistor, based on the above various experimental results. In the example shown in the figure, the off-state current increases remarkably in the region where the dose amount in the LDD region exceeds a certain value (approximately 10 ¹³ cm ^-2 ). Therefore, in this area, ON / OFF
The ratio decreases. Further, FIG. 6 shows the relationship between the ion doping conditions and the flat band voltage V _FB in various experiments shown in FIG. From FIGS. 5 and 6, if the conditions of the ion shower doping are set so that the impurity concentration of the LDD regions 9 is within a predetermined range, a thin film transistor having an LDD structure having a desired ON / OFF ratio can be manufactured. it can. For example, in order to obtain a thin film transistor having an ON / OFF ratio of 10 ⁸ or more, it has been found that a condition that the flat band voltage V _FB of the thin film transistor is −5 V or more and 0 V or less may be selected. Therefore, a thin film transistor having a desired ON / OFF ratio can be manufactured by selecting the values of the ion acceleration energy and the dose amount using the relationship shown in FIG. 3 or FIG. 4, for example.

The conditions of the ion shower doping found in the above embodiment are ON / OF in the switching thin film transistor used in the liquid crystal panel.
This is suitable when it is necessary to secure the F ratio of 10 ⁸ or more. Therefore, if the characteristic values required for the thin film transistors are different, it goes without saying that the conditions of the dose amount and the acceleration energy of the ion shower doping corresponding to them may be appropriately set.

Although the method of manufacturing the thin film transistor having the LDD structure has been described in the above embodiments, the non-mass separation type ion doping method can also be used for the method of manufacturing the thin film transistor having the offset structure. . In this case, similarly to the above-mentioned embodiment, preferably, the acceleration energy or dose amount of the ion shower doping that the flat band voltage is in the range of −5 V to 0 V is selected to reduce the phosphorus concentration in the gate insulating film in the offset region. As a result, the off current can be reduced.

[0028]

As described above, in the method of manufacturing a thin film transistor according to the present invention, the high concentration region of the source / drain region and the L region are formed by using the non-mass separation type ion doping.
Since the DD region and the DD region are formed at the same time, the manufacturing process of the thin film transistor is simplified and the manufacturing efficiency is improved. Further, by selecting the acceleration energy and dose amount of the ion shower doping to reduce the positive charges in the gate insulating film in the offset region, it is possible to reduce the off current and obtain a high ON / OFF ratio. it can.

[Brief description of drawings]

FIG. 1 is a cross-sectional structural view showing steps (a) to (d) of a manufacturing process of a thin film transistor according to an embodiment of the present invention.

FIG. 2 is an impurity profile by ion shower doping (a) and ion implantation (b).

FIG. 3 is a dose amount in ion shower doping,
The correlation diagram which shows the relationship between ion acceleration energy and flat band voltage _VFB .

FIG. 4 is a correlation diagram showing a relationship between a dose amount and an off current of a thin film transistor in ion shower doping.

FIG. 5 is a correlation diagram showing a relationship between a dose amount of an LDD region and an off current and an on current of a thin film transistor.

6 is a correlation diagram showing the relationship between the conditions of the experimental data in FIG. 5 and the flat band voltage.

FIG. 7 is a sectional structural view showing two ion implantation steps (a) and (b) used in a conventional method of manufacturing a thin film transistor.

[Explanation of symbols]

 1 ... Insulating substrate 2 ... Semiconductor layer 3 ... Gate insulating film 4 ... Gate electrode 6 ... Source / drain region 9 ... LDD region

Claims (2)

[Claims] 1. A method of manufacturing a thin film transistor having an LDD region and a source / drain region, which comprises sequentially forming a gate insulating layer and a gate electrode layer narrower than the gate insulating layer on a surface of a semiconductor layer. And a step of simultaneously forming the LDD region and the source / drain regions in the semiconductor layer by using a non-mass separation type ion doping method. 2. In the ion doping step,
The method of manufacturing a thin film transistor according to claim 1, wherein the dose amount of the impurity ions and the ion acceleration energy are selected such that the flat band voltage of the thin film transistor is −5 V or higher and 0 V or lower.