JPH0888353A - Field effect transistor - Google Patents

Abstract

PURPOSE: To suppress a device parasitic effect caused by the trap in the boundary between an epitaxial layer and a semi-insulating substrate. CONSTITUTION: In a field effect transistor which is formed on a semi-insulating compound semiconductor substrate by the epitaxial growth, the region of the epitaxial layer which touches the semi-insulating substrate 11 is composed of a semiconductor layer 13 whose conductivity type is opposite to the type of an active layer. The impurity concentration of that region is not less than 1×10<17> cm<-3> and the thickness of that region is good enough to deplete the region completely.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to the structure of field effect transistors.

[0002]

2. Description of the Related Art A compound semiconductor field effect transistor (FET) using gallium arsenide or the like is characterized by higher electron mobility than silicon, and has low power consumption and high speed I.
It has been applied to C and microwave devices. The high performance of such compound semiconductor field effect transistors is due to the molecular beam epitaxy (MBE) method and the metal organic chemical vapor deposition (MOC) method.
This is largely due to the improvement of crystal technology such as the VD) method.

Incidentally, the epitaxial layer / semi-insulating substrate regrowth interface is often contaminated with impurities such as oxygen and carbon, and it is known that its cleaning is difficult. Of these impurities, oxygen and the like form deep levels in the semiconductor and cause device parasitic effects such as frequency dispersion of drain conductance and drain lag.
Conventionally, as one means for suppressing such a phenomenon, a technique of providing a p-type buffer layer (assuming an n-channel) under the channel layer has been used.

FIG. 5 is a crystal structure diagram of a conventional heterojunction field effect transistor (HJFET) having a p-type buffer layer. In FIG. 5, 51 is a semi-insulating GaAs substrate, 53 is a p-type GaAs layer forming a buffer layer, 54 is an undoped GaAs layer forming a carrier transit layer, and 55 is an n ⁺ -Al _0.2 Ga _0.8 As layer forming a carrier supply layer. Is. A gate electrode 59 is formed in contact with 55.

[0005]

When a p-type buffer layer is introduced, it is usually necessary to completely deplete holes.
The impurity concentration and thickness are determined. This is because the presence of the neutral p region increases the parasitic capacitance, which may deteriorate the original operating speed of the device. That is, there are restrictions on the impurity concentration and thickness of the p-type buffer layer, and
Simply introducing the p-type layer into the buffer region does not work effectively for suppressing the interface trap effect.

An object of the present invention is to provide a field effect transistor having a structure in which a p-type layer is introduced in the most efficient region with an effective impurity concentration and a thickness for suppressing the interface trap effect. is there.

[0007]

According to the present invention, in a field effect transistor formed on a semi-insulating compound semiconductor substrate by epitaxial growth, the region of the epitaxial layer in contact with the semi-insulating substrate has a conductivity opposite to that of the active layer. Type semiconductor layer, and has an impurity concentration of 1 × 10
It is characterized in that the thickness is ¹⁷ cm ⁻³ or more and the thickness is completely depleted.

The above-mentioned conventional example is an n-channel FE.
T is assumed, and an n-channel FET is also assumed in the following description. However, in the case of the p-channel FET, the same argument can be made by only inverting the sign of the charge.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of the field effect transistor of the present invention. Semi-insulating GaAs substrate 1
1, a p-type GaAs layer 13, an undoped GaAs layer 14, by a molecular beam epitaxy method or a metal organic chemical vapor deposition method,
An n ⁺ -Al _0.2 Ga _0.8 As layer 15 and an n ⁺ -GaAs layer 16 are sequentially formed.

For example, it has the following structure.

Composition Impurity (cm ⁻³ ) Thickness (nm) 16 GaAs 3e18 (n) 80 15 Al _0.2 Ga _0.8 As 2e18 (n) 65 14 GaAs undoped 500 13 GaAs 1e18 (p) 10 11 semi-insulating GaAs substrate 13 is the p-type layer introduced by the present invention.

On this semiconductor substrate, a source electrode 17 and a drain electrode 18 are formed by using, for example, gold germanium / nickel / gold, and a gate electrode 19 is formed by using, for example, tungsten silicide by a conventional technique. ing.

In this embodiment, AlGaAs / GaA is used.
Although it is an s-based HJFET, the present invention is also applicable to a GaAs MESFET formed by epitaxial growth.

Next, the operation of this embodiment will be described.

FIG. 2 is an energy band diagram of this embodiment, and FIG. 3 is a diagram showing the impurity concentration and thickness range of the p-type layer of this embodiment. In FIG. 2, by providing the p-type layer 23 in the region in contact with the semi-insulating substrate 21, the Fermi level pinned by the interface trap is separated from the interface level, and the interface trap is always depleted. . At this time, the interface traps can be considered as merely fixed charges, and device parasitic effects such as frequency dispersion do not occur. The concentration and thickness of the p-type layer are higher than the surface density of the interface trap and are determined under the condition that the p-type layer is completely depleted. In the shaded area shown in FIG. 3, the surface density of the interface trap is 5 × 10 ¹¹ cm ² or less, and the effect of the deep level at the energy depth of the interface trap deeper than 0.4 eV from the conduction band is eliminated. This is the region of the impurity concentration and thickness of the p-type layer. These are typical values of interface traps, and from FIG. 3, interface traps that can be expected if the conditions of the p-type layer are set such that the impurity concentration is 1 × 10 ¹⁷ cm ⁻³ or more and complete depletion is set. The effect of can be removed.

FIG. 4 is a diagram showing the effect of this embodiment by comparing this embodiment with the conventional example. FIG. 4 compares the transient response of the drain current when the drain voltage is changed stepwise. In the conventional example, a large fluctuation of the drain current, which is considered to be due to the response of the interface trap, is observed, but in the present example, the response of the interface trap disappears, and only a slight variation due to the substrate trap remains.

[0018]

As described above, according to the present invention, in the region of the epitaxial layer which is in contact with the semi-insulating substrate, the impurity concentration is 1 × 10 ¹⁷ cm ⁻³ or more and the p thickness is such that it is completely depleted.
The introduction of the mold layer has an effect that the device parasitic effect due to the trap at the interface between the epitaxial layer and the semi-insulating substrate can be suppressed.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a heterojunction field effect transistor of the present invention.

FIG. 2 is an energy band diagram of this example.

FIG. 3 is a diagram showing an impurity concentration and a thickness range of a p-type layer of the present embodiment.

FIG. 4 is a diagram for explaining the effect of the present embodiment on the interface trap effect.

FIG. 5 is a cross-sectional view of a conventional heterojunction field effect transistor.

[Explanation of symbols]

11, 21, 51 Semi-insulating GaAs substrate 13, 23, 53 p-type GaAs buffer layer 52 undoped GaAs buffer layer 14, 24, 54 undoped GaAs electron transit layer 15, 25, 55 n ⁺ -Al _0.2 Ga _0.8 As electron supply Layer 16,56 n ⁺ -GaAs cap layer 17,57 Source electrode 18,58 Drain electrode 19,59 Gate electrode

Claims (3)

[Claims] 1. A field effect transistor formed by epitaxial growth on a semi-insulating compound semiconductor substrate, wherein a region of the epitaxial layer in contact with the semi-insulating substrate is formed of a semiconductor layer having a conductivity type opposite to that of the active layer. The field effect transistor is characterized in that its impurity concentration is 1 × 10 ¹⁷ cm ⁻³ or more and the thickness is completely depleted. 2. In a heterojunction field effect transistor formed by epitaxial growth on a semi-insulating compound semiconductor substrate, a region of the epitaxial layer in contact with the semi-insulating substrate is a semiconductor layer having a conductivity type opposite to that of the active layer. A heterojunction field effect transistor which is formed, has an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or more, and has a thickness such that it is completely depleted. 3. In a GaAs Schottky gate field effect transistor formed by epitaxial growth on a semi-insulating compound semiconductor substrate, a region of the epitaxial layer in contact with the semi-insulating substrate is a semiconductor layer having a conductivity type opposite to that of the active layer. Formed, and the impurity concentration is 1 × 10 ¹⁷
A GaAs Schottky gate field effect transistor characterized by having a thickness of not less than cm ⁻³ and completely depleted.