JPH0888285A - Non-voltage semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE: To obtain a non-volatile semiconductor memory device in which the drop of a program voltage and the microminiaturization of a cell are compatible by forming a floating gate via a tunnel insulating film on protrusion element forming regions divided by the parallel grooves of the main surface of a semiconductor substrate and rounded at an upper edge. CONSTITUTION: A plurality of grooves 12 are formed in parallel on the surface of a semiconductor substrate 11, and an embedded insulating film 13 is embedded to the midway of the grooves 12. The substrate part protruding without being embedded by the film 13 is an element forming region 14, and the upper edge of the region 14 is rounded. A floating gate 16 is formed via a tunnel insulating film 15 on the region 14. The gate 16 is isolated with each element forming region in a direction perpendicular to the groove 12, and isolated at a predetermined interval in the direction parallel with the groove 12. A control gate 18 is formed on the gate 16 via a gate insulating film 17. The gate 18 is so formed as to be extended in the direction perpendicular to the groove 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device having an improved memory cell structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices have been increasing in concentration, and research and development of finer memory devices have been actively conducted. For example, among various semiconductor memory devices, a nonvolatile semiconductor memory device (EEPROM) in which a floating gate and a control gate are stacked on a semiconductor substrate and data is rewritten by exchanging charges between the floating gate and the substrate is a hard disk device. It is expected as a substitute, and higher integration is desired.

This EEPROM has a special structure in which a floating gate and a control gate which are not found in other semiconductor memory devices are laminated, and the voltage applied between the floating gate and the substrate is expressed as follows. be able to.

Vox = Cono / (Cox + Cono) Vpp (1) Cono: capacitance with respect to gate oxide film (interpoly insulating film) Cox: capacitance with respect to tunnel oxide film Vpp: voltage applied to control gate during writing Vox: tunnel oxidation Voltage Applied to Membrane Here, in order to function as a memory element of the EEPROM, it is necessary to sufficiently increase the above capacitances Cox and Cono. Further, in the above formula (1), Cono / (Cox
+ Cono) is a coupling constant, and by increasing this coupling constant, a low Vpp voltage can be realized. Therefore, it is necessary to increase the Cono for Cox.

However, it has been difficult to increase the coupling constant due to structural restrictions, as Cono and Cox become smaller as the device is miniaturized and highly integrated.

[0006]

As described above, in the conventional nonvolatile semiconductor memory device, in the structure in which the floating gate is formed separately, it is extremely difficult to achieve both reduction of the program voltage and miniaturization of the cell. It was

The present invention has been made in consideration of the above circumstances, and an object thereof is to obtain a C
(EN) Provided are a non-volatile semiconductor memory device capable of sufficiently increasing ono and Cox and a coupling constant, and achieving both reduction of program voltage and miniaturization of cells, and a manufacturing method thereof. To do.

[0008]

In order to solve the above problems, the present invention employs the following configurations.

That is, the present invention is a nonvolatile semiconductor memory device in which a floating gate and a control gate are stacked on a semiconductor substrate, and data is rewritten by exchanging charges between the floating gate and the substrate. A convex element forming region which is formed and is separated by a plurality of grooves arranged in parallel to each other and whose upper edge is rounded; and a floating gate formed on these element forming regions through a tunnel insulating film. And a control gate formed on these floating gates with a gate insulating film interposed therebetween and extending in a direction intersecting with the trench.

According to the present invention, in the method for manufacturing a nonvolatile semiconductor memory device having the above structure, a step of selectively etching a main surface of a semiconductor substrate to form a plurality of grooves, and an element formation region separated by the grooves are formed. Rounding the top edge,
A step of partially filling the trench with an insulating film; a step of forming a floating gate on the element formation region of the semiconductor substrate protruding above the buried insulating film via a tunnel insulating film; and a gate on the floating gate and the insulating film. And a step of forming a control gate via an insulating film.

[0011]

According to the present invention, the area of both the tunnel insulating film and the gate insulating film can be increased by rounding the substrate portion which becomes the element forming region, and Cono and Cox can be made sufficiently large. Further, by rounding the substrate part, the area ratio of the gate insulating film to the tunnel insulating film is increased and the coupling constant is also increased by utilizing the difference in radius of curvature between the tunnel insulating film and the gate insulating film with respect to the upper end of the semiconductor. You can As a result, the voltage Vpp during programming can be reduced. For example, the coupling ratio can be increased by about 10% compared to the conventional one, and the voltage during programming can be reduced by about 10%.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 shows an EE according to the first embodiment of the present invention.
FIG. 2A is a plan view showing the configuration of the memory cell portion of the PROM.
3B is a sectional view taken along the lines AA ′ and BB ′ of FIG. 1, respectively.

A plurality of grooves 12 are formed in parallel on the surface of a p-well (semiconductor substrate) 11 formed on an n-type Si substrate (not shown), and CVD-SiO is formed up to the middle of the grooves 12.
_Two films (buried insulating film) 13 are buried. The protruding substrate portion that is not filled with the insulating film 13 is the element forming region 14, and the upper edge of the element forming region 14 is rounded.

A floating gate 16 is formed on the element forming region 14 with a tunnel oxide film (tunnel insulating film) 15 interposed therebetween. The floating gate 16 is separated for each element formation region in the direction orthogonal to the groove, and is separated at a predetermined interval in the direction parallel to the groove 12. A control gate 18 is formed on the floating gate 16 via a gate oxide film (gate insulating film) 17. This control gate 1
8 is formed to extend in a direction orthogonal to the groove 12. A source / drain diffusion layer 19 is formed on the substrate between the gates 16 and 18. Then, the CVD-SiO ₂ film 20 as a protective film is formed on the substrate on which these are formed.
Are formed.

Next, the method of manufacturing the device of this embodiment will be described.
This will be described with reference to FIGS.

First, as shown in FIG. 3A, a p-type Si substrate (having a p-type well formed on an n-type Si substrate) 11 having, for example, a plane orientation (100) and a specific resistance of 5 to 50 Ωcm is prepared. To do. As a mask layer, a SiO ₂ film 31 of 100 nm is deposited on the Si substrate 11 by, for example, an atmospheric pressure CVD method.

Subsequently, a resist pattern (not shown) is selectively formed by photolithography, and the resist pattern is used as a mask for CVD-
After etching the SiO ₂ film 31 by, for example, RIE, the resist pattern is removed by an asher and H ₂ SO ₄
Strip with a solution of + H ₂ O ₂ . Further, using the mask layer 31, the groove 12 is formed on the Si substrate 11. Here, as a method of forming the groove 12, for example, Si-RIE is used to form a trench having a width of 0.4 μm and a depth of about 0.5 μm.

Then, as shown in FIG. 3B, the CVD-SiO ₂ film 31 is formed by using, for example, ammonium fluoride.
After etching, the corners of the trench are rounded using, for example, the CDE method so that the upper end of the trench is completely rounded. Then, a buffer oxide film 32 is formed on the Si substrate 11 to a thickness of about 25 nm by a thermal oxidation process, and a poly-Si film 33 is deposited thereon.

Next, as shown in FIG. 3C, a trench-embedded CVD-SiO ₂ film 13 is formed, for example, 1000
Deposit about nm. Then, as shown in FIG.
The D-SiO ₂ film 13 is etched back so that the Si substrate 11 is exposed, for example, up to about 200 nm from the upper end of the trench. At this time, it is important that the trench sidewall is exposed. Then, the poly-Si film 33 is oxidized to form a SiO ₂ film 33 '.

Next, as shown in FIG. 4E, the oxide films 33 'and 32 are removed by wet etching to expose the element forming region 14. After that, preferably an annealing step or the like is performed, and a crystal defect recovery step of the Si substrate 11 is performed
After further cleaning treatment, a tunnel oxide film 15 is formed as shown in FIG. After that, as shown in FIG. 4G, a poly-Si film 16 to be a floating gate is deposited, and P (phosphorus) is diffused in the poly-Si film 16.

Next, as shown in FIG. 5H, a resist pattern 35 is formed for forming a floating gate, and the poly-Si film 16 is etched by using this as a mask, for example, by RIE. After that, as shown in FIG. 5I, the resist pattern 35 is peeled off. Here, in order to round the edges of the poly-Si film 16, the poly-Si film 16 may be partially etched by, for example, CDE.

Next, as shown in FIG. 5 (j), after forming a gate oxide film 17 on the entire surface, a poly-Si film 18 serving as a control gate is deposited to complete the formation of the cell portion. In addition,
The poly-Si film 18 is patterned in a direction orthogonal to the groove 12, and at the same time, the poly-Si film 16 is also patterned. Then, the source / drain diffusion layers 19 are formed by ion implantation or the like using the poly-Si films 18 and 16 as masks.

In the memory cell structure thus obtained, since the substrate portion which becomes the element formation region 14 is rounded, the areas of both the tunnel oxide film 15 and the gate oxide film 17 can be increased, and the respective oxide films 15, The capacitances Cox and Cono for 17 can be made sufficiently large. Further, the tunnel oxide film 15 is formed by rolling the substrate portion.
By utilizing the difference in the radius of curvature between the gate oxide film 17 and the upper end of the semiconductor, the area ratio of the gate oxide film 17 to the tunnel oxide film 15 can be increased, and the coupling constant can also be increased. As a result, for example, the coupling ratio can be increased by about 10% as compared with the conventional one, and the voltage Vpp during programming can be reduced by about 10%. In other words, even if the cell is miniaturized, Cono and Cox can be made sufficiently large and the coupling constant can be made large, so that it is possible to achieve both the reduction of the program voltage and the miniaturization of the cell. Becomes (Embodiment 2) FIGS. 6 to 9 are sectional views showing a manufacturing process of an EEPROM according to a second embodiment of the present invention. The same parts as those in FIGS. 3 to 5 are designated by the same reference numerals, and detailed description thereof will be omitted.

The conditions for the Si substrate are the same as in the first embodiment. First, as shown in FIG. 6A, a SiO ₂ film 37 is formed on the Si substrate 11 by a thermal oxidation process to have a thickness of, for example, about 25 nm. Further, as the first mask layer 38, for example, polycrystalline Si is deposited to a thickness of about 400 nm, and as the second mask layer 39, for example, a CVD-SiO ₂ film is deposited to a thickness of about 350 nm.

Next, a resist pattern (not shown) is selectively formed by photolithography, the second mask layer 39 is etched by RIE using this as a mask, and then the resist film is removed by, for example, asher + SH. . continue,
Using the second mask layer 39 as a mask, the first mask layer 38 and the thermal oxide film 37 formed on the Si substrate 11 are etched by, for example, RIE. Furthermore, using the mask layers 38 and 39 selectively left on the Si substrate 11 as a mask,
For example, a trench 1 is formed in the Si substrate 11 by the RIE method.
Form 2

Next, as shown in FIG. 6B, a buried CVD-SiO ₂ film 13 is deposited to 1000 nm. Subsequently, as shown in FIG. 6C, Si is formed using RIE or the like.
The O ₂ film 13 is etched back. At this time, it is important that the trench sidewall is exposed, for example, by about 100 nm.

Then, as shown in FIG.
_{2. A} material that can be selectively etched with respect to ₂ and poly-Si, such as a silicon nitride (Si ₃ N ₄ ) film 41
Is deposited to a thickness of 100 nm, and a substance capable of being selectively etched with respect to the Si ₃ N ₄ film 41, for example, a SiO ₂ film 42 is deposited to a thickness of about 500 nm.

Next, as shown in FIG. 7E, the deposited SiO ₂ film 42 is etched back by using, for example, RIE. At this time, about 10 from the upper end of the Si ₃ N ₄ film 41
It is important to overetch 0 nm. Then, as shown in FIG. _{7 (f), Si 3 N} 4 etching the film 41 for example, RIE or the like, Si ₃ N ₄ film 41 deposited on the first mask layer 38 (poly Si) and on the trench side walls
Is removed.

Next, as shown in FIG. 8G, after removing the first mask layer 38 (poly-Si) by, for example, Si-RIE, the thermal oxide film 37 formed on the Si substrate 11 is removed.
Are removed by, for example, ammonium fluoride, and the Si substrate 11
To expose. Then, Si-CDE is performed to round the edges generated during the trench-RIE process. At this time, it is important that the upper end of the trench be completely rounded.

Then, as shown in FIG. 8 (h), in order to remove contamination, buffer oxidation is performed to remove the buffer oxide film 4
3 is formed. Then, wet etching is performed to remove the buffer oxide film 43. Next, as shown in FIG. 8I, a tunnel oxide film 15 is formed by thermal oxidation,
Further, as shown in FIG. 8J, a floating gate forming poly-Si film 16 is deposited.

Then, as shown in FIG. 9 (h), poly S
After the i film 16 is flattened and the upper end surface of the CVD-SiO ₂ film 42 is exposed, the CVD-SiO ₂ film 42 and the SiN film 4 are formed by, for example, CDE, as shown in FIG.
1 is removed to form a slit in the first poly-Si film.
Since this process can be performed in a self-aligning manner with respect to the trench, even minute slits can be formed.

Next, as shown in FIG. 9 (m), after forming the gate oxide film 17, a poly-Si film 18 to be a control gate is deposited to complete the cell portion forming step. Incidentally, the subsequent patterning of the poly-Si films 18 and 16 and the formation of the source / drain diffusion layer 19 may be performed in the same manner as in the first embodiment.

As described above, according to the present embodiment, the capacitances Cox and Cono for the tunnel oxide film 15 and the gate oxide film 17 can be made sufficiently large as in the first embodiment, and further, for the tunnel oxide film 15. Gate oxide film 1
7 and the coupling constant can be increased. Therefore, the same effect as that of the first embodiment can be obtained. Further, in the present embodiment, the floating gate 16 can be processed by self-alignment in the direction orthogonal to the groove 12, which is more effective in miniaturizing the cell. (Embodiment 3) FIGS. 10 and 11 are sectional views showing the steps of manufacturing an EEPROM according to the third embodiment of the present invention. The same parts as those in FIGS. 3 to 5 are designated by the same reference numerals, and detailed description thereof will be omitted.

The process up to the trench filling etch back process is the same as in the first embodiment. After that, the poly-Si film that is the first mask layer 38 is removed by, for example, RIE, and the thermal oxide film 37 formed on the Si substrate 11 is removed by NH ₄ F or the like. This state is shown in FIG.

Then, as shown in FIG.
-CDE and round the shoulders of the trench. At this time, it is important that the upper end of the trench be completely rounded. After that, annealing and oxidation for crystal recovery are performed. Next, as shown in FIG. 10C, the buffer oxide film 43 is etched with ammonium fluoride, and then a cleaning process is performed.

Next, as shown in FIG. 11 (d), a tunnel oxide film 15 is formed by thermal oxidation, and poly-Si is further formed.
The film 16 is deposited to diffuse P (phosphorus). Then
As shown in FIG. 11E, a resist pattern (not shown) is selectively formed for forming the floating gate, and the poly-Si film 16 is etched by, for example, RIE using this as a mask, and then the resist is peeled off. .

Next, as shown in FIG. 11F, after forming a gate oxide film 17, poly-Si which will become a control gate is formed.
The film 18 is deposited to complete the formation of the cell portion. Incidentally, the subsequent patterning of the poly-Si films 18 and 16 and the formation of the source / drain diffusion layer 19 may be performed in the same manner as in the first embodiment.

Also in this embodiment, the capacitances Cox, Con for the tunnel oxide film 15 and the gate oxide film 17 are provided.
can be made sufficiently large, and the area ratio of the gate oxide film 17 to the tunnel oxide film 15 can be increased,
The coupling constant can also be increased. Therefore,
The same effect as the first embodiment can be obtained.

The present invention is not limited to the above embodiments. In the embodiment, the poly-Si film is used as the material of the floating gate and the control gate, but the material is not limited to this, and silicide, another semiconductor, or metal may be used. Further, the material of the tunnel insulating film and the gate insulating film is not limited to the oxide film, but can be changed appropriately according to the specifications. Further, the shape of the element formation region is not limited to that shown in the embodiment, and any element formation region that is separated by the groove and protruded may be rounded. Further, the manufacturing process is not limited to the method shown in the embodiment, and can be changed appropriately according to the specifications. In addition, various modifications can be made without departing from the scope of the present invention.

[0040]

As described above in detail, according to the present invention, the area of both the tunnel insulating film and the gate insulating film is increased by rounding the substrate portion which becomes the element forming region, and the Con
o and Cox can be made sufficiently large, and the area ratio of the gate insulating film to the tunnel insulating film can be increased to increase the coupling constant. Therefore,
Even if the cell is miniaturized, Cono and Cox can be sufficiently increased, the coupling constant can be increased, and a low programming voltage and miniaturization of the cell can be achieved at the same time. And the manufacturing method thereof can be realized.

[Brief description of drawings]

FIG. 1 is a plan view showing a memory cell configuration of an EEPROM according to a first embodiment.

FIG. 2 is a sectional view taken along the line AA ′, BB ′ of FIG.

FIG. 3 is a sectional view showing a manufacturing process of the device of the first example.

FIG. 4 is a cross-sectional view showing the manufacturing process of the device of the first example.

FIG. 5 is a cross-sectional view showing the manufacturing process of the device of the first example.

FIG. 6 is a cross-sectional view showing the manufacturing process of the EEPROM according to the second embodiment.

FIG. 7 is a cross-sectional view showing the manufacturing process of the EEPROM according to the second embodiment.

FIG. 8 is a cross-sectional view showing the manufacturing process of the EEPROM according to the second embodiment.

FIG. 9 is a cross-sectional view showing the manufacturing process of the EEPROM according to the second embodiment.

FIG. 10 is a cross-sectional view showing the manufacturing process of the EEPROM according to the third embodiment.

FIG. 11 is a cross-sectional view showing the manufacturing process of the EEPROM according to the third embodiment.

[Explanation of symbols]

11 ... P-well (Si substrate) 12 ... Trench (trench) 13 ... CVD-SiO ₂ film (buried insulating film) 14 ... Element forming region 15 ... Tunnel oxide film (tunnel insulating film) 16 ... Poly Si film (floating gate) 17 ... Gate oxide film (gate insulating film) 18 ... Poly Si film (control gate) 19 ... Source / drain diffusion layer 20 ... CVD-SiO ₂ film (protective film)

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[Procedure amendment]

[Submission date] April 5, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Title of invention

[Correction method] Change

[Correction content]

Non-volatile semiconductor memory device and manufacturing method thereof

Claims (2)

[Claims] 1. A convex element formation region, which is formed on a main surface of a semiconductor substrate and is separated by a plurality of grooves arranged in parallel with each other, and has a rounded upper edge, and a tunnel on the element formation region. A floating gate formed through an insulating film,
A nonvolatile semiconductor memory device comprising: a control gate formed on the floating gate via a gate insulating film and extending in a direction intersecting with the groove. 2. A method for manufacturing a nonvolatile semiconductor memory device, comprising: stacking a floating gate and a control gate on a semiconductor substrate; and rewriting data by exchanging charges between the floating gate and the substrate. A step of selectively etching to form a plurality of trenches; a step of rounding the upper edge of the element formation region separated by the trenches; a step of partially filling the trenches with an insulating film; and a step above the buried insulating film. A step of forming a floating gate on the element formation region of the semiconductor substrate protruding from above through a tunnel insulating film, and a step of forming a control gate on the floating gate and the buried insulating film through a gate insulating film. A method for manufacturing a non-volatile semiconductor memory device, comprising: