JPH0887453A - Cache memory device, method for controlling resistration of cache memory device, and computer - Google Patents

Abstract

PURPOSE: To provide the cache memory device which is improved in the hit rate of a cache. CONSTITUTION: The cache memory device has data registered for data transfer between a CPU 28 and a main memory 29, and fetches data read out of the main memory 29 and they are replaced with other registered data in read mode when the read data are already registered. This device is equipped with storage means 4 and 5 which stores replacement inhibition areas of addresses, a decision circuit 6 which decides whether or not the address of data to be read or registered is included in the replacement inhibition area, and a replacement inhibition bit 23a which stores the decision result of the decision circuit 6 as to the data to be registered; when data are read out, the replacement is executed or inhibited according to the decision result of the decision circuit 6 as to the data to be read and the storage contents of the replacement inhibition bit 23a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a cache memory device for registering data between a CPU and a main memory in order to transfer data between the CPU and the main memory in a computer. It is a thing.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing a configuration of an example of a conventional cache memory device. In this cache memory device, a part of the address from the address bus 1 of the data to be registered (for example, 2 of the address having 32 bits is used).
A decoder 20 that decodes an index that is 0 to 29 bits (for 10 bits) and the rest of the address (for example, 20 bits for 0 to 19 bits) according to the code that the decoder 20 decodes the index. A tag unit 21 that stores a tag 21a and one word (32 bits) of data to be registered (for example, having a 32-bit width) given from the data bus 3 corresponding to the tag 21a.
(Bit) data 22a, 22b, 22c, 22d which are stored separately, and a comparator 24 which compares the tag of the data to be read with the tag 21a of the registered data having an index equal to the data to be read, The cache control circuit 27 receives the comparison result of the comparator 24 and inputs from the data bus 3 and the address bus 1 and controls the cache memory 2.

The cache memory 2 includes a comparator 24.
, The decoder 20, the tag 21a and the data 22a, 2
The cache memory 2 has, for example, 1024 entries including 2b, 22c, and 22d (therefore, the storage capacity of the cache memory 2 is 4 kwords), and the CPU 28 and the main memory are connected via the data bus 3 and the address bus 1. It is connected to 29. FIG. 9 is a format showing a configuration example of a 32-bit address. 0 to 19 bits correspond to a 20-bit tag 13, 20 to 29 bits correspond to a 10-bit index 12, and 30, 31 bits correspond to 32-bit data 22a, 22b, 22c, 22.
It is a word control 11 for designating any one of d.

The operation of the cache memory device having such a configuration will be described below. When registration is done, the CPU
By reading from 28, the data of 4 words to be registered in the main memory 29 and the address corresponding thereto are
The data is input to the cache memory 2 via the data bus 3 and the address bus 1, respectively. In the cache memory 2, the 10-bit index of 20 to 29 bits of the address is decoded by the decoder 20 into the code corresponding to the entry of the cache memory, and the tag 21a of the tag section 21 of the entry corresponding to the decoded code is The tag 13 of the address of the data to be registered is registered in the words 22a, 22b, 22c and 22d addressed to 1 word of the data part 22, and the data of 4 words to be registered are respectively addressed to 1 word. By the way, when data is registered using an index which is a part of an address in this way, there are a plurality of data having the same index in the cache memory 2, but among the plurality of data, the cache memory Only one data can be registered in 2 at the same time.

When data is read, the address of the data to be read is input from the CPU 28 to the cache memory 2 via the address bus 1. In the cache memory 2, the decoder 20 decodes the 10-bit index of 20 to 29 bits of this address. next,
The tag 21a of the entry in the cache memory 2 corresponding to this decoded code and the tag 13 of the address of the read target data are compared by the comparator 24,
If they match, a cache hit occurs and 22a, 22b, 22c, 22d addressed to one word of the data section 22.
Of the data, one word of data designated by the word control 11 is read out and sent to the CPU via the data bus 3. At this time, since reading from the main memory 29 having a slow access speed is not performed, the reading is efficiently performed.

The tag 21a of the entry in the cache memory 2 corresponding to the decoded code and the tag 13 of the address of the data to be read are compared by the comparator 24. If they do not match, a cache miss occurs and the reading is performed. The target data is read from the main memory 29, sent to the CPU via the data bus 3, and
It is also input to the cache memory 2. In the cache memory 2, the read target data is registered according to the above-described registration operation. That is, the read target data is re-registered (replaced) in place of the registered data having the same index. Even if the data having the same index is not already registered, the read target data is registered.
However, at this time, the main memory 2 with a slow access speed
Since the reading from 9 is performed, the efficiency becomes poor.

[0007]

By the way, among the data in the main memory 29 having the same index, frequently referenced data is registered in the cache memory 2 and it is better not to replace the cache even if a cache miss occurs. The hit rate is high and efficient data transfer is possible. However, in the conventional cache memory, even though one of the data in the main memory having the same index is often referred to, it is replaced every time a cache miss occurs, so that the cache hit rate decreases. There was a problem.

The present invention has been made in view of the above circumstances, and in the first invention, a storage means for storing an address area of a data group for which replacement is prohibited and an address or registration of data to be read. The address of the data to be
A cache memory that improves the hit rate of the cache by providing a determination circuit that determines whether or not the address area is included and a replace prohibition bit for each data that stores the determination result of the determination circuit for the data to be registered The purpose is to provide a device.

In the second invention, the address area of the data group in which replacement is prohibited is set, and for the data to be registered, the determination result as to whether or not the address is included in the address area is stored for each data. At the same time, when reading, a method is adopted that determines whether or not the address of the data to be read is included in the address area, and executes or suppresses replacement according to the determination result and the determination result for already registered data. By doing so, it is an object of the present invention to provide a registration control method for a cache memory device in which the cache hit rate is improved. According to a third aspect of the present invention, there is provided a computer including a cache memory device in which a cache hit rate is improved by providing an instruction having a bit indicating whether or not it can be registered in the cache memory device and an instruction determination circuit for determining the bit. The purpose is to provide.

According to the fourth aspect of the present invention, it is determined whether or not the storage means for storing the address area of the data group whose replacement is prohibited and the address of the data to be read or the address of the data to be registered are included in the address area. A decision circuit,
An object of the present invention is to provide a computer provided with a cache memory device in which a cache hit ratio is improved by providing a replace prohibition bit for each data that stores the determination result of the determination circuit for data to be registered.

According to the fifth aspect of the invention, a bit is set in the instruction to indicate whether the instruction can be registered in the cache memory device, and the cache memory device executes or suppresses the instruction registration according to the result of the determination of the bit. It is an object of the present invention to provide a registration control method for a cache memory device in which the cache hit rate is improved by adopting

According to the sixth aspect of the invention, a bit indicating whether or not the instruction can be registered in the cache memory device is set in the instruction, and
An address area of a data group whose replacement is prohibited is set in the cache memory device, and it is determined whether the address of the data to be registered is included in the address area,
While storing the determination result for each data, when reading the data, the cache memory device determines the determination result of the bit and the determination result of whether the address of the data to be read is included in the address area. An object of the present invention is to provide a registration control method for a cache memory device that improves the hit rate of a cache by adopting a method of executing or suppressing replacement according to the determination result of already registered data.

[0013]

In a cache memory device according to a first aspect of the present invention, a storage means for storing an address area of a data group for which replacement is prohibited and an address of data to be read or an address of data to be registered are: A judgment circuit for judging whether or not the data is included in the address area and a replace prohibition bit for each data storing the judgment result of the judgment circuit for the data to be registered are provided. The replacement is executed or suppressed according to the determination result of the circuit and the stored content of the replacement prohibition bit.

In the cache memory device registration control method according to the second aspect of the present invention, the address area of the data group for which replacement is prohibited is set in advance, and the data to be registered is
The determination result as to whether or not the address is included in the address area is stored for each data, and when reading, it is determined whether or not the data to be read is included in the address area,
The replacement is executed or suppressed according to the determination result and the determination result of the registered data.

A computer according to a third aspect of the present invention includes an instruction having a bit indicating whether or not it can be registered in a cache memory device, and an instruction determination circuit for determining the bit, and the cache memory device determines the instruction determination circuit. According to the result, the registration of the target data of the command is executed or suppressed.

In the computer according to the fourth aspect of the present invention, the storage means for storing the address area of the data group for which replacement is prohibited and the address of the data to be read or the address of the data to be registered are included in the address area. And a replace prohibition bit for each data that stores the judgment result of the judgment circuit for the data to be registered. When reading, the judgment result of the instruction judgment circuit and the judgment for the data to be read are provided. The replacement is executed or suppressed according to the determination result of the circuit and the stored content of the replacement prohibition bit.

In the cache memory device registration control method according to the fifth aspect of the present invention, a bit indicating whether registration to the cache memory device is permitted or not is set in the instruction, and the cache memory device determines the bit according to the determination result. It is characterized by executing or suppressing the registration of instructions.

In the cache memory device registration control method according to the sixth aspect of the present invention, a bit indicating whether registration to the cache memory device is permitted or not is set in the instruction and the address of the data group whose replacement is prohibited in the cache memory device. An area is set, it is determined whether the address of the data to be registered is included in the address area, and the determination result is stored for each data. On the other hand, when reading, the cache memory device uses the bit And the judgment result of
It is characterized in that the replacement is executed or suppressed in accordance with the result of the determination as to whether or not the data to be read is included in the address area and the result of the determination regarding the registered data.

[0019]

In the cache memory device according to the first aspect of the present invention, the storage means stores the address area of the data group whose replacement is prohibited. The determination circuit determines whether the address of the data to be read or the address of the data to be registered is included in the address area stored in the storage means, and the replacement prohibition bit for each data is the determination circuit for the data to be registered. The determination result of is stored. When data is read from the CPU, according to the determination result of the determination circuit regarding the data to be read and the stored content of the replace prohibition bit,
Execute or suppress replacement.

In the registration control method of the cache memory device according to the second aspect of the present invention, the address area of the data group for which replacement is prohibited is set and it is determined whether the address of the data to be registered is included in the address area. Then, the determination result is stored for each data. Then, when the data is read from the CPU, it is determined whether or not the address of the data to be read is included in the address area. When the address of the data to be read is included in the address area, replacement or registration is performed. If the address of the data to be executed and read is not included in the address area, and the replace prohibition bit of the registered data is valid, replacement is suppressed and the address of the data to be read is not included in the address area, and the registered If the replace prohibition bit of the data is invalid, the replace is executed.

In the computer according to the third aspect of the present invention, the instruction has a bit indicating whether or not it can be registered in the cache memory device, and the cache memory device includes an instruction determination circuit that determines the bit. Whenever there is an instruction, the cache memory device executes or suppresses the registration (including replacement) of the instruction according to the determination result determined by the instruction determination circuit.

In the computer according to the fourth aspect of the present invention, the storage means stores the address area of the data group whose replacement is prohibited. The determination circuit determines whether the address of the data to be read or the address of the data to be registered is included in the address area stored in the storage means, and the replacement prohibition bit for each data is the determination circuit for the data to be registered. The determination result of is stored. When data is read from the CPU, replacement is executed or suppressed according to the determination result of the instruction determination circuit, the determination result of the determination circuit for the data to be read, and the stored contents of the replace prohibition bit.

In the cache memory device registration control method according to the fifth aspect of the present invention, a bit indicating whether registration to the cache memory device is possible or not is set in the instruction, and the cache memory device determines the bit according to the determination result. Executes or suppresses registration (including replacement) of instruction target data.

In the cache memory device registration control method according to the sixth aspect of the present invention, a bit indicating whether registration to the cache memory device is permitted or not is set in the instruction and the address area of the data group in which replacement is prohibited is set in the cache memory device. Is set, it is determined whether the address of the data to be registered is included in the address area, and the determination result is stored for each data. Then, when the data is read from the CPU, the cache memory device indicates that the bit is registerable, and when the address of the data to be read is included in the address area, the replace or register is executed, and the bit is stored. If the address of data to be read is not included in the address area and the replace prohibition bit of the registered data is valid, the replacement is suppressed, the bit indicates that the register is possible, and the address of the data to be read. Is not included in the address area and the replace prohibition bit of the registered data is invalid, the replace is executed,
If the bit indicates that registration is not possible, replacement is suppressed.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments. Example 1. FIG. 1 is a block diagram showing the configuration of an embodiment of a cache memory device according to the first invention and a registration control method of the cache memory device according to the second invention. In this cache memory device, a decoder 20 for decoding an index which is a part of an address (for example, 10 bits of 20 to 29 bits of an address having 32 bits) of data to be registered is provided with a decoder 20. A tag unit 21 that stores a tag 21a that is the remaining part of the address (for example, 20 bits of 0 to 19 bits) according to the decoded code, and a tag 2
A data section 22 for storing data 22a, 22b, 22c, 22d addressed to 1 word for data to be registered (for example, having a 32-bit width) given from the data bus 3 is provided corresponding to 1a. .

Further, the tag of the registered data 21a having an index equal to the tag of the data to be read and the data to be read.
And a cache control circuit 27a which receives the comparison result of the comparator 24 and inputs from the data bus 3 and the address bus 1 and controls the cache memory 2a. Cache memory 2
a is a comparator 24, a decoder 20, and a tag 21.
a and the data 22a, 22b, 22c, 22d, for example, 1024 entries (therefore,
The storage capacity of the cache memory 2a is 4 kwords), and the CP via the data bus 3 and the address bus 1
It is connected to the U 28 and the main memory 29.

Further, the lower limit register 4 and the upper limit register 5 which are connected to the address bus 1 and respectively store the lower limit address and the upper limit address of the data group whose replacement is prohibited, and the address of the data to be read or the address of the data to be registered. , The lower limit register 4 and the upper limit register 5, it is determined whether or not it is included in the address area, and the determination circuit 6 for sending the determination result to the cache control circuit 27a.
And a replace prohibition bit 23a for each tag 21a that stores the determination result of the determination circuit 6 for the data to be registered. The initial value of the replacement prohibition bit 23a indicates invalidity.

FIG. 9 is a format showing a configuration example of a 32-bit address. 0 to 19 bits correspond to a 20-bit tag 13, 20 to 29 bits correspond to a 10-bit index 12, and 30 and 31 bits correspond to 3, respectively.
The word control 11 designates any of the 2-bit data 22a, 22b, 22c, 22d.

The operation of the cache memory device having such a configuration will be described with reference to the flowchart of FIG. 2 showing the operation. When the registration is performed, the instruction from the CPU 28 inputs the 4-word data to be registered in the main memory 29 and the corresponding address to the cache memory device via the data bus 3 and the address bus 1, respectively. . In the cache memory device, the 10-bit index of 20 to 29 bits of the address is decoded by the decoder 20 into the code corresponding to the entry, and the data to be registered in the tag 21a of the tag section 21 of the entry corresponding to the decoded code. 13 of the address of the data part 22 is addressed to one word of the data part 22a, 22a.
The data of 4 words to be registered in b, 22c and 22d is 1
Each ward is registered. At this time, the determination circuit 6
Determines whether or not the address of the registration target data is included in the address area (replacement prohibition area) stored in the lower limit register 4 and the upper limit register 5, and the determination result is stored in the replacement prohibition bit 23a.

When data is read, the address of the data to be read is input from the CPU 28 to the cache memory device via the address bus 1. In the cache memory device, the decoder 20 decodes the 10-bit index of 20 to 29 bits of this address. Next, the tag 21a of the entry in the cache memory 2a corresponding to this decoded code and the tag 13 of the address of the read target data are compared by the comparator 24 (FIG. 2S10), and when they match, It becomes a cache hit, and four 22s addressed to 1 word of the data part 22
Of a, 22b, 22c, and 22d, the data for one word designated by the word control 11 is read (see FIG. 2).
S20), and sent to the CPU via the data bus 3.

The tag 21a of the entry in the cache memory 2a corresponding to the decoded code and the tag 13 of the address of the data to be read are compared by the comparator 24 (S10 of FIG. 2). As a result of a miss, the data to be read is read from the main memory 29, sent to the CPU via the data bus 3 and also input to the cache memory device.
In the cache memory device, the determination circuit 6 determines that the address of the read target data is the lower limit register 4 and the upper limit register 5.
It is determined whether or not it is included in the replacement prohibition area stored in (1) in FIG. 2 (S11).

When the judgment circuit 6 judges that the data is included in the replacement prohibited area (S11 in FIG. 2), the read target data is re-registered in the entry in which the data of the same index is already registered according to the above-mentioned registration operation ( Replace the existing data will be deleted) (Fig. 2 S1)
2, 13). Even when the data having the same index is not already registered (S12 in FIG. 2), the read target data is registered (S14 in FIG. 2). And the replace prohibition bit 23
a is set and validated (S15 in FIG. 2).

When the determination circuit 6 determines that the data is not included in the replacement prohibited area (FIG. 2S11), the registered data (FIG. 2S1) having the same index as the read target data is stored.
If the replace prohibition bit 23a of 6) is invalid (see FIG. 2).
S17), according to the above-described registration operation, the read target data is re-registered (replaced; the already-registered data is erased) in the entry in which the data of the same index is already registered (S18 in FIG. 2). If the replacement prohibition bit 23a is valid (S17 in FIG. 2), the read target data is not registered (not replaced). If the data with the same index is not already registered (FIG. 2S16), the read target data is registered (FIG. 2S19).

In this way, the cache hit rate is improved by setting the address range of frequently referenced data among the data in the main memory 29 having the same index, which is a part of the address, in the replacement prohibited area. Can be made. In this embodiment, the address area of the data group whose replacement is prohibited is stored in the lower limit register 4 and the upper limit register 5, but the lower limit of the address area is set in the lower limit register 4 and the size of the address area is set differently. You may make it memorize | store in a register.

Example 2. FIG. 3 is a block diagram showing the configuration of an embodiment of a computer according to the third invention and a registration control method for a cache memory device according to the fifth invention. In this computer, a decoder 20 that decodes an index, which is a part of an address (for example, 10 bits of 20 to 29 bits of an address having 32 bits) of data to be registered, and a decoder 20 decodes the index. Depending on the code, the rest of the address (for example, 20 bits from 0 to 19 bits)
And a tag portion 21 for storing the tag 21a that is
Corresponding to the above, there is provided a data section 22 for storing data 22a, 22b, 22c, 22d addressed to 1 word for data to be registered (for example, having a 32-bit width) given from the data bus 3.

Further, the tag of the registered data 21a having an index equal to the tag of the data to be read and the data to be read.
And a cache control circuit 27b which receives the comparison result of the comparator 24 and the inputs from the data bus 3 and the address bus 1 and controls the cache memory 2b. Cache memory 2
b is a comparator 24, a decoder 20, and a tag 21.
a and the data 22a, 22b, 22c, 22d, for example, 1024 entries (therefore,
The storage capacity of the cache memory 2b is 4 kwords), and the CP via the data bus 3 and the address bus 1
It is connected to the U 28 and the main memory 29. Further, it is provided with an instruction determination circuit 26 which is connected to the data bus 3 and determines a bit included in the instruction, which indicates whether or not the instruction can be registered in the cache memory device, and the determination result is sent to the cache control circuit 27b.

FIG. 4 is a format showing a configuration example of a 32-bit transfer instruction. In this transfer command, for example,
The 10th bit is a bit indicating whether registration to the cache memory device is possible or not. For example, when the 10th bit is “1” (FIG. 4A), it indicates registration possible to the cache memory device. When the 10th bit is "0" (Fig. 4
(B)) indicates that registration in the cache memory device is impossible. Thus, the other instructions have similar bits. Since the configuration example of the address is the same as that described in the first embodiment, the description will be omitted.

The operation of the computer having such a configuration is
The operation will be described with reference to the flowchart of FIG. When the instruction determination circuit 26 determines that the 10th bit of the instruction is “1” and cache registration is possible, and the registration is performed, the 4-word instruction to be registered in the main memory 29 and the address corresponding thereto are The data is input to the cache memory 2b via the data bus 3 and the address bus 1, respectively. In the cache memory 2b, the address 2
The 10-bit index of 0 to 29 bits is decoded by the decoder 20 into the code corresponding to the entry, and the tag 13a of the address of the instruction to be registered is added to the tag 21a of the tag unit 21 of the entry corresponding to the decoded code.
22a, 22b, 22c addressed to one word of the data section 22,
Data of 4 words to be registered is respectively registered in 22d for 1 word.

When reading is performed, the address of the instruction is input to the cache memory 2 via the data bus 3 and the address bus 1. In the cache memory 2b,
The decoder 20 decodes the 10-bit index of 20 to 29 bits of this address. Then, the tag 21a of the entry in the cache memory 2b corresponding to this decoded code and the tag 13 of the address of the instruction to be read are compared by the comparator 24 (FIG. 5S3).
0), when they match, it is a cache hit,
22a, 22b, 22c addressed to one word of the data section 22,
An instruction for one word designated by the word control 11 out of 22d is read (S35 in FIG. 5), and the data bus 3
To the CPU.

The tag 21a of the entry in the cache memory 2b corresponding to the decoded code and the tag 13 of the address of the instruction are compared by the comparator 24 (S30 in FIG. 5). If they do not match, a cache miss occurs. , Instructions are read from the main memory 29, sent to the CPU via the data bus 3, and input to the cache memory device. In the cache memory device, the instruction determination circuit 26 determines the 10th bit of the instruction, which indicates whether the instruction can be registered in the cache memory device.

When the instruction determination circuit 26 determines that the 10th bit of the instruction is "1" and the cache can be registered (FIG. 5S).
31), according to the above-mentioned registration operation, the instruction is re-registered in the entry in which the data of the same index is already registered (replaced. The already-registered data is erased).
(FIG. 5 S32, 33). Even when the command with the same index is not already registered (S32 in FIG. 5), this command is registered (S34 in FIG. 5).

When the instruction determination circuit 26 determines that the 10th bit of the instruction is "0" and the cache cannot be registered (FIG. 5).
S31), the read target data is not registered (not replaced). In this way, by setting whether or not cache registration is possible for an instruction, among the instructions in the main memory 29 in which a part of the addresses have the same index, the instruction that is often referred to in the program is registered in the cache memory device and is referred to less often. It is possible to improve the hit rate of the cache by not registering the instruction not to register. In this embodiment, the cache registration permission / inhibition is set for the instruction, but the cache registration permission / prohibition may be set for the data. In addition, whether or not cache registration is possible may be set for both instructions and data.

Example 3. FIG. 6 is a block diagram showing the configuration of an embodiment of a computer according to the fourth invention and a registration control method for a cache memory device according to the sixth invention. This computer has a lower limit register 4 and an upper limit register 5 which store the lower limit address and the upper limit address of a data group prohibited to be replaced, respectively, and an address of data to be read or an address of data to be registered. A determination circuit 6 that determines whether the address area stored in the lower limit register 4 and the upper limit register 5 is included and sends the determination result to the cache control circuit 27c.
And a replace prohibition bit 23a for each tag 21a that stores the determination result of the determination circuit 6 for the data to be registered. Other configurations are the same as the configurations described in the second embodiment, and thus the description will be omitted.

FIG. 4 is a format showing a configuration example of a 32-bit transfer instruction. In this transfer command, for example,
The 10th bit is a bit indicating whether registration to the cache memory device is possible. For example, when the 10th bit is “1” (FIG. 4A), registration to the cache memory device is possible (cache registration). When the 10th bit is “0” (FIG. 4B), it indicates that registration in the cache memory device is impossible (no cache registration command). Thus, the other instructions have similar bits. Since the configuration example of the address is the same as the configuration described in the first embodiment, the description will be omitted.

The operation of the computer having such a configuration is
The operation will be described with reference to the flowchart of FIG. When the 10th bit of the instruction is "1" and the cache registration is possible and the registration is performed by the instruction determination circuit 26, the data of 4 words to be registered in the main memory 29 and the corresponding address are Cache memory 2a via data bus 3 and address bus 1, respectively
Is input to. In the cache memory 2a, the 10-bit index of 20 to 29 bits of the address is decoded by the decoder 20 into the code corresponding to the entry,
Tag part 21 of the entry corresponding to the decoded code
The tag 13a of the address of the data to be registered in the tag 21a of
22a, 22b, 22 addressed to one word of the data part 22
The data of 4 words to be registered are respectively registered in c and 22d for 1 word. At this time, the determination circuit 6 determines that the address of the data to be registered is the address area (replacement prohibited area) stored in the lower limit register 4 and the upper limit register 5.
Is included in the replacement prohibition bit 23a.

When reading is performed, the address of the data to be read is input from the CPU 28 to the cache memory 2a via the address bus 1. In the cache memory 2a, the decoder 20 decodes the 10-bit index of 20 to 29 bits of this address. Next, the tag 21a of the entry in the cache memory 2a corresponding to this decoded code and the tag 13 of the address of the read target data are compared by the comparator 24 (S40 in FIG. 7), and if they match, A cache hit occurs, and one word data designated by the word control 11 is read out from the four parts 22a, 22b, 22c, 22d addressed to one word of the data part 22 (S51 in FIG. 7) and is transferred via the data bus 3. Sent to the CPU.

The tag 21a of the entry in the cache memory 2a corresponding to the decoded code and the tag 13 of the address of the data to be read are compared by the comparator 24 (S40 in FIG. 7). If they do not match, the cache is found. As a result of a miss, the data to be read is read from the main memory 29, sent to the CPU via the data bus 3 and also input to the cache memory device.
In the cache memory device, the instruction determination circuit 26 determines the 10th bit indicating whether the instruction can be registered in the cache memory device, and the determination circuit 6 determines that the address of the data to be read is the lower limit register 4 and the upper limit register. It is determined whether or not it is included in the replacement prohibited area stored in No. 5.

When the instruction determination circuit 26 determines that the 10th bit of the instruction is "0" and the cache cannot be registered (FIG. 7).
S41), the read target data is not registered (not replaced). The instruction determination circuit 26 determines that the 10th bit of the instruction is "1" and the cache can be registered (S41 in FIG. 7).
When the determination circuit 6 determines that the read target data is included in the replacement prohibited area (S42 in FIG. 7), the read target data is reregistered (replaced) in the entry in which the data of the same index is already registered according to the above-described registration operation.
The registered data is erased) (S43, 44 in FIG. 7). Even when data with the same index is not already registered (see FIG. 7).
S43), the data to be read is registered (S4 in FIG. 7).
5). Then, the replace prohibition bit 23a is set and made valid (S46 in FIG. 7).

The instruction judging circuit 26 judges that cache registration is possible when the 10th bit of the instruction is "1" (S4 in FIG. 7).
1) If the determination circuit 6 determines that the replacement prohibition area is not included in the replacement prohibition area (S42 of FIG. 7), the replacement prohibition bit 23a of the registered data (FIG. 7S47) having the same index as the read target data is invalid (FIG. 7S42). 7S4
8), according to the above registration operation,
The data of the same index is re-registered (replaced. The already-registered data is erased) in the already-registered entry (S49 in FIG. 7). Replace prohibition bit 23
If a is valid (S48 in FIG. 7), the read target data is not registered (not replaced). If the data with the same index is not already registered (FIG. 7S47), the read target data is registered (FIG. 7S50).

As described above, of the data in the main memory 29 having the same index which is a part of the address, the range of the address of the data that is often referred to is set in the replace prohibition area, and the cache registerability is set in the instruction. By registering frequently-referenced data in the cache memory device and not registering infrequently-referenced data, the cache hit rate can be improved.

[0051]

According to the cache memory device of the first aspect of the present invention, it is possible to realize a cache memory device having an improved cache hit rate.

According to the cache memory device registration control method of the second, fifth, and sixth inventions, the cache hit rate can be improved.

According to the computers of the third and fourth aspects of the invention, it is possible to realize a computer equipped with a cache memory device in which the cache hit rate is improved.

[Brief description of drawings]

FIG. 1 is a cache memory device according to a first aspect of the invention and a registration control method 1 for a cache memory device according to the second aspect of the invention.
It is a block diagram which shows the structure of an Example.

FIG. 2 is a cache memory device according to a first invention and a registration control method 1 for a cache memory device according to the second invention.
It is a flow chart which shows operation of an example.

FIG. 3 is a block diagram showing a configuration of an embodiment of a registration control method of a computer according to a third invention and a cache memory device according to the fifth invention.

FIG. 4 is a format showing a configuration example of an instruction.

FIG. 5 is a flowchart showing an operation of a computer according to a third aspect of the invention and an embodiment of a registration control method for a cache memory device according to the fifth aspect of the invention.

FIG. 6 is a block diagram showing a configuration of an embodiment of a computer according to a fourth invention and a registration control method of a cache memory device according to the sixth invention.

FIG. 7 is a flowchart showing the operation of a computer according to a fourth invention and an embodiment of a registration control method for a cache memory device according to the sixth invention.

FIG. 8 is a block diagram showing a configuration of an example of a conventional cache memory device.

FIG. 9 is a format showing a configuration example of an address.

[Explanation of symbols]

1 address bus, 2a, 2b cache memory, 3
Data bus, 4 lower limit register, 5 upper limit register,
6 decision circuit, 12 index, 13, 21a tag, 22a to 22d data, 23a replacement prohibition bit, 24 comparator, 26 instruction decision circuit, 2
8 CPU, 29 main memory.

Claims (6)

[Claims] 1. In order to transfer data between the CPU and the main memory, when data is registered via the CPU and the main memory and read from the CPU,
If the data to be read is already registered, the already registered data is read, while if the data to be read is not registered, the data read from the main memory is fetched and reregistered instead of other already registered data. In a cache memory device that executes replacement, a determination circuit that determines whether replacement is possible and a replacement prohibition bit for each data that stores the determination result of the determination circuit for the data to be registered are provided and read from the CPU. In this case, the cache memory device is characterized in that the replacement is executed or suppressed according to the judgment result of the judgment circuit for the data to be read and the stored content of the replacement prohibition bit. 2. In order to transfer data between the CPU and the main memory, when data is registered via the CPU and the main memory and read from the CPU,
If the data to be read is already registered, the already registered data is read, while if the data to be read is not registered, the data read from the main memory is fetched and reregistered instead of other already registered data. In the method for controlling registration of a cache memory device that executes replacement, whether replacement is possible is determined, the determination result is stored for each data, and when read from the CPU, the address of the read data is the address area. The method for controlling registration of a cache memory device, which determines whether or not a replacement is included in the cache memory device, and executes or suppresses replacement according to the determination result and the determination result for already registered data. 3. In order to transfer data between the CPU and the main memory, when data is registered via the CPU and the main memory and read from the CPU,
If the data to be read is already registered, the already registered data is read, while if the data to be read is not registered, the data read from the main memory is fetched and reregistered instead of other already registered data. In a computer including a cache memory device that executes replacement, an instruction has a bit indicating whether or not registration in the cache memory device is possible, and the cache memory device includes an instruction determination circuit that determines the bit, The cache memory device, according to the determination result of the instruction determination circuit,
A computer characterized by being adapted to execute or inhibit registration of the instruction. 4. The cache memory device comprises a determination circuit for determining whether or not replacement is possible, and a replacement prohibition bit for each data that stores the determination result of the determination circuit for the data to be registered, and is read from the CPU. In this case, the replacement is executed or suppressed according to the judgment result of the instruction judgment circuit, the judgment result of the judgment circuit for the data to be read, and the stored content of the replacement prohibition bit. The computer according to claim 3. 5. When data is registered between the CPU and the main memory and data is read from the CPU in order to transfer the data between the CPU and the main memory,
If the data to be read is already registered, the already registered data is read, while if the data to be read is not registered, the data read from the main memory is fetched and reregistered instead of other already registered data. In the method of controlling registration of a cache memory device, a bit indicating whether registration to the cache memory device is possible is set in an instruction, and the cache memory device is
A method for controlling registration of a cache memory device, wherein registration of the instruction is executed or suppressed according to a determination result of determining the bit. 6. In order to transfer data between the CPU and the main memory, when data is registered via the CPU and the main memory and read from the CPU,
If the data to be read is already registered, the already registered data is read, while if the data to be read is not registered, the data read from the main memory is fetched and reregistered instead of other already registered data. In a cache memory device registration control method for executing replacement, an instruction has a bit indicating whether registration to the cache memory device is possible, and the cache memory device determines whether replacement is possible, and the determination result is a data. Each time the data is stored, the cache memory device, when read from the CPU, determines the result of the determination of the bit, the result of whether the read data is replaceable, and the result of the registered data. And according to
A cache memory device registration control method for executing or suppressing replacement.