JPH0883807A - Hetero junction bipolar transistor - Google Patents

Abstract

PURPOSE: To reduce the reduction in current amplification rate even at a high temperature and to extend life by including an electrically neutral second impurity element for III-V compound semiconductor into a base layer and an emitter layer near the base layer at a specific ratio for a first impurity element. CONSTITUTION: An electrically active first impurity element such as Be giving conductive type to a base is included in a base layer 24. Then, a second impurity element consisting of III or V elements such as electrically neutral In, Sb, and P for III-V compound semiconductor is included in the base layer 24 and emitter layers 45 and 46 within ×0.02-×30 of the first impurity element and at least a second impurity is doped to the emitter/base up to a range where the depletion layer of junction spreads. This restricts the dislocation of the emitter/base junction in the depletion layer.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an ultra high speed LSI, an ultra high speed
The present invention relates to a heterojunction bipolar transistor (hereinafter referred to as HBT) used for large-capacity optical communication, communication in the microwave band to the terahertz band, and the like. More specifically, the present invention relates to a long life and high reliability of HBT.

[0002]

2. Description of the Related Art It is required to improve the maximum oscillation frequency as an index for increasing the speed of a bipolar transistor. The maximum oscillation frequency f _max is

[Equation 1]

[Equation 2] Is represented. Boltzmann constant K here, the q as elementary _{charge, r e = KT / nqI c} , R e is an external emitter _resistor, C _{BE, C bc} is the base-emitter, base-collector junction capacitance, _{C P} is the parasitic capacitance, τ _F is the total electron transit time, and τ _B and τ _C are the base and collector transit times.
From the formula (1), in order to improve the maximum oscillation frequency,
It is necessary to improve the cutoff frequency f _T and lower the base resistance R _B. These two factors pose conflicting requirements for the design of the base layer. That is, it is necessary to reduce the base width W _{B to} improve f _T , and to increase the base width to decrease R _B. An HBT has been developed as a structure that can satisfy these conflicting requirements. In this structure, a wide bandgap emitter is used to improve the injection efficiency. As a result, the injection efficiency can be maintained at a predetermined value even if the emitter concentration is lowered, so the depletion layer between the base and emitter is set to extend to the emitter layer, and the base concentration is reduced while suppressing the tunnel current between the emitter and base. It has become possible to improve. As a result, even if the base width is reduced,
Since the base resistance can be kept low, f _max can be greatly improved. Behind the expectations for HBTs, threshold dispersion and drive capability may still be issues in GaAs FET integrated circuits.
The operating characteristics of HBT are basically the same as those of Si bipolar transistor, and the mutual conductance is standard G
It is 10 to 20 times larger than aAs MESFET. The high current drive capability and the high speed resulting from the excellent electron transport characteristics of III-V semiconductors make the HBT
Has become the driving force for the development of.

The characteristics of HBT with respect to GaAsFET are summarized as follows: (1) High transconductance; (2) Stable because the threshold is almost determined by the bandgap of the base (characteristic variation with epi thickness and doping concentration is small). (3) Since the current control depends on the potential of the base, FE
There is no characteristic deterioration due to scale-down, which is equivalent to the so-called short channel effect at T; (4) The input / output separation is good, so the output conductance is sufficiently small; (5) The influence of the element surface is small, so 1 / f Noise is small; (6) Device breakdown voltage is determined by the epi structure and can be made relatively large; (7) Since the intrinsic part of the device is determined by the epi structure, the influence of lithography variations is small. To date, the most successful HBT structures have been based on materials using a combination of AlGaAs and GaAs. This is mainly because the electron transport properties in GaAs are suitable for high-speed operation,
This is because the lattice mismatch between GaAs and AlGaAs is relatively small, and a high-quality heterojunction can be easily epitaxially grown.

[0004]

However, AlGaAs
When operating at a high current density, HBTs made of GaAs and GaAs have a large number of defects in the device as the energization time increases, and for example, the current gain of the device decreases and finally becomes inoperable. There is a problem that ends up.

In particular, when a high concentration of Be is used as the base dopant, the current amplification factor decreases within a few tens to a few hundreds of hours when an energization test is conducted at a high temperature of about 200 ° C., and the device deteriorates. (References: Nozu et al., IEICE Technical Committee ED91-16)
3, MW 91-146, ICD 91-189). That is, the mean failure interval (Mean Time to Fai)
lure; hereinafter referred to as MTTF) had a shortcoming that it was short. C or Zn instead of Be as the base dopant
Similar results can be obtained with a different degree of use. These results mean that the device has poor reliability even at room temperature operation. InGaP and Ga
Similar deterioration is observed in the HBT made of As.
To date, the cause of the decrease in current amplification factor in these high temperature current tests is not completely understood. However, it is conceivable that the transition of non-radiative recombination centers in the base layer or the proliferation of defects at the time of high-temperature operation causes the current amplification factor to decrease.

In order to solve the above problems, the present invention has an object to provide a highly reliable HBT having a long current and a small decrease in current amplification factor even at high temperatures.

A further object of the present invention is to provide a highly reliable and long-life HBT capable of suppressing the growth of defects such as dislocations and recombination centers in the base layer and in the vicinity of the emitter / base junction and the base / collector junction. Is.

[0008]

In order to achieve the above object, the first feature of the present invention according to claim 1 is that in an HBT as shown in FIG. 2, the profile of impurities in the vicinity of the base is shown in FIG. Be, which gives the base a conductivity type, as shown
Etc. containing an electrically active first impurity element such as, for example, I, which is electrically neutral to the III-V group compound semiconductor.
Second group consisting of group III or V elements such as n, Sb, P
The impurity element of 0.02 to 3 times that of the first impurity element
It is included in the base layer 24 and the emitter layers 45 and 46 near the base layer in a range of 0 times.

A second feature of the present invention according to claim 2 is shown in FIG.
In the HBT as shown in FIG. 3, the base layer 24 contains an electrically active first impurity element such as Be which gives the base a conductivity type, as shown in FIG. The second impurity element, which is electrically neutral to the group V compound semiconductor and is composed of a group III or group V element such as In, Sb, P, etc., in a range of 0.02 times to 30 times that of the first impurity element It is included in the base layer 24, the emitter layers 25 and 26 near the base layer, and the collector layer 23 near the base layer 24.

The third feature of the present invention according to claim 3 is the HBT of the first or second feature, and further, as described in FIGS. 5 to 7, the first impurity element in the base layer 24. Profile has a non-uniform doping profile that gradually increases or decreases with respect to the emitter layer. Although FIGS. 5 to 7 show a gentle slope, the profile may be a higher-order curve or may be increased or decreased stepwise.

More preferably in the first or second feature, the first impurity element is Be and the second impurity element is I.
It is that n is doped with In in the base layer 24 in a range of 0.11 to 11 times that of Be.

More preferably in the first or second feature, the first impurity element is Be and the second impurity element is S.
In b, Sb is doped in the base layer 24 in a range of 0.025 to 2.5 times that of Be.

More preferably, the first impurity element is C and the second impurity element is In.
That is, In is doped in the base layer 24 in a range of 0.24 to 24 times that of C.

More preferably in the first or second feature, the first impurity element is Zn and the second impurity element is P.
And P is in the range of 0.05 to 5 times that of Zn in the base layer 2
4 is doped.

More preferably in the first or second characteristic, the first impurity element is C and the second impurity element is Sb.
That is, Sb is doped in the base layer 24 in a range of 0.27 to 27 times that of C.

[0016]

According to the first feature of the present invention, the first impurity having a covalent bond radius smaller than that of at least one of the constituent elements of the III-V group compound semiconductor, which is the base material of the base layer, in the base layer 24. When the element is doped, a second impurity element that is electrically neutral to the III-V group compound semiconductor and has a larger covalent radius than at least one of the constituent elements of the III-V group compound semiconductor is added. Addition to the base layer makes it possible to relax lattice strain or internal stress. On the contrary, when the first impurity element causes the lattice constant of the base layer to be larger than the lattice constant of the host crystal, the covalent bond radius is smaller than at least one of the constituent elements of the host crystal, and a III-V group compound semiconductor is obtained. On the other hand, by adding the electrically neutral second impurity element to the base layer, lattice strain or internal stress can be relaxed.

For example, in the case of a GaAs base layer, GaAs
When C or Be having a covalent bond radius smaller than that of GaAs is doped, the internal stress can be relaxed by simultaneously doping In or Sb having a covalent bond radius larger than that of GaAs. When Zn, Cd or the like having a larger covalent radius than GaAs is doped as the first impurity element, the lattice strain and the internal stress are relaxed by doping P or N as the second impurity element.

Further, according to the first feature of the present invention, the second
Of the impurity element of (3) extends to the emitter layer side, and the emitter / base is doped with at least the second impurity element to the extent that the depletion layer of the junction spreads. By thus doping the second impurity element, generation of dislocations in the depletion layer of the emitter-base junction is suppressed,
Moreover, since lattice strain and internal stress in the base layer are alleviated, a long life and high reliability operation of the HBT can be realized.
Further, when the first impurity element that causes conductivity in the base layer is located at the group III element position (group V element position) in the group III-V compound semiconductor, the base layer is used as the second impurity element. If a group V element (group III element) different from the constituent group V element (group III element) is added to the base layer, the stoichiometric balance is not lost and the activation rate of impurities in the base layer is reduced. Never.

According to a second aspect of the present invention, in addition to the first aspect, the second impurity element is doped so as to cover at least a region where the depletion layer of the base-collector junction extends, Since the generation and multiplication of dislocations in the depletion layer of the collector junction are suppressed, long life and stable operation are possible.

According to the third feature of the present invention, in addition to the first feature, the occurrence of misfit dislocations due to the heterojunction between the emitter and the base is further suppressed, so that the life and stability are further improved. Various operations are possible.

[0021]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 shows AlG according to the first embodiment of the present invention.
The impurity density profile in the vicinity of the pGaAs base layer 24 of aAs / GaAsHBT is shown. The numbers on the horizontal axis in FIG. 1 represent the respective layers of the emitter top npn type HBT shown in FIG. 2, and the vertical axes represent the concentrations of Be and In. However, the vertical axis is an arbitrary scale, and although the concentration cannot be directly compared from FIG. 1, it is 5 × 10 ¹⁹ cm ^{−3 in} the first embodiment of the present invention.
Of Be and In of 6.6 × 10 ¹⁹ cm ⁻³ are simultaneously pGa
It can be seen that the As base layer is doped to alleviate the lattice constant reduction that occurs when Be is solely doped. In is not only in the base region but also in nAl _x Ga as shown in FIG.
_1-x As layer 45, nAl _0.3 Ga _0.7 As emitter layer 4
The region 7 is doped to prevent the generation of dislocations and other intrinsic defects in the depletion layer region between the emitter and the base.

The HBT shown in FIG. 2 has a semi-insulating GaAs substrate 21 and an n ⁺ GaAs collector contact layer 22, n sequentially.
GaAs collector layer 23, pGaAs base layer 24, n
Al _x Ga _1-x As layer 45, nAl _0.3 Ga _0.7 As emitter layer 46, nAl _x Ga _1-x As layer 47, n ⁺ In
_It has a structure in which a _y Ga _1-y As layer 48 and an n ⁺ In _0.5 Ga _0.5 As emitter contact layer 27 are laminated. Here, for example, n ⁺ GaAs collector contact layer 25
Is 500 nm, Si concentration is 6 × 10 ¹⁸ cm ⁻³ , nGaAs
Collector layer 12 is 600 nm, Si concentration is 5 × 10 ¹⁶ cm
^-3 , the pGaAs base layer 24 has an impurity profile shown in FIG. 1 and a thickness of 70 nm, and an nAl _x Ga _{1 -x} As layer 45.
Is 30 nm, Si concentration is 1 × 10 ¹⁸ cm ⁻³ , nAl _x Ga
_1-x As layer 47 is 30 nm, Si concentration is 1 × 10 ¹⁸ c
m ⁻³ , n ⁺ In _y Ga _{1 -y} As layer 28 is 50 nm, Si
Concentration 3 × 10 ¹⁹ cm ⁻³ , n ⁺ In _0.5 Ga _0.5 As emitter contact layer 29 is 50 nm, Si concentration 3 × 10 ¹⁹
cm ^-3 .

Next, a manufacturing process for manufacturing the HBT of the first embodiment of the present invention shown in FIG. 2 will be described. First, M
The n ⁺ GaAs collector contact layer 22, the nGaAs collector layer 23, ..., N ⁺ I are formed on the semi-insulating GaAs substrate 21 by the BE method, the low pressure MOCVD method, the CBE method, or the like.
n _y Ga _1-y As graded layer 48, n ⁺ In _{0. 5}
The Ga _0.5 As emitter contact layer 27 is successively and epitaxially grown. At this time, the pGaAs base layer 24
Is doped with Be and In, and the nAl _x Ga _1-x As graded layer 45 and the nAI _0.3 Ga _0.7 As emitter layer 46 are doped with Si and In.

Next, a mask pattern for etching the U-groove for taking out the base electrode is formed on the continuous epitaxially grown wafer with a photoresist, and the mask pattern is used to form InGaAs layers 27, 48 and AlGaAs layers 47, 4.
6, 45 are etched by RIE or ECR ion etching until the nAl _x Ga _1-x As graded layer is exposed to form U grooves. After that, the semiconductor layer on the sidewall of the U groove is slightly side-etched by wet etching with the photoresist mask attached. The amount of this side etching determines the separation between the base electrode and the emitter region. The optimum value of the side etching amount depends on the structure of the epitaxial film, the film quality, the pattern size, etc., but may be about 0.1 μm, for example. Although dry etching was used here as the main etching means,
It is also possible to use only wet etching. Subsequently, Pt / Ti / Pt / Au for the base electrode is vapor-deposited on the entire surface of the wafer, and then the photoresist is removed, so that the base electrode 32 is formed at the bottom of the U groove by a so-called lift-off method. Then, heat treatment (alloy) is performed so that the Pt of the lowermost layer penetrates to the pGaAs base layer 24,
The base layer 24 and the base electrode 32 are electrically contacted. In FIG. 2, a thin nAl _x Ga _{1 -x} As graded layer 45 is shown to remain between the pGaAs base layer 24 and the base electrode 32, but this portion is actually a Pt and pGaAs base layer. There is an alloy layer with layer 24. Further, in order to form an insulating layer of the base electrode 32 and the emitter electrode 31, a prepolymer solution of a polyimide resin is applied to the entire surface of the substrate by a spin coating method, and the polyimide resin is gradually cured up to a thermosetting temperature (350 ° C.). By heating, the polyimide resin 34 is formed on the entire surface including the U groove. Then, by the RIE method using O ₂ or the like, n ⁺ In
_The polyimide resin 34 is etched back until the _0.5 Ga _0.5 As emitter contact layer 27 is exposed, leaving the polyimide resin 34 only on the base electrode 32 in the U groove, and opening the contact hole of the emitter electrode 31 in a self-aligned manner. . Next, Ti / Pt / Au for the emitter electrode 31 is vapor-deposited and patterned by using the lift-off method, then the element isolation region 35 is formed by proton ion implantation, and finally the sub-collector layer 22 is exposed by wet etching. After depositing AuGe / Ni / Ti / Au, patterning is performed using a lift-off method, and alloying is performed by heat treatment at about 370 ° C. to form a collector electrode 33 as shown in FIG.

FIG. 3 shows impurity profiles in the depth direction of Be and Sb near the base layer of the emitter top npn type HBT according to the second embodiment of the present invention as shown in FIG. As shown in the sectional view of FIG. 4, InGaP / GaAsHBT has a thickness of 50 on the semi-insulating GaAs substrate 21.
0 nm n ⁺ GaAs collector contact layer (Si-doped; 5 × 10 ¹⁸ cm ⁻³ ) 22 and 200 nm thick nGa
As collector layer (Si-doped; 5 × 10 ¹⁶ cm ⁻³ ) 2
3, p of 70 nm thickness according to the impurity profile shown in FIG.
GaAs base layer (Be, Sb doped) 24, thickness 85
nm nIn _0.49 Ga _0.51 P emitter layer (Si-doped;
5 × 10 ¹⁷ cm ⁻³ ) 25, 100 nm thick nGaAs
A layer 26 and an n ⁺ InGaAs emitter contact layer 27 having a thickness of 100 nm are sequentially stacked, and a metal emitter electrode 31 made of Ti / Pt / Au is formed on the n ⁺ InGaAs emitter contact layer 27 and an upper part of the pGaAs base layer. Metal base electrode 32 made of Ti / Pt / Au
However, AuGe / Ni / is formed on the bottom of the groove formed to reach the n ⁺ GaAs collector contact layer 22.
A metal collector electrode 33 made of Au is formed.
The pGaAs base layer 24 has a Be concentration of 5 as shown in FIG.
The density was × 10 ¹⁹ cm ^-3 and the Sb concentration was 1.25 × 10 ¹⁹ cm ^-3 , which alleviates the reduction of the lattice constant due to Be. Further S
b is nGaAs collector layer 23 and nIn _0.49 Ga
_{The 0.51} P emitter layer 25 and the nGaAs layer 26 are doped to suppress the generation of dislocations in the depletion layer region between the emitter and the base and the depletion layer region between the collector and the base.

The HBT shown in FIG. 4 is manufactured as follows. First, the n ⁺ GaAs collector contact layer 22, the nGaAs collector layer 23, ..., Are formed on the semi-insulating GaAs substrate by the MBE method, the low pressure MOCVD method, the CBE method, or the like.
Successively epitaxially grows sequentially with the n ⁺ InGaAs emitter contact layer 27, and then the U groove for taking out the base electrode is formed by photolithography, that is, the n ⁺ InGaAs emitter contact layer and the GaAs layer are formed using the photoresist as a mask until the pGaAs base layer 24 is reached. 26, nIn _0.49 G _0.51 P emitter layer 25 is formed by etching. At this time, the etching of the nIn _0.49 Ga _0.51 P emitter layer 25 is performed using HCl: H ₂ O or HC.
l: G using a hydrochloric acid-based etchant such as H ₃ PO ₄
Since aAs is hardly etched and InGaP can be selectively etched, the pGaAs base layer 24 functions as an etching stopper and the U groove depth can be accurately controlled. Next, Ti / Pt / Au is vapor-deposited while leaving the photoresist used for the U-groove etching, and then the photoresist is removed by a so-called lift-off method.
A Pt / Au metal base electrode 32 is formed. Then U
The groove is filled with polyimide or the like, a Ti / Pt / Au metal emitter electrode 31 is formed on the n ⁺ InGaAs emitter contact layer 27, and the n ⁺ GaAs collector contact layer 22 is exposed by wet etching to remove AuGe / Ni / The Au collector metal electrode 33 may be formed.

FIG. 5 shows AlG according to the third embodiment of the present invention.
The depth direction impurity concentration distribution (profile) of Be and In concentration of the pGaAs base layer of aAs / GaAsHBT is shown. This HBT has the same structure as that shown in FIG. 4, and is formed on the GaAs substrate sequentially by the MBE method or the like.
⁺ GaAs collector contact layer (Si-doped: 6 × 1)
0 ¹⁸ cm ⁻³ ) 22, nGaAs collector layer (Si doping: 5 × 10 ¹⁶ cm ⁻³ ) 23, pGaAs base layer 24
And Al _0.3 Ga _0.7 As emitter layer (Si-doped:
5 × 10 ¹⁷ cm ⁻³ ) 46 and the like. pG
The Be concentration in the aAs base layer is 5 × 10 ¹⁹ cm ⁻³ , I
The n concentration is 6.6 × 10 ¹⁹ cm ⁻³ , and Ga by Be is Ga.
It is a value that alleviates the As lattice constant reduction. Also, I
n is nAlxGa _1-x As graded layer 45, nAl
_0.3 Ga _0.1 As is doped to the emitter layer 46 side,
It suppresses the generation and multiplication of dislocations in the depletion layer of the emitter-base junction.

The In _0.49 Ga shown in FIGS.
_{In 0.51} P / GaAs HBT, the emitter layer and the base layer are almost lattice-matched, but AlGaAs / GaAs HBT
Cannot lattice match the emitter layer and the base layer. Therefore, in the third embodiment of the present invention, the pGaAs base layer 24 is divided into two layers, and the pGaAs base layer 2 on the collector side is divided into two layers.
4 In the lower layer, the amount of In added is selected so as to compensate for the reduction of the GaAs lattice constant due to Be, and in the upper layer of the pGaAs base layer 24 on the emitter side, the amount of In added is increased and
The base layer is designed to expand.

FIG. 6 shows AlG according to the fourth embodiment of the present invention.
C near the pGaAs base layer of aAs / GaAs HBT
And the distribution of In concentration in the depth direction are shown. This HB
T also has a structure similar to that shown in FIG. 4, and n ⁺ GaAs collector contact layers (Si-doped: 6 × 10 ¹⁸ cm ⁻³ ) 22, nGaA sequentially formed on the GaAs substrate by the MBE method or the like.
s collector layer (Si-doped: 5 × 10 ¹⁶ cm ⁻³ ) 23,
The pGaAs base layer 24 and the Al _0.3 Ga _0.7 As emitter layer (Si-doped: 5 × 10 ¹⁷ cm ⁻³ ) 46 are used. The C concentration in the pGaAs base layer is 5 × 10 ¹⁹ cm ⁻³ , and the In concentration is 1.25 × 10 ¹⁹ cm ^−3.
Is a value that alleviates the reduction of the GaAs lattice constant due to C single doping. In the fourth embodiment, In is extruded and doped on both the emitter side and the collector side to suppress the generation and multiplication of dislocations in the depletion layer of the emitter-base junction and the base-collector junction. In the fourth embodiment, the doping amount of In is increased so as to increase on the AlGaAs emitter side, and the doping amount of the peak is set to 3 × 10 ²⁰ cm ⁻³ .

FIG. 7 shows AlG according to the fifth embodiment of the present invention.
Z in the vicinity of the pGaAs base layer of aAs / GaAs HBT
The depth direction distribution of n and P concentration is shown. This HB
T has the same structure as in FIG. 4, and MOCV is formed on the GaAs substrate.
N ⁺ GaAs collector contact layer (Si doping: 6 × 10 ¹⁸ cm ⁻³ ), nGaA sequentially formed by the D method or the like
s collector layer (Si-doped: 5 × 10 ¹⁶ cm ⁻³ ) 23,
The pGaAs base layer 24 and the Al _0.3 Ga _0.7 As emitter layer (Si-doped: 5 × 10 ¹⁷ cm ⁻³ ) 46 are used. Zn in the pGaAs base layer 24
The concentration is 5 × 10 ¹⁹ cm ^-3 , and the P concentration is 2.5 × 10 ¹⁹ cm 3.
^-3, which is a value that alleviates the GaAs lattice constant expansion when Zn is solely doped. In the fifth embodiment, the P concentration of the pGaAs base layer 24 is reduced on the emitter layer side so that the lattice constant expansion due to Zn doping is dominant, and the lattice constant in the pGaAs base layer is on the AlGaAs emitter layer side. It is supposed to inflate. Further, P is doped so as to extend to the nAl _x Ga _{1- x} As graded layer 45 and the nGaAs collector layer 23, so that the generation of dislocations in the air-system layer at the emitter-base junction and the base-collector junction occurs. Prevents proliferation. Alternatively, the pGaAs base layer 24 is divided into two, the collector layer side is doped with Zn and P, the emitter layer side is doped with Zn and Sb, the collector layer side compensates for lattice distortion due to Zn, and both are shared on the emitter layer side. The lattice may be expanded by Zn and Sb having an engagement radius larger than that of the matrix.

FIG. 8 shows AlG according to the sixth embodiment of the present invention.
The depth distribution of C and Sb concentrations in the vicinity of the pGaAs base layer 24 of aAs / GaAsHBT is shown. This HBT has the same structure as in Fig. 4, and MB is formed on the GaAs substrate.
N ⁺ GaAs collector contact layer (Si doping: 6 × 10 ¹⁸ cm ⁻³ ) 22, nG sequentially formed by the E method or the like
aAs collector layer (Si-doped: 5 × 10 ¹⁶ cm ⁻³ ) 2
3, pGaAs base layer 24 and Al _0.3 Ga _0.7 A
The s emitter layer (Si-doped: 5 × 10 ¹⁷ cm ⁻³ ) 46 and the like. The C concentration in the pGaAs base layer 24 is 5 × 10 ¹⁹ cm ⁻³ , and the Sb concentration is 1.45 × 10.
^{It is 20} cm ^−3, which is a value that alleviates the lattice constant reduction due to C. Sb is extruded and doped to the nAlxGa _1-x As graded layer 45 and the nGaAs collector layer 23 side to prevent generation of dislocations in the depletion layer at the emitter-base junction and the base-collector junction. There is.

FIG. 9 shows AlG according to the seventh embodiment of the present invention.
It is a typical sectional view of aAs / GaAsHBT. FIG.
However, a plurality of lines in the pGaAs base layer 24 schematically show the molecular layer surface. That is, pGa
The As base layer 24 is a so-called non-doped layer in which the Ga surface 241 is not intentionally doped with impurities.
2. Sb 3.97 × 10 ¹² cm ⁻² , C 1.4 × 10
¹² cm ^-2 doped GaAs layers totaling 247 layers or 6 layers
This is the case where the film has a thickness of 9.9 nm. Lattice distortion can be accurately compensated by controlling in atomic layer units.

The structure of FIG. 9 can be realized by using the MLE method (Molecular Layer Epitaxy method). That is, TEG (triethylgallium) and AsH
GaAs by one cycle of alternating introduction with ₃ (arsine)
A monolayer grows, but at this time, Si ₂ H occurs simultaneously with TEG.
By introducing ₆ (disilane), the n ⁺ GaAs collector contact layer 22 and the nGaAs collector layer 23 can be grown. Next, the growth of the pGaAs base layer 24 is TMG.
Using (trimethylgallium) as a source gas for C doping, TEG 4 seconds introduction, 2 seconds vacuum exhaust, TMG 1 second introduction, vacuum exhaust 2 seconds, SbH ₃ (stibine) · AsH ₃
When a cycle of simultaneous introduction for 3 seconds, AsH ₃ alone introduction for 10 seconds, and vacuum evacuation for 3 seconds for a total of 25 seconds was repeated 247 times, the As plane 242 was doped with C and Sb and the lattice strain was relaxed p.
The GaAs base layer 24 is formed. Then TEIn
(Triethyl indium), TEG, doped SbH ₃ when in alternating introduction of PH ₃ (phosphine), form a nIn _0.49 Ga _{0. 51} P emitter layer 25 which is doped Sb, thereafter TEG and AsH ₃ alternately introduced nGaAs layer 2
6, TEIn, TEG, and AsH ₃ are alternately introduced into n ⁺ In
_{The 0.5} G _0.5 As emitter contact layer 27 may be formed. Si ₂ H ₆ and SbH ₃ are also used as the dopant gas for the nGaAs layer 26, n ⁺ In _0.5 G _0.5 As emitter contact layer 27, and TEG, Si ₂ H _{6 are} simultaneously introduced, vacuum exhaust, SbH ₃ , AsH _{3 are} simultaneously introduced, and vacuum is applied. A mode called exhaust may be used. DEZn (diethyl zinc), DBBe as a dopant gas for the pGaAs base layer 24
(Dibutyl beryllium C ₈ H ₁₈ Be) is used, and Ga surface 2
41 is doped with Zn or Be, and As plane 2
42 may be doped with Sb. If an MLE device equipped with a Knudsen cell is used, metal Be can be used as a dopant source. If the group III site is replaced with a dopant element, it is preferable that the group III site is similarly doped with another group III element having a different covalent radius. For example, in a mode of simultaneous introduction of TMZn, TMIn and TEG, evacuation, introduction of AsH ₃ and evacuation, the Ga face 241 is doped with Zn and In, and the As face 242 is not doped by doping in atomic layer units. You may.

In addition to this, the same effect can be obtained by adding various Group III and V elements at the same time as the dopant element.
Further, the same effect can be obtained not only by one kind but also by adding a plurality of group III and group V elements simultaneously or in different regions or different atomic layer planes.

Further, since it is possible to control the doping in atomic layer units or molecular layer units by using the MLE method, the first 100 molecular layers of the pGaAs base layer 247 molecular layers of FIG. The next 47 molecular layers are Zn and Be doped layers, and the 100 molecular layer on the next 47 molecular layers are Be and In doped layers.
It is possible to dope by sandwiching n in a sandwich shape. If doped in this way, no lattice distortion occurs and no abnormal diffusion occurs even at a high concentration of about 5 × 10 ²⁰ cm ^-3 . The hole mobility at room temperature (300K) is also 3 × 10 ²⁰ c
The value was as high as 70 cm ² / V · sec at m ⁻³ .

Also, 11 molecular layers are Be-doped, 8 molecular layers are In-doped, 11 molecular layers are Be-doped, and 8 molecular layers are I-doped.
Lattice strain can be compensated even when doped with a period of 19 molecular layers such as n-doped.

Further, when an nAlGaAs emitter layer is used instead of the nIn _0.49 G _0.51 P emitter layer 25 in FIG. 9, since the lattice constant of AlGaAs is larger than the lattice constant of GaAs, the lower 100 molecular layers of the 247 molecular layers are Be and In are doped on the Ga face 241 so as to compensate for lattice strain with GaAs, and the 147 molecular layer on it increases the In doping amount, and at the same time, the As face 242 is doped with Sb,
If the doping amounts of In and Sb are gradually increased so that the lattice spacing is gradually expanded, the AlGaAs emitter layer and Ga
The lattice strain with the As base layer is relaxed.

[0039]

As described above, according to the first feature of the present invention, the lattice strain and internal stress in the base layer are alleviated, and the generation and multiplication of dislocations in the emitter-base junction are suppressed. Therefore, the generation of process-induced defects is suppressed, and at the same time, the base current, which is a leak component such as a tunnel current via the recombination center in the emitter-base junction, is also reduced. As a result, the current gain of the HBT increases and the 1 / f noise decreases. Further, in the manufacturing process, variations in characteristics within the wafer and within the lot can be suppressed. As a result, the HBT becomes highly reliable, and its MTTF is 200 ° C., 10 ⁵ A /
A value of 10 ⁶ hours was achieved in measuring the current density in cm ² . In addition, the lattice strain in the base layer and the emitter
Dislocations near the base junction are suppressed, epitaxial growth can be performed at a lower temperature, the impurity profile of HBT becomes sharper, and it becomes suitable for high-speed / high-frequency operation. Since dislocations in the vicinity of the emitter / base junction are suppressed, abnormal diffusion at the junction interface is eliminated, the process design is facilitated, and the HBT frequency can be increased.

According to the second feature of the present invention, in addition to the above effects, dislocations and recombination centers in the base-collector junction are reduced, the base-collector leakage current is reduced, and the breakdown voltage is improved. Long life and high reliability are obtained in high power operation.

According to the third feature of the present invention, in addition to the above effects, misfit dislocations at the heterojunction between the emitter and the base are prevented, and an HBT with low noise and long life can be obtained.

[Brief description of drawings]

FIG. 1 is a concentration distribution diagram in the vicinity of a base layer of an HBT according to a first embodiment of the present invention.

FIG. 2 is a sectional view of the HBT according to the first embodiment of the present invention.

FIG. 3 is a concentration distribution diagram in the vicinity of the base layer of the HBT according to the second embodiment of the present invention.

FIG. 4 is a sectional view of an HBT according to a second embodiment of the present invention.

FIG. 5 is a concentration distribution diagram in the vicinity of the base layer of the HBT according to the third embodiment of the present invention.

FIG. 6 is a concentration distribution diagram in the vicinity of a base layer of HBT according to a fourth embodiment of the present invention.

FIG. 7 is a concentration distribution diagram in the vicinity of a base layer of HBT according to a fifth embodiment of the present invention.

FIG. 8 is a concentration distribution diagram in the vicinity of a base layer of HBT according to a sixth embodiment of the present invention.

FIG. 9 is a schematic sectional view of an HBT according to a seventh embodiment of the present invention.

[Explanation of symbols]

1 In concentration 2 Be concentration 3 Sb concentration 4 C concentration 5 Zn concentration 6 P concentration 21 Semi-insulating GaAs substrate 22 n ⁺ GaAs collector contact layer 23 nGaAs collector layer 24 pGaAs base layer 25 nIn _0.49 Ga _0.51 P emitter layer 26 nGaAs layer 45 nAl _x Ga _1-x As graded layer 46 nAl _0.3 Ga _0.7 As emitter layer 47 nAl _x Ga _1-x As graded layer 48 n ⁺ In _y Ga _1-y As graded layer 27 n ⁺ In _0.5 Ga _0.5 As emitter contact layer 31 emitter electrode 32 base electrode 33 collector electrode 34 polyimide 35 element isolation region 241 Ga surface 242 As surface

Claims (8)

[Claims] 1. A bipolar transistor using a III-V group compound semiconductor, wherein the base layer contains an electrically active first impurity element that imparts conductivity to the base layer,
A second impurity element, which is electrically neutral to the III-V group compound semiconductor, is added to the base layer and the emitter layer near the base layer in a range of 0.02 times to 30 times that of the first impurity element. A heterojunction bipolar transistor characterized by including a small amount. 2. A bipolar transistor using a III-V group compound semiconductor, wherein the base layer contains an electrically active first impurity element that imparts conductivity to the base layer,
The second impurity element, which is electrically neutral to the III-V group compound semiconductor, is in the range of 0.02 to 30 times that of the first impurity element in the base layer, the emitter layer near the base layer, and , A heterojunction bipolar transistor characterized by including at least a collector layer near the base layer. 3. The heterojunction bipolar transistor according to claim 1, wherein the second impurity element is nonuniformly doped in the base layer. 4. The first impurity element is Be, the second impurity element is In, and In is 0.1 with respect to Be.
The heterojunction bipolar transistor according to claim 1 or 2, wherein the heterojunction bipolar transistor has a region doped in a range of 1 to 11 times. 5. The first impurity element is Be, the second impurity element is Sb, and Sb is 0.0 with respect to Be.
The heterojunction bipolar transistor according to claim 1 or 2, wherein the heterojunction bipolar transistor has a region doped in a range of 25 to 2.5 times. 6. The first impurity element is C, and the second impurity element is C.
Is an impurity element of In, and In is 0.24 to
The heterojunction bipolar transistor according to claim 1 or 2, wherein the heterojunction bipolar transistor has a region doped in a range of 24 times. 7. The first impurity element is Zn, the second impurity element is P, and P is 0.05 to 0.05 with respect to Zn.
The heterojunction bipolar transistor according to claim 1 or 2, wherein the heterojunction bipolar transistor has a region doped in a range of 5 times. 8. The first impurity element is C, and the second impurity element is C.
The impurity element of is Sb, and Sb is 0.27 to C with respect to
The heterojunction bipolar transistor according to claim 1 or 2, wherein the heterojunction bipolar transistor has a region doped in a range of 27 times.