JPH0878620A - Power semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] To provide a power semiconductor device capable of preventing a warp of the mounting substrate 1 and processing a large current in a region including a high frequency region. [Structure] Semiconductor unit unit 2 mounted on mounting board 1
In the power semiconductor device having the mounting substrate 1 covered with a hermetically sealed container having external lead-out terminals, the unit unit 2 has one or more semiconductor chips 4 to 6 arranged on the insulating substrate 3 in a junction arrangement.
And a plurality of electrode patterns 7 to 9 arranged on the insulating substrate 1 in a joined arrangement.
, A plurality of metal wires 10 for connection, and a plurality of terminal connection parts 1
1 to 13 and a plurality of internal connection terminals that connect the terminal connection portions 11 to 13 and the lead-out terminal, the number of unit units is two or more, and the terminal connection portion 11 on the first main electrode side of the unit unit 2 and Any of the two main electrode-side terminal connecting portions 12 is arranged in proximity to each other, and is separated from the control electrode-side terminal connecting portion 13 of the unit unit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device having a modular structure which can be used in a high frequency band and can process a large amount of power.

[0002]

2. Description of the Related Art Conventionally, IGBTs have been used for power semiconductor devices.
There is known a module structure in which a power semiconductor switching element such as (insulated gate bipolar transistor), diode, GTO thyristor (gate turn-off thyristor), and power transistor is sealed in an insulating container. This power semiconductor device having a module structure is used in various inverter devices and the like in accordance with the withstand voltage and current capacity characteristics of a built-in power semiconductor switching element. Among them, as a power semiconductor switching element, an IGBT is used. A power semiconductor device having a module structure including a power supply is used as a control circuit for various power devices from the viewpoint that the IGBT is a voltage-controlled type, and therefore is easy to control and can process a large current in a high frequency region. Many are used.

Here, a power semiconductor device having a module structure including a power semiconductor switching element such as an IGBT is usually made of alumina (Al ₂ O ₃ ) or aluminum nitride (Al ₂ O ₃ ) on a mounting substrate made of a copper (Cu) plate or the like. AIN)
A ceramic insulating substrate made of, for example, is bonded, a semiconductor chip, an electrode pattern, a terminal portion, and the like are formed on the insulating substrate, and required wiring processing is performed between them. Then, the surface of the semiconductor chip or the electrode pattern is covered with a coating material such as a gel-like resin, and then an epoxy resin or the like is injected and cured, and the mounting substrate is sealed in a resin-made hermetic container. It was done.

By the way, in an apparatus for processing a large amount of electric power, such as an inverter apparatus, in order to obtain a large drive current, normally, the above-mentioned module-structured electric power semiconductor devices are connected in parallel and used. There is. However, in the case where such power semiconductor devices are connected in parallel, the current flowing between the power semiconductor devices of the module structure is likely to be unbalanced, the resonance phenomenon is likely to occur due to the current flow, and the mounting area is large. Due to such reasons, various problems such as the limit of 2 to 4 power semiconductor devices having a module structure that can be connected in parallel occur. Therefore, in order to increase the drive current of the inverter device, etc.,
Rather than using a plurality of power semiconductor devices having a module structure of a relatively small current capacity connected in parallel, a power semiconductor device of a module structure having a large current capacity is formed, and one power semiconductor device of this module structure is formed. It would be preferable to use it alone.

Generally, in order to increase the current capacity of a power semiconductor device having a module structure, the effective area of a semiconductor chip must be increased. In this case, in a power semiconductor switching element such as an IGBT, in order to increase its effective area, a plurality of IGBT chips having the same characteristics are prepared, and these are mounted in the same module structure, so that the current consumption is reduced as a whole. It is intended to obtain a power semiconductor device having one module structure with increased capacity.

In the power semiconductor device having such a module structure, in order to avoid the occurrence of current imbalance between a plurality of IGBT chips, two IGBT chips connected in parallel are connected from the emitter internal terminal to the insulating substrate. The distances to the top are equivalently made approximately equal,
Means for avoiding the occurrence of current imbalance between T chips has already been disclosed in Japanese Patent Laid-Open No. 61-139051.

[0007]

In the known power semiconductor device having the module structure, if the number of semiconductor chips to be connected in parallel is increased in order to further increase the current value that can be processed in the device, a plurality of semiconductor chips can be provided. There is a problem that the imbalance of the current value between the semiconductor chips cannot be avoided.

The device disclosed in Japanese Patent Laid-Open No. 61-139051 has, for example, eight or more semiconductor chips (IGBT chips) arranged in parallel in order to increase the current capacity of a power semiconductor device having a module structure. In this case, as a means for avoiding the occurrence of the imbalance of the current value between the IGBT chips, in order to make the distances from the emitter internal terminals to the insulating substrate substantially equal to each other for eight or more IGBT chips, If the IGBT chips are arranged in a circle around the emitter internal terminal, I
There is a problem that the mounting efficiency of the GBT chip is reduced and the volume of the power semiconductor device having a module structure is increased, and the reduction of the mounting efficiency is increased as the number of IGBT chips connected in parallel increases. is there.

Further, when one semiconductor unit unit having a plurality of semiconductor chips is mounted on the mounting board as disclosed in the above-mentioned JP-A-61-139051, an undesired warp is formed on the mounting board. There is also a problem that occurs.

Further, in the one disclosed in the above-mentioned Japanese Patent Laid-Open No. 61-139051, when the current capacity of the power semiconductor device having the module structure is increased, any consideration is given to the point of enabling a large current operation in a high frequency region. There is a problem of not being paid.

The present invention is intended to solve the above-mentioned problems, and an object thereof is to prevent warpage of a mounting substrate and to process a large current in a region including a high frequency region. To provide a device.

[0012]

To achieve the above object, the present invention covers a mounting board, a semiconductor unit unit mounted on the mounting board, and a mounting board on which the semiconductor unit unit is mounted. In a power semiconductor device having a hermetically sealed container and a plurality of external lead-out terminals provided in the hermetically sealed container, the semiconductor unit unit includes an insulating substrate,
One or more semiconductor chips bonded and arranged on the insulating substrate, a plurality of electrode patterns bonded and arranged on the insulating substrate and provided corresponding to the semiconductor chips, the semiconductor chips, and the plurality of semiconductor chips. A plurality of metal wires bridgingly connected between the electrode patterns and a plurality of terminal connecting portions which are jointly arranged on the insulating substrate and are conductively connected to any of the plurality of electrode patterns, and these terminal connecting portions. The semiconductor chip is composed of internal connection terminals that are conductively connected to the corresponding external lead-out terminals, and the number of the semiconductor unit units mounted on the mounting substrate is two or more, and the semiconductor chips bonded to each semiconductor unit unit are arranged. A first means is provided which has two or less of the same function.

In order to achieve the above object, the present invention provides a mounting substrate, a semiconductor unit unit mounted on the mounting substrate, and a hermetic container covering the mounting substrate mounting the semiconductor unit unit. In a power semiconductor device having a plurality of external lead-out terminals provided in the hermetically sealed container, the semiconductor unit unit includes an insulating substrate, one or more semiconductor chips bonded and arranged on the insulating substrate, and the insulating unit. A plurality of electrode patterns that are arranged on the substrate so as to correspond to the semiconductor chips; a plurality of metal wires that are bridge-connected between the semiconductor chips and the plurality of electrode patterns; and the insulating substrate. A plurality of terminal connecting portions which are arranged on the upper side and are conductively connected to any of the plurality of electrode patterns, and these terminal connecting portions are conductively connected to the corresponding external lead terminals. Two or more semiconductor unit units mounted on the mounting substrate, each of which has an internal connection terminal, and a terminal connection portion connected to an external lead terminal serving as a first main electrode of each semiconductor unit unit; Any one of the terminal connecting portions connected to the external lead-out terminals that will be the second main electrodes of the semiconductor unit units is arranged in close proximity and connected to the external lead-out terminals that will be the control electrodes of the semiconductor unit units. The second means is arranged so as to be spaced apart from each of the terminal connecting portions.

[0014]

According to the first means, since two or less semiconductor chips having the same function are jointly arranged in each semiconductor unit unit, the current flowing in each semiconductor unit unit is relatively small. Therefore, the impedance from each semiconductor chip to the corresponding internal connection terminal and the impedance from each internal connection terminal to the external lead-out terminal can be made uniform.
When a large number of semiconductor chips connected in parallel are provided in one semiconductor unit unit, it becomes possible to make the static characteristics and dynamic characteristics uniform among the semiconductor chips, and for power supply with large current capacity. A semiconductor device can be obtained.

Further, according to the first means, since two or more semiconductor unit units are mounted on the mounting substrate,
It is possible to reduce the warp of the mounting substrate that occurs when the semiconductor unit unit is joined to the mounting substrate, and to obtain a comparatively small semiconductor unit unit, such as solder that occurs when the semiconductor unit unit is joined to the mounting substrate. The occurrence of voids in the brazing filler metal is also reduced.

Further, according to the first means, since two or more semiconductor unit units are mounted on the mounting substrate, the number of internal connection terminals connected to one external lead-out terminal is increased, and the actual number of internal connection terminals is increased. Thermal stress at the time of driving and mechanical stress at the time of tightening the external connection terminal are dispersed, respectively, and large thermal stress and mechanical stress are applied between the terminal connection part of the semiconductor unit unit and the internal connection terminal. Therefore, the connection state between the terminal connection portion and the internal connection terminal is less likely to deteriorate.

According to the second means, in addition to the function obtained by the first means, the terminal connecting portion connected to the external lead-out terminal which becomes the first main electrode of each semiconductor unit unit, and each semiconductor. Since any one of the terminal connecting portions connected to the external lead-out terminal which is the second main electrode of the unit unit is arranged in proximity, the terminal connecting portions arranged in proximity to each other become the first main electrode. Mutual inductance is formed between the internal lead-out terminals and the internal lead-out terminals connected to the external lead-out terminals to be the second main electrode, and the mutual inductance substantially reduces the inductance of the internal lead-out terminals. Thus, it becomes possible to operate in a high frequency region, and a large current can be switched at a high speed.

Further, according to the second means, each terminal connecting portion connected to the external lead-out terminal which becomes the control electrode of each semiconductor unit unit and the external lead-out terminal which becomes the first and second main electrodes are connected. Since each terminal connection part is separated from each other, it is possible to reduce noise mixing into the control electrode and suppress the occurrence of the voltage rising phenomenon when switching a large current at a high speed. .

[0019]

Embodiments of the present invention will now be described in detail with reference to the drawings.

1 and 2 are structural views showing a first embodiment of a power semiconductor device according to the present invention. FIG. 1 is a top view thereof, and FIG. 2 (a) is shown in FIG. FIG. 2B is a cross-sectional view taken along the line AA ′ in the top view, and FIG. 2B is a cross-sectional view taken along the line BB ′ in the top view shown in FIG. 1. The power semiconductor device has a module structure as a whole. It shows an example of doing.

In FIGS. 1 and 2A and 2B, 1
Is a common mounting substrate, 2 is a semiconductor unit unit, 3 is an insulating substrate, 4 is an IGBT chip (semiconductor chip), 5 is a diode chip (semiconductor chip), 6 is a resistor chip (semiconductor chip), and 7 is a collector electrode pattern. Cathode electrode pattern (hereinafter, referred to as collector electrode pattern), 8 is an emitter electrode pattern and anode electrode pattern (hereinafter, referred to as emitter electrode pattern), 9 is a gate electrode pattern, 10 is a metal wire, 11 is a collector terminal connection , 12 is an emitter terminal connecting portion, 13 is a gate terminal connecting portion, 14 is a bonding layer, 15 is a collector internal connecting terminal, 15c is a connecting portion between the collector internal connecting terminal 15 and the collector external lead-out terminal 18, and 15h is inside the collector. A vertically extending portion of the connection terminal 15, 15v is a horizontally extending portion of the collector internal connection terminal 15, 1v Emitter internal connection terminals, 16
c is a connecting portion between the emitter internal connection terminal 16 and the emitter external lead-out terminal 19, 16h is a vertically extending portion of the emitter internal connecting terminal 16, 16v is a horizontal extending portion of the emitter internal connecting terminal 16, 17 is a gate internal connecting terminal, 18 Is a collector external lead-out terminal, 19 is an emitter external lead-out terminal, 20 is a sealed container, 21 is a resin terminal plate, 22 is a hard resin, and 23
Is a coating material such as a gel resin.

The mounting substrate 1 is composed of a metal plate such as copper (Cu), and a plurality of semiconductor unit units 2, in this embodiment, four semiconductor unit units 2 are mounted thereon. The semiconductor unit unit 2 has an insulating substrate 3 made of alumina (Al ₂ O ₃ ) or aluminum nitride (AlN) or the like, and a bonding layer 14 made of a silver (Ag) brazing material is provided on the insulating substrate 3. Then, the collector electrode pattern 7, the emitter electrode pattern 8 and the gate electrode pattern 9 which are made of a thin plate made of copper (Cu) or a composite thin plate made of copper (Cu) -molybdenum (Mo) -copper (Cu), etc. are jointly arranged. It Two IGBTs are formed on the collector electrode pattern 7.
The chip 4 and the two diode chips 5 are jointly arranged, and the two resistor chips 6 are jointly arranged on the gate electrode pattern 9. In this case, the emitter electrode pattern 8, the IGBT chip 4, the diode chip 5, the resistor chip 6 and the gate electrode pattern 9 are arranged in tandem on one side of the insulating substrate 3, and also on the other side of the insulating substrate 3. The emitter electrode pattern 8, the IGBT chip 4, the diode chip 5, the resistor chip 6, and the gate electrode pattern 9 are arranged in a column. The collector terminal connecting portion 11, the emitter terminal connecting portion 12, and the gate terminal connecting portion 13 are all arranged in the central portion of the insulating substrate 3 between the two column arrangements, of which the collector terminal connecting portion 11 and the emitter are connected. The gate terminal connecting portion 13 is disposed close to the terminal connecting portion 12, and the gate terminal connecting portion 13 is the collector terminal connecting portion 11 or the emitter terminal connecting portion 1.
It is arranged apart from 2. The collector terminal connecting portion 11 is conductively connected to the collector electrode pattern 7, the emitter terminal connecting portion 12 is conductively connected to the two emitter electrode patterns 8, and the gate terminal connecting portion 13 is conductively connected to the two gate electrode patterns 9. Between the plurality of emitter bonding pads (not shown) of the IGBT chip 4 and the emitter electrode pattern 8, between the plurality of anode bonding pads (not shown) of the diode chip 5 and the emitter electrode pattern 8
And a plurality of metal wires 10 are bridge-connected to each other, and one metal is provided between a common gate bonding pad (not shown) of the IGBT chip 4 and one bonding pad (not shown) of the resistor chip 6. The wire 10 is bridge-connected.

Further, the collector internal connection terminal 15 and the emitter internal connection terminal 16 are respectively provided in the horizontal extending portion 15
h, 16h and vertical extending portions 15v, 16v, which are bent, and have their lower portions conductively joined to the collector terminal connecting portion 11 and the emitter terminal connecting portion 12, respectively. In this case, the vertical extending portions 15v and 16v are configured to be arranged close to each other, and the horizontal extending portions 15h and 16h are configured to project in a direction in which they are separated from each other. The gate internal connection terminal 17 also has a bent configuration similar to that of the collector internal connection terminal 15 and the emitter internal connection terminal 16, and the lower portion thereof is the gate terminal connection portion 13
Is conductively joined to. The collector external lead-out terminal 18 and the emitter external lead-out terminal 19 are both provided on the terminal plate 21, and the lower portion of the collector external lead-out terminal 18 and the upper portion of the collector internal connection terminal 15 are conductively connected by the connecting portion 15c. A lower portion of the emitter external lead-out terminal 19 and an upper portion of the emitter internal connection terminal 16 are conductively connected to each other by a connection portion 16c.
In FIG. 2B, the collector internal connection terminals 15 of the two semiconductor unit units 2 are conductively connected to the collector external lead-out terminal 18 via the connection portion 15c, and similarly, the two semiconductor unit units 2 are connected together. Although the emitter internal connection terminals 16 are electrically conductively connected to the emitter external lead-out terminals 19 via the connection portions 16c, in reality, the collector internal connection terminals 15 of the four semiconductor unit units 2 are connected to the connection portions 1 respectively.
5c is conductively connected to the collector external lead-out terminal 18, and similarly, the four emitter unit internal connection terminals 16 of the semiconductor unit units 2 are conductively connected to the emitter external lead-out terminal 19 via the connecting portion 16c. The gate internal connection terminal 17 of the semiconductor unit unit 2 is also conductively connected to the gate external lead-out terminal (not shown) in common.

Further, the mounting substrate 1 is covered with a hermetically sealed container 20 in a state in which four semiconductor unit units 2 are mounted, and the surface of each semiconductor unit unit 2 is coated with a coating material 23 such as gel resin. Then, the hard resin 22 is formed by curing the epoxy resin or the like filled in the sealed container 20.

Here, FIG. 3 is a diagram of FIG. 1 and FIG.
2B is an electrically equivalent circuit shown by the power semiconductor device of the first embodiment shown in FIG.

In FIG. 3, L1 is the inductance exhibited by the collector internal connection terminal 15, L2 is the inductance exhibited by the emitter internal connection terminal 16, and L3 is the connection portion 15.
c is the inductance, L4 is the inductance that the connecting portion 16c exhibits, and in addition, FIG. 1 and FIG.
The same components as those shown in (a) and (b) are designated by the same reference numerals.

According to the power semiconductor device having the above-mentioned structure, first, in each of the semiconductor unit units 2, one IGBT chip 4 has a collector and an emitter has one diode chip 5 which has a cathode and an anode, respectively. Connected, that is, one set of IGBT chips 4
And the diode chip 5 are connected in parallel, another pair of the IGBT chip 4 and the diode chip 5 are further connected in parallel, and the collector side of the two IGBT chips 4 and the two diode chips 5 are connected. The cathode side is commonly connected to the collector terminal connecting portion 11, and the emitter sides of the two IGBT chips 4 and the anode sides of the two diode chips 5 are commonly connected to the emitter terminal connecting portion 12. Further, in the four semiconductor unit units 2, the collector terminal connecting portion 11 has the connecting portion 15c through the inductance L1 exhibited by the collector internal connecting terminal 15.
Connected to the collector external lead-out terminal 18 via the inductance L3 of the connecting portion 15c, and the emitter terminal connecting portion 12 connects to the connecting portion 16 via the inductance L2 of the internal emitter connecting terminal 16.
c, and is then commonly connected to the emitter external lead-out terminal 19 via the inductance L4 provided by the connecting portion 16c. In this way, the collector external lead-out terminal 18
Between the emitter external lead-out terminal 19, two IGBT chips 4 and five diode chips 5 are provided in parallel in each of the four semiconductor unit units 2, two in total. In this case, for example, the peak current that can flow in each IGBT chip 4 is set to 20
If it is 0 A, the peak current that can flow in each semiconductor unit unit 2 is 400 A, and the peak current that can flow in the entire four semiconductor unit units 2 is 1600 A. A semiconductor device for use can be formed.

As described above, according to the first embodiment, the number of semiconductor chips having the same function, for example, the IGBT chip 4, the diode chip 5, and the resistance chip 6 provided in one semiconductor unit unit 2 is two, respectively. Therefore, the current flowing through each of the semiconductor unit units 2 becomes relatively small, and the collector of the IGBT chip 4 (cathode of the diode chip 5) to the collector internal connection terminal 15
And the impedance between the collector external lead-out terminal 18 via the connection portion 15c and the emitter external lead-out terminal 19 from the emitter of the IGBT chip 4 (the anode of the diode chip 5) via the emitter internal connection terminal 16 and the connection portion 16c. Can be made to have a uniform impedance, and when a large number of semiconductor unit units 2 are mounted on a common mounting substrate 1, static and dynamic characteristics between the IGBT chips 4 in each semiconductor unit unit 2 can be obtained. Can be made uniform, and it becomes easy to realize a power semiconductor device having a large current capacity.

Further, according to the first embodiment, since a plurality of semiconductor unit units 2 each having a relatively small current capacity, here four semiconductor unit units 2, are mounted on the common mounting substrate 1, Since the heat generation during operation of the power semiconductor device is small and dispersed, the mounting substrate 1 made of metal (copper)
Since warp is less likely to occur and the area occupied by one semiconductor unit unit 2 is relatively small, when the semiconductor unit unit 2 is brazed to the mounting substrate 1, there are few voids in the brazing filler metal. Become.

Further, according to the first embodiment, each semiconductor unit unit 2 is provided with the collector internal connection terminal 15, the emitter internal connection terminal 16, and the gate internal connection terminal 17, respectively, and the semiconductor unit unit is provided. Since the number of these internal connection terminals 15 to 17 in 2 is large, the thermal stress at the time of actual driving and the mechanical stress at the time of fastening the external lead-out terminals 18 and 19 are dispersed, and these internal connection terminals 1
The deterioration of the joints between the terminal connection parts 11 to 13 and the corresponding parts 5 to 17 is reduced.

Further, according to the first embodiment, the collector terminal connecting portion 11 and the emitter terminal connecting portion 12 are arranged close to each other,
Further, since the vertically extending portion 15v of the collector internal connecting terminal 15 and the vertical extending portion 16v of the emitter internal connecting terminal 16 are similarly arranged close to each other, the inductance L1 exhibited by the collector internal connecting terminal 15 and the emitter internal connecting terminal 16 are exhibited. Mutual inductance works between the inductances L2 and between the inductance L3 exhibited by the connecting portion 15c and the inductance L4 exhibited by the connecting portion 16c, and these inductances L1 to L4 are reduced, and the inductances L1 to L4 and the current change rate di / It is possible to suppress the occurrence of the voltage jumping phenomenon at the time of high-speed switching of a large current proportional to the product of dt. here,
As described above, in order to effectively reduce the inductances L1 to L4 by the action of the mutual inductance, as shown in FIG.
It is preferable that the distance 1 between the internal connection terminal 5 and the emitter internal connection terminal 16 be within twice the width w of the collector internal connection terminal 15 or the emitter internal connection terminal 16. On the other hand, since the gate terminal connecting portion 13 is arranged apart from the collector terminal connecting portion 11 and the emitter terminal connecting portion 12, switching noise is mixed into the gate internal connecting terminal 17 when switching a large current at a high speed. Can be reduced.

Further, according to the first embodiment, the vertically extending portion 15v of the collector internal connecting terminal 15 and the vertical extending portion 16v of the emitter internal connecting terminal 16 are arranged close to each other, and the horizontal extending portion of the collector internal connecting terminal 15 is arranged. Since 15h and the horizontally extending portion 16h of the emitter internal connection terminal 16 are arranged in a direction away from each other, the height of the bent portion for absorbing the internal stress becomes low, and the gel-like material to be filled in the sealed container 20 is formed. The amount of the coating material 23 such as resin can be reduced, and the thermal reliability can be improved. In addition, a short circuit between the collector internal connection terminal 15 and the emitter internal connection terminal 16 due to thermal or mechanical displacement in the vertical extending portion 15v direction of the collector internal connecting terminal 15 and the vertical extending portion 16v direction of the emitter internal connecting terminal 16. The occurrence can be extremely reduced.

Continuing with FIG. 5, the collector internal connection terminal 15 is shown.
FIG. 6 is a cross-sectional view showing a second example of the arrangement structure of the emitter internal connection terminal 16;

In FIG. 5, the same components as those shown in FIG. 2B are designated by the same reference numerals.

The difference between the structure of the second example (hereinafter, referred to as the second structure example) and the structure shown in FIG. 2B (hereinafter, referred to as the first structure example) is the collector. Regarding the configuration of the horizontal extending portion 15h of the internal connecting terminal 15 and the horizontal extending portion 16h of the emitter internal connecting terminal 16, in the first structural example, the extending directions of the horizontal extending portion 15h and the horizontal extending portion 16h are opposite to each other. In contrast to the configuration in which they are separated from each other, the second structural example is different only in the configuration in which the extending directions of the horizontal extending portion 15h and the horizontal extending portion 16h are the same and they are close to each other. However, other than that, there is no structural difference between the second structural example and the first structural example.

According to this second structure example, similarly to the first structure example, the inductance L1 exhibited by the collector internal connection terminal 15, the inductance L2 exhibited by the emitter internal connection terminal 16, the inductance L3 exhibited by the connecting portion 15c,
The inductance L4 exhibited by the connecting portion 16c can be reduced.

Further, according to the second structure example, the collector internal connecting terminal 15 and the collector internal connecting terminal 16 are integrally formed with the insulating material sandwiched therebetween, and the collector internal connecting terminal 15 and the collector internal connecting terminal 16 are formed. Can be made narrower than that of the first structure example, so that an increase in mutual inductance causes the inductance L1 exhibited by the collector internal connection terminal 15 and the emitter internal connection terminal 16 to be increased.
It is possible to further reduce the inductance L2 exhibited by.

Next, FIG. 6 shows a collector internal connection terminal 15
FIG. 7 is a cross-sectional view showing a third example of the arrangement structure of the emitter internal connection terminal 16;

In FIG. 6, the same components as those shown in FIG. 2B are designated by the same reference numerals.

The difference between the structure of the third example (hereinafter referred to as the third structure example) and the structure example (first structure example) shown in FIG. 2B is the collector external lead-out terminal 18. Regarding the thickness of the emitter external lead-out terminal 19, the first structural example is configured to have substantially the same thickness as the collector internal connecting terminal 15 and the emitter internal connecting terminal 16, whereas the third structural example , Collector internal connection terminal 1
5 and the emitter internal connection terminal 16 are configured to be considerably thicker than the above, and there are no other structural differences between the third structural example and the first structural example.

According to the third structure example, as compared with the first structure example, the collector external lead-out terminals 18 in which the currents from the plurality of collector internal connection terminals 15 flow in a concentrated manner, and
The impedance of the emitter external lead-out terminal 19 in which the current from the plurality of emitter internal connection terminals 16 concentrates and decreases, and the current loss of the collector external lead-out terminal 18 and the emitter external lead-out terminal 19 can be further reduced.

According to the third structure example, the collector external lead-out terminal 18 and the emitter external lead-out terminal 19 can be mechanically tightened with high strength during mounting.
Collector external lead-out terminal 18 and emitter external lead-out terminal 19
Since the collector internal connection terminal 15 and the emitter internal connection terminal 16 are thinner than the thickness of the vertical extension portion 15
It is easy to deform in the directions of v and 16v, thermal stress or mechanical stress at the time of tightening can be absorbed, and a highly reliable power semiconductor device can be obtained.

FIG. 7 shows a specific structure of the terminal connecting portion,
And (a) is a structural view showing a connection state between the terminal connecting portion and the internal connecting terminal, wherein (a) is an example of the structure of the terminal connecting portion,
(B) shows another example of the structure of the terminal connecting portion.

In FIGS. 7A and 7B, 24 is the first
Of the terminal connection part (for example, collector terminal connection part), 25 is a second terminal connection part (for example, collector terminal connection part), 2
Reference numeral 6 denotes a bonding layer, and other components that are the same as the components shown in FIG. 2B are given the same reference numerals.

The first terminal connecting portion (for example, collector terminal connecting portion) 24 has an opening which opens downward in a substantially U shape and a tongue piece which is continuous with the opening. Is bonded to the insulating substrate 3 in a state of facing downward, and the lower part of the internal connection terminal (for example, collector internal connection terminal) 15 is bonded to the upper side of the opening. Also, the second
The terminal connection part (for example, collector terminal connection part) 25 of
It is a substantially U-shaped one having an opening on the lateral side, and one surface of this substantially U-shape is bonded onto the insulating substrate 3, and an internal connection terminal (for example, inside the collector is provided above the other surface of this substantially U-shape. The lower part of the connection terminal) 15 is joined.

When the first terminal connecting portion 24 or the second terminal connecting portion 25 having such a structure is used, the internal connecting terminal 1
The force in the direction of the vertically extending portion 15v applied to 5 can be almost absorbed by the elastic structure of the first terminal connecting portion 24 or the second terminal connecting portion 25 which is displaceable in the direction.
In addition, the first terminal connecting portion 24 or the second terminal connecting portion 2
When the internal connection terminals 15 connected to 5 are taller than the other internal connection terminals 15,
As shown on the left side of (a) and (b), if the first terminal connecting portion 24 or the second terminal connecting portion 25 is appropriately deformed, the height unevenness of the internal connecting terminals 15 can be absorbed. Therefore, it is possible to configure a highly reliable terminal connecting portion.

Next, FIG. 8 is a top view showing a second embodiment of the power semiconductor device according to the present invention, and FIG. 9 shows the power semiconductor device of the second embodiment shown in FIG. It is an electrical equivalent circuit.

In FIGS. 8 and 9, the same components as those shown in FIGS. 1 and 3 are designated by the same reference numerals.

Looking at the difference in configuration between the second embodiment and the first embodiment, each semiconductor unit unit 2
In the first embodiment, the semiconductor unit units 2 in the row direction are arranged in the same direction, and the semiconductor unit units 2 in the column direction are arranged in the opposite direction with respect to each other. On the other hand, in the second embodiment,
The semiconductor unit units 2 in the column direction are arranged to face the same direction, and the semiconductor unit units 2 in the row direction are arranged so that every other semiconductor unit unit 2 faces the opposite direction, and the collector terminal connecting portion 11 Regarding the arrangement of the emitter terminal connecting portion 12, the first embodiment is arranged so as to face the substantially central portion of each semiconductor unit unit 2, whereas the second embodiment is arranged so as to correspond to each semiconductor unit unit 2. Of the semiconductor unit unit 2 and the emitter terminal connection unit 12 of the semiconductor unit unit 2 adjacent to the collector terminal connection unit 11 (or the emitter terminal connection unit 12) of one semiconductor unit unit 2
(Or collector terminal connecting portion 11) is arranged so as to face each other, and there is no other structural difference between the second embodiment and the first embodiment. Therefore, further description of the configuration of the second embodiment will be omitted.

According to the above construction, the second embodiment is similar to FIG.
When attention is paid to the semiconductor unit unit 2 arranged on the upper left side of the figure (herein, this semiconductor unit unit is referred to as a first semiconductor unit unit), the semiconductor unit unit 2 arranged on the right side thereof, that is, shown in FIG. The semiconductor unit unit 2 arranged on the upper right side of the semiconductor unit unit 2 (herein, this semiconductor unit unit is referred to as the second semiconductor unit unit) is arranged so as to face the opposite direction to the first semiconductor unit unit 2,
On the other hand, the semiconductor unit unit 2 arranged on the lower side of the first semiconductor unit unit 2, that is, the semiconductor unit unit 2 arranged on the lower left side in FIG. 8 (here, this semiconductor unit unit is the third semiconductor unit unit). Unit) is arranged so as to face the same direction as the first semiconductor unit unit 2. Further, the semiconductor unit unit 2 arranged on the right side of the third semiconductor unit unit, that is, the semiconductor unit unit 2 arranged on the lower right side in FIG. 8 (here, this semiconductor unit unit is referred to as the fourth semiconductor unit unit). Is arranged so as to face the opposite direction to the third semiconductor unit unit 2 and the same direction as the second semiconductor unit unit 2. In this case, the collector terminal connection portion 11 of the first semiconductor unit unit 2 and the emitter terminal connection portion 12 of the second semiconductor unit unit 2 are arranged relatively close to each other, and
The emitter terminal connecting portion 12 of the semiconductor unit unit 2 and the collector terminal connecting portion 11 of the third semiconductor unit unit 2 are arranged close to each other. Second semiconductor unit unit 2
The collector terminal connecting portion 11 and the emitter terminal connecting portion 12 of the fourth semiconductor unit unit 2 are arranged close to each other,
Collector terminal connecting portion 11 of the third semiconductor unit unit 2
And the emitter terminal connection portion 1 of the fourth semiconductor unit unit 2
2 are arranged relatively close to each other, and the emitter terminal connection 12 of the third semiconductor unit unit 2 and the collector terminal connection 11 of the fourth semiconductor unit 2 are arranged close to each other.

The power semiconductor device having the above structure has an equivalent circuit as shown in FIG. 9 as a whole.
The two IGBT chips 4 and the two diode chips 5 provided in the first to fourth semiconductor unit units 2 are connected in parallel between the collector external lead-out terminal 18 and the emitter external lead-out terminal 19. Become. In this case, even if the collector terminal connecting portion 11 and the emitter terminal connecting portion 12 of the adjacent semiconductor unit units 2 are brought close to each other,
If the structure of the collector internal connection terminal 15 and the emitter internal connection terminal 16 as shown in FIG. 2B, FIG. 5 and FIG. 6 is adopted, the collector internal connection terminal 15 of the collector internal connection terminal 15 is similar to the first embodiment. It is possible to reduce the presenting inductance L1 and the presenting inductance L2 of the emitter internal connection terminal 16, etc., and to switch a large current at a high speed. In the second embodiment, the IG of each one of the first to fourth semiconductor unit units 2 is
The BT chip 4 and the diode chip 5 are the other IGB
Compared to the T chip 4 and the diode chip 5, the collector terminal connecting portion 11 and the emitter terminal connecting portion 12 are arranged at positions farther from each other. However, the current flowing through each of the IGBT chip 4 and the diode chip 5 is , IGB of each other
The non-uniformity of the current flowing through the T chip 4 and the diode chip 5 is very small and usually stays within the allowable range, so that the non-uniformity of the current is hardly affected.

Further, according to the second embodiment, all the effects expected in the first embodiment can be expected.

In the above-mentioned embodiment, as the semiconductor chip used for one semiconductor unit unit 2,
Although the IGBT chip 4, the diode chip 5, and the resistance chip 6 are used in the example described above, the semiconductor chip according to the present invention is not limited to the type and the number described above, and other types may be used. Instead of these semiconductor chips, for example, one or two transistor chips, GTO thyristor chips or the like may be used, or one or two transistor chips, GTO thyristor chips or the like may be used in combination. Good.

Further, in the above-mentioned embodiment, the example in which the number of the semiconductor unit units 2 mounted on the mounting substrate 1 is four has been described, but the number of the semiconductor unit units 2 according to the present invention is described. Is not limited to four, but five
You may make it use the number of pieces or more.

[0055]

As described above, according to the first and second aspects of the present invention, two or less semiconductor chips 4 and 5 having the same function are bonded and arranged in each semiconductor unit unit 2. Therefore, the current flowing through each semiconductor unit unit 2 becomes relatively small, and the impedance between each semiconductor chip 4, 5 to the corresponding internal connection terminal 15, 16 and the internal connection terminal 15, 16
To the external lead-out terminals 18 and 19 can be made uniform, and in particular, a plurality of semiconductor chips 4, 5 connected in parallel in one semiconductor unit unit 2
Is provided, the static characteristics and the dynamic characteristics between the semiconductor chips 4 and 5 can be made uniform,
There is an effect that a power semiconductor device having a large current capacity can be obtained.

According to the first and second aspects of the present invention, since the mounting substrate 1 is equipped with two or more semiconductor unit units 2 having a relatively small current capacity, the semiconductor unit unit 2 is mounted on the mounting substrate. When the semiconductor unit units 2 are mounted on the semiconductor unit 1, the semiconductor unit units 2 generate less heat and are dispersedly generated, so that the warpage of the mounting substrate 1 can be reduced, and the semiconductor unit units occupy a relatively small area. Since it is the unit 2, there is also an effect that voids are less likely to occur in the brazing filler metal such as solder that is generated when the semiconductor unit unit 2 is joined to the mounting substrate 1.

Further, according to the invention as set forth in claims 1 and 2, since two or more semiconductor unit units 2 are mounted on the mounting substrate 1, the internal connecting to one external lead-out terminal 18, 19 is achieved. The number of connection terminals 15 and 16 is increased, and thermal stress at the time of actual driving and mechanical stress at the time of tightening the external connection terminal are dispersed, respectively, and the terminal connection portions 11 and 12 of the semiconductor unit unit 2 and the internal connection terminal No large thermal stress or mechanical stress is applied between the terminals 15 and 16, and the terminal connecting portions 11 and 12 and the internal connecting terminals 15 and 16 are not applied.
There is also an effect that the connection state between and is less likely to deteriorate.

According to the invention described in claims 3 to 7, in addition to the effects obtained in the invention described in claims 1 to 2, terminal connection connected to the first main electrode side of each semiconductor unit unit 2 Since any one of the portion 11 and the terminal connecting portion 12 connected to the second main electrode side of each semiconductor unit unit 2 is arranged in proximity, the terminal connecting portions 11, 12 arranged in proximity to each other. From the external lead-out terminal 1 to be the first main electrode
8 and the external lead-out terminal 19 serving as the second main electrode, a mutual inductance is formed between the internal connection terminals 15 and 16, and this mutual inductance is the inductance L1 of these internal connection terminals 15 and 16. Since L2 is substantially reduced, there is an effect that an operation in a high frequency region becomes possible and a large current can be switched at a high frequency.

In addition, according to the invention described in claims 3 to 7, each terminal connecting portion 13 connected to the external lead-out terminal which becomes the control electrode of each semiconductor unit unit 2, and the first and second main electrodes. Since the terminal connection portions 11 and 12 connected to the external lead-out terminals 18 and 19 are arranged separately from each other, noise mixing into the control electrode side is reduced when switching a large current at a high speed, There is also an effect that the occurrence of the voltage rising phenomenon can be suppressed.

[Brief description of drawings]

FIG. 1 is a top view showing the configuration of a first embodiment of a power semiconductor device according to the present invention.

FIG. 2 is a sectional view showing a sectional structure of a first embodiment of a power semiconductor device according to the present invention.

FIG. 3 is an electrical equivalent circuit shown by the power semiconductor device of the first embodiment shown in FIGS. 1 and 2.

FIG. 4 is an explanatory diagram showing the relationship between the distance between the collector internal connection terminal and the emitter internal connection terminal and the width of the collector internal connection terminal and the emitter internal connection terminal.

FIG. 5 is a cross-sectional view showing a second example of the arrangement structure of collector internal connection terminals and emitter internal connection terminals.

FIG. 6 is a cross-sectional view showing a third example of the arrangement structure of collector internal connection terminals and emitter internal connection terminals.

FIG. 7 is a structural diagram showing a specific structure of a terminal connecting portion and a connection state between the terminal connecting portion and an internal connecting terminal.

FIG. 8 is a top view showing the configuration of a second embodiment of the power semiconductor device according to the present invention.

9 is an electrically equivalent circuit shown by the power semiconductor device of the second embodiment shown in FIG.

[Explanation of symbols]

1 common mounting substrate 2 semiconductor unit unit 3 insulating substrate 4 IGBT chip (semiconductor chip) 5 diode chip (semiconductor chip) 6 resistance chip (semiconductor chip) 7 collector electrode pattern / cathode electrode pattern (collector electrode pattern) 8 emitter electrode pattern Combined anode electrode pattern (emitter electrode pattern) 9 gate electrode pattern 10 metal wire 11 collector terminal connecting portion 12 emitter terminal connecting portion 13 gate terminal connecting portion 14 bonding layer 15 collector internal connecting terminal 15c connecting portion 15h vertical extending portion 15v horizontal extending portion 16 emitter internal connection terminal 16c connection part 16h vertical extension part 16v horizontal extension part 17 gate internal connection terminal 18 collector external lead-out terminal 19 emitter external lead-out terminal 20 hermetically sealed container 21 terminal board 22 hard resin 3 coating material 24 first terminal connecting portion 25 and the second terminal connecting portion

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Shigeki Sekine, Inventor Shigaki Sekine, 1-1, Omika-cho, Hitachi-shi, Ibaraki Hitachi Research Laboratory, Hitachi Ltd. (72) Inventor Shinya Koike, 3-chome, Saiwaicho, Hitachi, Tokyo No. 1 Hitachi Ltd., Hitachi Plant (72) Inventor Hideya Kokubun 10-2 Bentencho, Hitachi City, Tokyo Inside Hitachi Haramachi Electronic Industry Co., Ltd.

Claims (9)

[Claims] 1. A mounting substrate, a semiconductor unit unit mounted on the mounting substrate, a hermetic container that covers the mounting substrate on which the semiconductor unit unit is mounted, and a plurality of external lead terminals provided in the hermetic container. In the power semiconductor device having, the semiconductor unit unit includes an insulating substrate,
One or more semiconductor chips bonded and arranged on the insulating substrate, a plurality of electrode patterns bonded and arranged on the insulating substrate and provided corresponding to the semiconductor chips, the semiconductor chips, and the plurality of semiconductor chips. A plurality of metal wires bridgingly connected between the electrode patterns and a plurality of terminal connecting portions which are jointly arranged on the insulating substrate and are conductively connected to any of the plurality of electrode patterns, and these terminal connecting portions. The semiconductor chip is composed of internal connection terminals that are conductively connected to the corresponding external lead-out terminals, and the number of the semiconductor unit units mounted on the mounting substrate is two or more, and the semiconductor chips bonded to each semiconductor unit unit are arranged. A power semiconductor device having two or less devices having the same function. 2. A semiconductor chip provided in one semiconductor unit unit comprises two or less IGBT chips and I
2. The power semiconductor device according to claim 1, comprising two or less diode chips antiparallelly connected to the GBT chip. 3. A mounting substrate, a semiconductor unit unit mounted on the mounting substrate, a hermetic container covering the mounting substrate mounting the semiconductor unit unit, and a plurality of external lead-out terminals provided in the hermetic container. In the power semiconductor device having, the semiconductor unit unit includes an insulating substrate,
One or more semiconductor chips bonded and arranged on the insulating substrate, a plurality of electrode patterns bonded and arranged on the insulating substrate and provided corresponding to the semiconductor chips, the semiconductor chips, and the plurality of semiconductor chips. A plurality of metal wires bridgingly connected between the electrode patterns, a plurality of terminal connecting portions that are arranged jointly on the insulating substrate and are conductively connected to any of the plurality of electrode patterns, and these terminal connecting portions. The semiconductor unit unit mounted on the mounting board is composed of internal connection terminals that are conductively connected to the corresponding external lead-out terminals.
More than one, and the first of each semiconductor unit
A terminal connecting portion that is connected to an external lead terminal that serves as a main electrode,
Any one of the terminal connecting portions connected to the external lead-out terminals that will be the second main electrodes of the semiconductor unit units is arranged in close proximity and connected to the external lead-out terminals that will be the control electrodes of the semiconductor unit units. The semiconductor device for electric power is characterized in that it is spaced apart from the respective terminal connecting portions. 4. In each of the semiconductor unit units, a terminal connecting portion connected to an external lead terminal serving as a first main electrode and a terminal connecting portion connected to an external lead terminal serving as a second main electrode are arranged in proximity to each other. The power semiconductor device according to claim 3, wherein the power semiconductor device is a power semiconductor device. 5. Between one semiconductor unit unit and a semiconductor unit unit adjacent thereto, a terminal connecting portion connected to an external lead-out terminal which is a first main electrode of the one semiconductor unit unit and the adjacent semiconductor unit unit. 5. The power semiconductor device according to claim 3, wherein the terminal connection portion connected to the external lead-out terminal that serves as the second main electrode is disposed close to the terminal connection portion. 6. An arrangement interval between a terminal connecting portion connected to an external lead terminal serving as the first main electrode and a terminal connecting portion connected to an external lead terminal serving as the second main electrode is the internal connection terminal. 6. The power semiconductor device according to claim 3, wherein the power semiconductor device has a width smaller than twice the conductor width constituting the. 7. A semiconductor chip provided in one semiconductor unit unit comprises two or less IGBT chips and I
7. The power semiconductor device according to claim 3, wherein the power semiconductor device comprises two or less freewheel diode chips connected in antiparallel to the GBT chip. 8. The thickness of a conductor forming the external lead-out terminal is set to be thicker than the thickness of a conductor forming the internal connection terminal. Power semiconductor device. 9. The metal plate which is elastically displaceable in the vertical direction with respect to the insulating substrate is arranged between the terminal connecting portion and the internal connecting terminal. The power semiconductor device according to item 1.