JPH0877796A - Semiconductor memory device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a semiconductor memory device capable of shortening the test time. [Structure] A DRAM 1 is provided with a memory cell array 2 including a plurality of memory cells, and is selected by an address decoder 3 based on an address signal from the outside. When testing the memory cells of the memory cell array 2, the conversion circuit 4 uses the physical address for the normal mode for selecting and testing one memory cell from the outside for the test mode for selecting and testing a plurality of memory cells. Convert to physical address and output. The switching signal generation circuit 5 generates and outputs a switching signal CH based on a control signal input from the outside. The switching circuit 6 includes the physical address for the normal mode and the conversion circuit 4
The physical address for the test mode is input, and the physical address for the normal mode and the physical address for the test mode are switched based on the switching signal and output to the address decoder 3 as an address signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
Specifically, it relates to a characteristic test of a random access memory (RAM).

In recent years, as semiconductor memory devices have become more complicated and highly integrated, the characteristic test of semiconductor memory devices by a tester has become more complicated and longer. Since increasing the test time leads to an increase in the inspection cost, it is required to shorten the test time with a tester.

[0003]

2. Description of the Related Art Generally, in a RAM, in addition to an electrical characteristic test such as operation speed and power consumption before shipment, each operation of writing / reading / holding data to / from a memory cell is normal. It is necessary to perform various functional tests to determine whether or not. In particular, in a dynamic random access memory (DRAM), it is necessary to perform an interference test in various complicated operation modes in order to check inter-cell interference and the like in addition to writing / reading / holding data to / from the memory cell.

For example, assume that data "1" and "0" are written in adjacent memory cells on a DRAM chip, respectively. At this time, if there is interference between the memory cells, the data of the memory cells that should have held “0” may change to “1”. vice versa,
In some cases, the data in the memory cell that should have held "1" may change to "0" and be read out. for that reason,
It is necessary to perform an inter-cell interference test for writing / reading based on a test pattern in which adjacent memory cells are combined with “0” and “1”.

In the inter-cell interference test of DRAM, adjacent memory cells are sequentially selected, and data writing and reading are performed with respect to the selected memory cells. The data written to the memory cell and the data read from the memory cell are compared to determine whether there is interference between cells. Then, the memory cell to be selected is performed based on the test pattern generated by the algorithmic pattern generator (ALPG) of the memory tester.

The test pattern includes an address for selecting a memory cell, write data to be held in the memory cell at the address, expected data to be read from the address, change of address, change of write / read operation, etc. And a clock control signal for controlling. Then, depending on the test pattern algorithm, the ALPG can also generate and output consecutive addresses so as to sequentially select adjacent memory cells.

By the way, in a DRAM memory cell, the address input to the address terminal of the DRAM is
It does not necessarily correspond to the physical arrangement of cells on the chip. In order to distinguish these, an address input to an address terminal is a logical address, and an address according to a physical arrangement on a chip is a physical address.

This is often due to layout reasons mainly due to chip size restrictions. A logical to physical address translation is required to properly test inter-cell interference. Therefore, an address scrambler (hereinafter, simply referred to as a scrambler) that is a conversion table from the logical address to the physical address is prepared.

The scrambler inputs a logical address generated by ALPG, converts the input logical address into a physical address, and outputs the physical address to the DRAM. The DRAM selects a memory cell based on the input physical address. As a result, depending on the test pattern algorithm, the adjacent memory cells are sequentially selected and the data is written, so that the inter-cell interference can be appropriately tested.

On the other hand, since the storage capacity of DRAM has increased dramatically in recent years, the test time of the DRAM is D
It is becoming longer and longer corresponding to the storage capacity of RAM. Therefore, in addition to the normal mode in which test data is written / read while selecting memory cells one by one,
A test mode is often adopted in which a plurality of memory cells are selected at a time and test data is written / read to / from the selected plurality of memory cells. That is, by selecting a plurality of memory cells at once and writing / reading data, the test time can be shortened as compared with the test time in the normal mode.

In this test mode, it is necessary to generate a test pattern (test mode pattern) different from the test pattern in the test in the normal mode because a plurality of memory cells can be selected at one time. Therefore, a scrambler for converting a logical address into a physical address is also prepared according to the test mode pattern. The scrambler for the test mode is replaced with the scrambler for the normal mode and set in the memory tester for use.

[0012]

By the way, when a RAM scrambler for a test mode is set and a RAM characteristic test is carried out, the characteristics of the RAM may be determined by the data read from the address designated by the test mode depending on the test item. It may not be possible to judge. That is, in a RAM of a type that is determined to be defective when the normal mode scrambler is used, it may be determined to be normal when the test mode scrambler is used.

Therefore, there is a demand for reading the data in the normal mode after writing the test data in the memory cell in the test mode. However, in order to exchange the address scrambler, the test pattern must be finished once, and it is not possible to exchange the scrambler for the normal mode and the scrambler for the test mode while holding the data in the DRAM. could not.
Therefore, during the test, the logical address for the test mode and the logical address for the test mode cannot be switched in real time. Therefore, for a DRAM of a type that cannot be tested in the test mode, all items must be tested in the normal mode, resulting in a long test time and high test cost.

The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor memory device capable of shortening the test time.

[0015]

FIG. 1 is a diagram for explaining the principle of the present invention. The DRAM 1 is provided with a memory cell array 2, an address decoder 3, a conversion circuit 4, a switching circuit 5, and a switching signal generation circuit 6. The memory cell array 2 is composed of a plurality of memory cells, and the memory cells receive an address signal from the outside and are selected by the address decoder 3 based on the address signal.

When testing a memory cell of the memory cell array 2, a physical address for a normal mode for selecting and testing one memory cell from the outside is input to the conversion circuit 4. Then, the conversion circuit 4 converts the physical address for the normal mode into a physical address for the test mode for selecting and testing a plurality of memory cells, and outputs the physical address.

The switching signal generating circuit 5 receives a control signal from the outside, generates a switching signal CH based on the control signal, and outputs it. The switching circuit 6 directly inputs the physical address for the normal mode and also inputs the physical address for the test mode converted by the conversion circuit 4. Then, the switching circuit 6 switches between the physical address for the normal mode and the physical address for the test mode based on the switching signal input from the switching signal generation circuit 6, and outputs the address signal to the address decoder 3 as an address signal. The address decoder 3 selects a memory cell based on the input address signal.

[0018]

Therefore, according to the present invention, the physical address for the normal mode and the physical address for the test mode can be switched. As a result, even in a DRAM of a type that cannot be read in the test mode, it is possible to write to a plurality of memory cells at once by the test mode, so that the write time can be shortened.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. FIG. 2 is a block circuit diagram illustrating a DRAM connected to the memory tester.

The memory tester 10 is provided with a scrambler 11 for the normal mode, and a logical address for the normal mode among the test patterns output from the algorithmic pattern generator (hereinafter referred to as ALPG) 12 is a physical address. It is converted to and output to the DRAM 20.

Further, the memory tester 10 is provided with a control signal generation circuit 13. Control signal generation circuit 13
Of the test patterns generated and output by the ALPG 12, the clock control signal is input, and the control signal required for the DRAM 20 connected based on the clock control signal is generated and output. In this embodiment, as shown in FIG. 3, the control signals include a column address strobe signal (hereinafter referred to as a column signal) bar CAS, a row address strobe signal (hereinafter referred to as a row signal) bar RAS, and a write enable signal bar. WE
Are generated by the signal generation circuit 13.

The memory tester 10 also includes a comparison circuit 1
4 are provided. The comparison circuit 14 compares the data read from the DRAM 20 with the expected data of the test pattern. Based on the comparison result of the comparison circuit 14, the memory tester 10 determines whether the tested DRAM 20 is normal or not.

The DRAM 20 includes a conversion circuit 21, a switching circuit 22, a switching signal generation circuit 23, and an address decoder 2.
4, a memory cell array 25, and an input / output circuit 26 are provided. The conversion circuit 21 inputs the physical address from the memory tester 10 via the scrambler 11 for the normal mode. Then, the conversion circuit 21 converts the input physical address for the normal mode into a physical address for the test mode and outputs it to the switching circuit 22.

As shown in FIG. 3, the switching circuit 22 is a multiplexer and has an input A and an input B. The inputs A and B each have a plurality of bit configurations. The input A is directly connected to the memory tester 10 and inputs the physical address for the normal mode. The input B is connected to the conversion circuit 21 and inputs the physical address for the test mode converted by the conversion circuit 21. And
The switching circuit 22 inputs the switching signal CH and switches between the input A and the input B based on the switching signal. That is, the switching circuit 22 selects the physical address for the normal mode or the physical address for the test mode based on the switching signal CH, and outputs the selected physical address to the address decoder 24. The switching signal CH is input from the switching signal generation circuit 23.

As shown in FIG. 3, the switching signal generating circuit 23 receives the column signal bar CAS, the row signal bar RAS, and the control signal from the memory tester 10 via the input terminal 31.
The write enable signal bar WE is input. The switching signal generation circuit 23 uses the signal bars CA.
A switching signal CH is generated and output based on S, RAS and WE. The timing for generating the switching signal CH is a timing that is not realized when the user of the DRAM 20 normally uses it, and is generated at the timing shown in FIG.

That is, when the test mode is set, the control signal generation circuit 13 of the memory tester 10 generates and outputs the signals bar CAS, bar RAS, and bar WE at the timings shown in FIG. 4A. Then, the switching signal generation circuit 2
When detecting that the column signal bar CAS and the write enable signal bar WE are at L level, 3 generates and latches the H level switching signal CH.

On the other hand, the control signal generating circuit 13 of the memory tester 10 releases each signal bar CA at the timing shown in FIG. 4B when the test mode is released (set to the normal mode).
S, bar RAS, bar WE are generated and output. When the switching signal generation circuit 23 detects that the column signal bar CAS is at the L level and the write enable signal bar WE is at the H level when the row signal bar RAS falls, it generates the L level switching signal CH, To latch. The switching signal generation circuit 23 then latches the switching signal C
The H is output to the switching circuit 22 and the address decoder 24.

As shown in FIGS. 4 (a) and 4 (b), the control signal generation circuit 13 of the memory tester 10 is operated by each signal bar CA.
The timing for generating S, bar RAS, and bar WE is J
EDEC (Joint Electron Devices Engineering Counci
l) The timing is defined by the standard. That is, FIG.
As shown in (a), the WCBR method (column signal bar C
The test mode is set by the combination of the timing of AS, the row signal bar RAS, and the write enable signal bar WE. Further, as shown in FIG. 4B, the test mode is released by the CBR method defined by the same standard.

A memory cell array 25 is connected to the address decoder 24. The memory cell array 25 is
Divided into four blocks BL1 to BL4, each of which has 2
It is composed of memory cells arranged in a dimension. The address decoder 24 is a row address decoder and selects a memory cell based on the addresses RA0 to RA11 input via the switching circuit 22. The address decoder 24 is connected to the switching signal generating circuit 23 and inputs the switching signal CH.

When the address decoder 24 receives the L level switching signal CH from the switching signal generating circuit 23, it selects one memory cell based on the addresses RA0 to RA11 input via the switching circuit 22. There is. Then, the selected memory cell becomes a target of data writing / reading.

When the switching signal CH of the H level is input from the switching signal generation circuit 23, the address decoder 24 receives each block BL1 to BL4 of the memory cell array 25.
Select Then, the address decoder 24 receives the address RA0 input via the conversion circuit 21 and the switching circuit 22.
~ RA9 based on memory cells in each block BL1 ~ B
Each is selected from L4. Therefore,
When the switching signal CH is at H level, the address decoder 24
Selects four memory cells simultaneously. Then, the selected four memory cells are the targets of data writing / reading.

The input / output circuit 26 is a memory cell array 25.
It is connected to the. Further, the input / output circuit 26 receives the write enable signal bar WE. Then, the input / output circuit 26 writes the data input from the outside of the DRAM 20 to the memory cell selected by the address decoder 24 in the write operation based on the write enable signal bar WE. Further, in the case of a read operation based on the write enable signal bar WE, the input / output circuit 26 reads the data held in the memory cell selected by the address decoder 24 and outputs it to the outside. And the switching signal CH
Is at the H level, the address decoder 24 simultaneously selects four memory cells. Therefore, the input / output circuit 26
Writes / reads data to / from four memory cells.

The input / output circuit 26 is connected to the memory tester 10 when testing the DRAM 20, and inputs the write data of the test pattern. Further, the input / output circuit 26 is
The write enable signal bar WE output from the control signal generation circuit 13 of the memory tester 10 is input. Then, the input / output circuit 26 writes the write data input from the memory tester 10 to the memory cell selected by the address decoder 24 when the write enable signal bar WE of L level is input. Further, when the input / output circuit 26 receives the H-level write enable signal bar WE, the input / output circuit 26 reads data from the memory cell selected by the address decoder 24 and outputs the data to the memory tester 10.

Although only the circuit for the row addresses RA0 to RA11 input to the DRAM 20 is shown in FIG. 3, the circuit for the column address is also similarly performed. That is, a multiplexer is provided between the address terminal 32 and the conversion circuit 21, and the multiplexer has a column signal bar CAS and a row signal bar RA.
Addresses A0 to A11 input based on S are used as column addresses CA0 to CA11 and are output to the column decoder through a conversion circuit for converting the column address into a physical address for the test mode and a switching circuit. Also, it outputs directly to the column decoder through the switching circuit. The column decoder selects a column of memory cells based on the input column address. Then, the memory cells at the intersections with the rows of the memory cells selected by the row decoder are targeted for writing / reading.

When the DRAM 20 configured as described above is normally used, the switching signal generation circuit 23 outputs the L level switching signal CH based on the row signal bar RAS, the column signal bar CAS, and the write enable signal bar WE. Generate and output. The switching circuit 22 uses the L level switching signal CH.
When inputting, the input A is selected. As a result, the address input to the address terminal 32 is input to the address decoder 24 from the address terminal 32 via the switching circuit 22 as row addresses RA0 to RA11. The address decoder 24 receives the input row addresses RA0 to RA11.
Select a column of memory cells based on. Then, based on the input column address, a column decoder (not shown) selects a row of memory cells. Then, the data is read out from the memory cell at the intersection of the selected column and row.
Writing is done.

On the other hand, the DRAM 2 configured as described above
When a functional test, for example, an interference test between memory cells is performed on 0, the control signal generation circuit 13 of the memory tester 10
Generates and outputs a control signal based on the test pattern generated by the ALPG 12. At this time, the control signal generation circuit 13 generates and outputs a control signal to set the test mode.

The ALPG 12 also outputs to the scrambler 11 logical addresses X0 to X9 according to the test mode. The scrambler 11 receives the input logical address X0
To X9 are converted to physical addresses for the normal mode, and are output to the DRAM 20 as addresses A0 to A9.

The switching signal generation circuit 23 of the DRAM 20 is
Column signal bar CAS and row signal bar R as control signals
AS and the write enable signal bar WE are input to generate a switching signal CH of H level and output to the switching circuit 22 and the address decoder 24.

The switching circuit 22 outputs the switching signal CH of H level.
Is input, input B is selected. Address decoder 2
When the switching signal CH at the H level is input, 4 selects all the blocks BL1 to BL4 of the memory cell array 25.

Further, the DRAM 20 is the memory tester 10
If you input address A0-A9 from
0 to A9 are input to the conversion circuit 21. Conversion circuit 21
Converts the input addresses A0 to A9, which are physical addresses for the normal mode, into physical addresses for the test mode. Then, the conversion circuit 21 sets the converted physical address as the row address RA0 to RA9 and the switching circuit 22.
Output to. At this time, since the input B is selected in the switching circuit 22 based on the switching signal CH at the H level, the row addresses RA0 to RA0, which are physical addresses for the test mode, are selected.
RA9 is output to the address decoder 24.

The address decoder 24 inputs the row addresses RA0 to RA9, which are physical addresses for the test mode, via the switching circuit 22, and among them, the row address R
One column of memory cells is selected for each block BL1 to BL4 of the memory cell array 25 based on A0 to RA9. Then, a column decoder (not shown) selects a row of memory cells, and a memory cell at the intersection of the selected column and row is selected. Therefore, in the memory cell array 25, four memory cells are simultaneously selected.

The input / output circuit 26 simultaneously writes the test data “0” input from the memory tester 10 to the selected four memory cells. as a result,
The time required for writing is shorter than that in the normal mode in which one memory cell is selected and test data is written.

Next, the memory tester 10 generates and outputs control signals for the column signal bar CAS, the row signal bar RAS, and the write enable signal bar WE at the timing of the CBR method for switching to the normal mode. Switching circuit 2
The column signal bar CAS, the row signal bar RAS, and the write enable signal bar WE are input to the signal line 2,
The L level switching signal CH is generated and output based on the timing of S, RAS and WE.

The switching circuit 22 outputs an L level switching signal CH.
When inputting, the input A is selected. As a result, the addresses A0 to A11, which are the physical addresses for the normal mode input from the address terminal 32, become the row addresses RA0 to RA.
11 is output to the address decoder 24.

The address decoder 24 selects the row address RA1 among the input row addresses RA0 to RA11.
One of the blocks BL1 to BL4 of the memory cell array 25 is selected based on 0 and RA11. Further, the address decoder 24 selects one column of memory cells from the block selected based on the row addresses RA0 to RA9. Then, a column decoder (not shown) selects a row of memory cells, and a memory cell at the intersection of the selected column and row is selected. The input / output circuit 26 writes the test data “1” input from the memory tester 10 to the selected memory cell.

Next, the memory tester 10 includes the DRAM 20.
The data is read from the memory cell in which the test data has been written, among the memory cells. Then, the comparison circuit 14 compares the read data with the expected data “1”. At this time, if there is interference (influence) from the memory cell adjacent to the memory cell in which the test data has been written in the memory cell array 25, the read data becomes “0”. The comparison circuit 14 compares the read data “0” with the expected data “1”. Since both data are different between "0" and "1", the memory tester 10 determines that the DRAM 20 that has performed this test is defective.

On the other hand, when there is no interference between the memory cells and the read data is "1", the read data "1" matches the expected data "1". Therefore, the memory tester 10 determines that it is normal and tests the next address. When the test data is written / read to / from all the memory cells, the DRAM 2
0 is judged to be normal in the inter-cell interference test, and the inter-cell interference test is ended.

Thus, in this embodiment, the DRAM 20
Is provided with a scrambler 11 and a switching circuit. Then, using the test pattern for the normal mode, the DRAM 20
When performing the test of 1, the switching circuit 22 is designed to directly input the test pattern input from the tester through the scrambler 11 for normal mode to the address decoder 24. On the other hand, depending on the test pattern for the test mode, DR
When the AM 20 is tested, the switching circuit 22 converts the test pattern input from the tester via the normal mode scrambler 11 into a physical address via the scrambler 11, and uses the physical address to decode the address decoder 24.
The memory cell is selected by. Therefore, DR
The physical address for the normal mode and the physical address for the test mode can be switched in real time without losing the data of the AM 20.

As a result, it is possible to write to a plurality of memory cells at a time in the test mode even in a DRAM of a type that cannot be read in the test mode, so that the write time can be shortened. Therefore, the test time can be shortened as compared with the conventional method.

Further, when reading data from the memory cells, since the memory cells are selected and read one by one in the normal mode, the data can be surely read as in the conventional case, and whether the DRAM 20 is normal or abnormal. You can avoid making a mistake in the decision.

The present invention may be carried out in the following modes other than the above embodiment. 1) In the above embodiment, as shown in FIG. 6, the memory tester 10 is provided with a test mode scrambler 41,
The DRAM 20 includes a conversion circuit 42 for converting the physical address for the test mode into the physical address for the normal mode.
May be provided and implemented. And DRAM
Switching signal CH is generated to select input B when 20 is normally used, input A when performing a memory test in the normal mode, and input B when performing a memory test in the test mode. To do so.

2) In the above embodiment, when the test mode is released, the L level switching signal CH is generated at the timing according to the CBR method, but the test mode is released at other timing (set to the normal mode). You may do it. For example, as shown in FIG. 5A, the WCBR method (column signal bar CAS,
The test mode is set by the combination of the timings of the row signal bar RAS and the write enable signal bar WE.
Then, as shown in FIG. 5B, the L level switching signal CH is generated at the timing of the ROR method to cancel the test mode.

3) In the above embodiment, the number of blocks dividing the memory cell array 25 of the DRAM 20 is appropriately changed. The larger the number of divided blocks, the shorter the test data writing time can be.

4) In addition to DRAM, SRA in which a logical address and a physical address are different and an address scrambler is required
It is embodied in a memory such as M (Static Random Access Memory).

[0055]

As described in detail above, according to the present invention,
A semiconductor memory device capable of shortening the test time can be provided.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block circuit diagram illustrating a DRAM connected to a tester.

FIG. 3 is an explanatory diagram illustrating a scrambler and a conversion circuit.

FIG. 4 is a waveform diagram showing a timing of generating a switching signal.

FIG. 5 is a waveform diagram showing the timing of generating another switching signal.

FIG. 6 is an explanatory diagram illustrating another scrambler and conversion circuit.

[Explanation of symbols]

 1 DRAM as semiconductor memory device 2 Memory cell array 3 Address decoder 4 Conversion circuit 5 Switching signal generation circuit 6 Multiplexer as switching circuit

Claims (4)

[Claims] 1. A semiconductor memory device comprising: a memory cell array including a plurality of memory cells; and an address decoder for inputting an address signal from the outside and selecting a memory cell of the memory cell array based on the address signal. A conversion circuit that converts the address signal input from the memory cell into physical addresses that sequentially specify the memory cells arranged in the memory cell and outputs the control signal, and switches based on the input control signal. A switching signal generation circuit that generates and outputs a signal, and a physical address converted by the conversion circuit are input, an address signal from the outside is directly input, and a switching signal output from the switching signal generation circuit is input. , The address is switched by switching between a physical address and an external address signal based on the switching signal. The semiconductor memory device including a switching circuit for outputting to the coder. 2. The semiconductor memory device according to claim 1, wherein the memory cell is composed of a plurality of blocks, and the address decoder is based on the switching signal, of the physical addresses input in the normal mode. A semiconductor memory device in which one of the plurality of blocks is selected based on a plurality of bits, and the plurality of blocks are simultaneously selected in a test mode. 3. The semiconductor memory device according to claim 1, wherein the switching signal generating circuit generates a switching signal based on a column address strobe signal, a row address strobe signal, and a write enable signal. Semiconductor memory device. 4. The semiconductor memory device according to claim 1, wherein the conversion circuit inputs a physical address for a normal mode for selecting and testing the memory cells one by one, A semiconductor memory device in which the physical address is further converted into a physical address for a test mode for selecting and testing a plurality of memory cells and output.