JPH087742B2 - One-chip microcomputer - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a one-chip microcomputer (hereinafter, one-chip microcomputer), and more specifically, to a commercialized one-chip microcomputer, an option for input / output terminals later. The present invention relates to a changeable one-chip microcomputer.

[Prior Art] One-chip microcomputers are often used as control circuits in cameras, household electric appliances, and other electronic devices, and many 4-bit or 8-bit control devices are manufactured.

Unlike general-purpose microprocessors, this type of one-chip microcomputer is built in advance in the form of a RAM, ROM, etc., fixed-capacity bus-connected inside one chip, and the same transmission and reception of signals to and from the outside. The I / O buffer connected to the bus is used, and these circuits are controlled by the central processor (or the controller, including the CPU below), and data is exchanged with external circuits via the I / O buffer. Is designed to.

Also, in a one-chip microcomputer having a ROM, an application program corresponding to each application of the circuit can be written in the ROM later, and after being manufactured as an LSI, the application program is loaded according to each application and the application corresponding to the application is loaded. Used as a one-chip microcomputer. Further, in the latter, various optional functions such as CMOS output or open drain output with one terminal can be set to the input / output terminal for the option by the mask option.

[Problems to be Solved] A one-chip microcomputer in which an application program can be written to a ROM later can be used for development of the one-chip microcomputer and various purposes because the application program can be changed later. However, in this case, the option function added to the input / output terminal cannot be changed later because it is a mask option.

Therefore, the change of the optional function of the input / output terminal has hitherto been carried out by correcting the external circuit or by providing an external additional circuit. As a result, especially when using this type of one-chip microcomputer for system development,
This has the drawback of reducing the efficiency of system development.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the prior art, and an object of the present invention is to provide a one-chip microcomputer in which an optional function of an input / output terminal can be changed later.

[Means for Solving the Problems] The configuration of the one-chip microcomputer of the present invention for achieving the above object is such that the non-volatile memory is a rewritable memory by an electric signal input from a terminal, and a reset period Reset circuit for generating a first initial reset signal having a short first period and a second initial reset signal having a second period having a longer reset period, and a signal for accessing an address of the nonvolatile memory And an I / O buffer that has a storage circuit in which specific data is set and that operates according to the data stored in the storage circuit, and the first period is a nonvolatile memory. Is a period until the address counter and the memory circuit become operable.
Is a period during which the internal circuits including the CPU other than the non-volatile memory, the address counter, and the storage circuit can operate, and the data transferred to the storage circuit is written to the non-volatile memory as an electric signal through the terminal. When the address counter receives the first initial reset signal from the initial reset circuit and reset is released, the count value of the address counter is sequentially updated from the end of the first period to the end of the second period. The data stored in the nonvolatile memory that is accessed according to the count value of the lever counter is transferred to the storage circuit and stored therein, and the internal circuit including the CPU receives the second initial reset signal from the initial reset circuit. The internal circuit including the CPU is operated after the end of the second period when the reset is released.

[Operation] By the way, the one-chip microcomputer includes various circuits inside the built-in CPU and the like, and various circuits outside the CPU. In this relationship, the reset period until reaching the power supply voltage for guaranteeing all the operations is relatively long. On the other hand, the operable voltage of the memory is set to a value lower than that of the CPU and general hardware circuits.
The period from turning on to becoming operable is shorter than the reset period. This is because of the guarantee of stored data and the back-amplifier operation. Further, it is easy to make a register, an access circuit, and the like into a circuit having a low operating voltage like a memory by devising a transistor. Therefore, the nonvolatile memory, the access circuit, and the storage circuit are operated during a period shorter than the reset period to initialize the option I / O. In this way, option setting is completed during the normal reset period.

That is, the first and second initial reset signals having different periods are generated in the initial reset circuit, and writing is performed by an electric signal between the first reset signal and the second reset signal via the terminal. Non-volatile memory, for example, EEPROM by operating the access circuit of EEPROM
Since the data stored in the I / O is transferred to the I / O, the data stored in the I / O can be easily changed if the data in the EEPROM is externally written and changed in advance.

As a result, when an I / O has an option, the I / O can be freely set later according to the option.

[Embodiment] An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the one-chip microcomputer of the present invention, and FIG.
FIG. 3 is an explanatory diagram showing the relationship with the I / O buffer, and FIG. 3 is an explanatory diagram of the internal configuration of the I / O of the option input / output terminal.

In FIG. 1, reference numeral 10 denotes a one-chip microcomputer, which includes a CPU 1 including a timing generation circuit, an EEPROM 2 for storing an application program, and an EEPROM 3 and E for storing data for adding optional functions to input / output terminals.
Address counter 4a for accessing EPROM2 and EEPROM3, register 4b for temporarily storing write data for EEPROM2 and EEPROM3, I / O buffers (I / O) 5a, 5b,
..., 5n, I / O buffer (I / O) 6a, 6b, ... 6m, I / O buffer (I / O) connected to the input / output terminal for option setting
O) 7a, 7b, ... 7 and a mode setting terminal 8. Then, these respective circuits are connected to each other via a bus 9. In addition to the bus 9, the EEPROM 3 for adding the optional function includes the I / O buffers 7a, 7b, ... 7 connected to the option setting input / output terminals, the data line 4c and the address bus 4d (this address bus May be the address bus of bus 9).

Reference numeral 11 denotes a clock generation circuit, which supplies a clock to each circuit of the one-chip microcomputer 10 including the CPU 2 and a clock (shown as a signal 11a) to an address counter + decoder 4a (hereinafter described as the address counter 4a).
To supply. As a result, the address counter 4a starts operating after the one-chip microcomputer 10 is powered on and reset is released. Reference numeral 12 denotes an initial reset circuit, which has a counter inside the normal initial reset circuit and generates a reset signal having two different reset periods when the power is turned on. The first reset signal 12a is a signal for releasing the reset of the address counter 4a, and is at a LOW level (hereinafter "L") during the period in which the power supply voltage becomes a voltage at which the circuit can operate, and maintains the reset state. This is, for example, “L” while counting about 1024 clocks of the clock generation circuit 11 from the power “ON”, and then becomes HIGH level (hereinafter “H”). This signal can be configured by a reset circuit or a counter using ordinary C and R. The second reset signal 12b changes from "ON" to "L",
After the first reset signal 12a becomes "H", the clock is further counted, for example, 1024, and then "L" to "H".
This signal is used to release reset of internal circuits such as CPU2. This signal can be configured by, for example, a reset circuit using a counter. By generating these two reset signals by such an initial reset circuit 12, the address counter 4a is released from reset and operates before the other circuits in the one-chip microcomputer 10, and operates the addresses 0 to 1023. appear.
During this period, the power supply voltage is EEPROM or I / O.
O The power supply voltage at which the buffer operates is set. At this time, the address counter 4a is sequentially incremented by the clock 11a until the second reset signal 12b becomes "H" after the first reset signal 12a becomes "H", and corresponds to each address value. Read data from each address of EEPROM3 to I / O buffer 7a for option input / output,
Data is sequentially transferred to 7b, ... 7 through the data line 4c.

A mode detection circuit 13 is connected to the mode setting terminal 8 and detects the voltage applied to the mode setting terminal 8 to set the one-chip microcomputer 10 in various mode states. Here, as a mode that can be set, for example, 0 V to
When a voltage of 2V is applied to this pin, it is in the normal operation mode, and when a voltage of more than 2V and up to 3V is applied to this pin, it is in the bus monitor mode. Also, 3V
When the voltage exceeding 5V is applied to this pin, it becomes the test mode in which the CPU can be controlled by receiving the external data, and when the voltage exceeding 5V and up to 7V is applied to this pin, EEPROM2,3 Write data to, E
Enters EPROM write mode.

Then, the I / O buffers 5a, 5b, ..., 5n are I / O buffers for output for monitoring the timing in the test mode or the EEPROM write mode, and the I / O buffer 6a, 6b, ..., 6n are I / O buffers that serve as data input terminals when writing program data or various data to EEPROM2 or EEPROM3 in the test mode or EEPROM writing mode. Each I / O buffer including the I / O buffers 7a, 7b, ..., 7 includes a circuit for storing data such as a latch circuit.

The bus 9 is composed of a data bus, an address bus, and a control bus, and the CPU 1 has ROM and RAM built therein. Further, 20 is an input / output terminal to which each I / O buffer is connected.

FIG. 2 shows the mode detection circuit 13 and the I / O buffers 6a, 6b ,.
.., 6n is shown. Each of these I / O buffers has the same structure, and the I / O buffer 6 is shown as a representative of them. The I / O buffer 6 includes an input buffer circuit 61, an output buffer circuit 62, latch circuits 63 and 64,
It has a 2-input gate circuit 65 and the like, and one input of the input buffer circuit 61, the output buffer circuit 62, and the gate circuit 65 is connected to the input / output terminal 20, respectively.

Here, when the mode detection circuit 13 detects the EEPROM writing mode, it outputs a signal of "H" to its output terminal 13a. This output is input to the other input of the gate circuit 65, and also to the input buffer circuit 61 and the output buffer circuit 62.
Input buffer circuit supplied as a disable signal for
61, stop the operation of the output buffer circuit 62. At this time, the gate circuit 65 is opened to allow the signal of the input / output terminal 20 to pass therethrough and to let it pass through the register 4b for storing the write data of the EEPROM.
Supply to the digit position corresponding to the digit position of the I / O terminal 20 of.

In addition, an input voltage of 3V to 5V is applied to the input of the mode detection circuit 13 to control the CPU from the outside, and among the flags of the status register provided inside the control circuit 14.
Set the EEPROM write flag to "1". When this flag is set to "1", the value of the address counter 4a is externally set via the I / O buffers 6a, 6b, ...
The position data can be written to the address indicated by the address counter 4a of the EEPROM 2 or 3 via the I / O buffers 6a, 6b, ..., 6n.

Further, the control circuit 14 has a status register for selecting one of the EEPROM2 and the EEPROM3.

Therefore, when loading a program or data to the EEPROMs 2 and 3, a voltage of more than 5V to 7V is applied to the mode setting terminal 8 and then predetermined address data of the EEPROM 2 and EEPROM 3 is externally written. The data write timing is set in synchronization with the clock generation by monitoring the bus 9.

Here, it is assumed that EEPROM2 and EEPROM3 are located in completely different address spaces. Therefore EEPROM2 and EEP
To select the ROM3, for example, 3 to 5 V is applied to the mode detection circuit 13 to set the mode in which the CPU is controlled from the outside, and the EEPROM2,
Select which of EEPROM3 to select. The address of EEPROM2 is set from CPU1. The EEPROM 3 is assumed to store 1-bit data at 1 address here.

FIG. 3 shows the output of the address counter 4a on the address bus.
Option I / O buffers 7a, 7b, ... that receive data via 4d and receive data from EEPROM 3 via data line 4c
..7 is shown. Similar to FIG. 2, the I / O buffer 7 is shown as a representative of each I / O buffer. The I / O buffer 7 is an input buffer and includes a latch circuit 71 connected to the data line 4c, an address decoder 72 connected to the address bus 4d, an input circuit 73, a pull-up transistor 74, and the like. Has been done. In the case of an output buffer, the input circuit 73 serves as an output circuit.

In this case, by setting the data “1” or “0” in the latch circuit 71, when it is “1”, the transistor 74 turns “OFF” and the input circuit 73 becomes an input circuit without a pull-up resistor, so that “0” In the case of, the transistor 74 is turned "ON" and the circuit has a pull-up resistor. This is just an example. In addition, whether the output circuit is an open drain circuit, a normal inverter circuit, a pull-up circuit, or a pull-down circuit is I / O. It can be freely set by the circuit configuration of the buffer.

Next, the overall operation of the one-chip microcomputer 10 will be described.

First, the data write operation for the EEPROM 3 will be described. When a signal with a voltage of more than 5V and up to 7V is supplied to the mode setting terminal 8, the one-chip microcomputer 10 causes the EE
Enter PROM write mode.

At this time, first, data can be written in the EEPROMs 2 and 3 via the I / O buffers 6a, 6b, ..., 6n. The address space of EEPROM3 is from "0" to "1023", so each I / O
The data to be set in the latch circuit 71 of the buffers 7a, 7b, ... In this case, the data stored in each address of the EEPROM 3 is "1" as the data to be latched by the latch circuit 71 at the address position where the address value and the decode address of the address decoder 72 in each I / O buffer 7 match. "Or" 0 "is stored.

In this way, the input of the mode detection circuit is input to the one-chip microcomputer 10 whose data is stored in each EEPROM 2, 3.
The reset circuit 13 is operated when the normal operation mode is set at 0V to 2V and the power is turned on to bring the operation state. Then, first, at the timing when the clock is counted up to about "1023", the first reset signal 12a changes from "L" to "H", and the reset of the address counter 4a is released. At this time, the power supply voltage is in a stable state in which the circuit can operate.

At this timing, the address counter 4a increments from “0” in accordance with the clock 11a from the clock generation circuit 11, accesses the address of the EEPROM 3 at each incremented address, and reads the data read from the EEPROM 3 into each I / O. , O buffers 7a, 7b, ... In each I / O buffer 7, an I / O buffer having an address decoder 72 for decoding the corresponding address decodes the address signal (value of the address counter 4a) supplied from the address bus 4d and latches it.
Set the data from EEPROM3 to.

In this way, the generated clock is from "1024" to "2048".
When it comes to the timing up to (= 1024 + 1024), this time,
The second reset signal 12b changes from "L" to "H", the reset of the internal circuit of the one-chip microcomputer 10 is released, and normal operation starts. At this time, each I / O buffer 7a, 7b, ...
.., 7 data is set to "1" or "0" according to the data stored in the EEPROM3, and the input / output terminal connected to it is selected for the function according to the option. There is.

Now, when it is desired to change the contents of each I / O buffer 7a, 7b, ..., 7, the above-mentioned predetermined voltage signal is applied to the mode setting terminal 8 and the EEPROM write mode is set.
It can be understood that other states can be easily set by changing the data in 3.

By doing so, at the same time as changing the application program, it is possible to freely set options for I / O later, and the corresponding input / output terminals can be made to function according to the options.

As described above, in the embodiment, the plurality of I / Os connected to the input / output terminals for option setting are provided, but the number may be one. Further, although the EEPROM for storing the application program is provided as the EEPROM, such an EEPROM may not be provided. Further, the present invention is not limited to the EEPROM, and any memory may be used as long as the memory is provided in the one-chip microcomputer as a nonvolatile memory that can be rewritten from the outside.

Further, in the embodiment, the EEPROM 3 for adding an option to the input / output terminal is a memory for storing 1 bit, but this may be for storing several bits.
For example, 8 bits may be stored in one address and transferred in parallel to each of the 8 I / O buffers.

In the embodiment, the EEPROM 3 is arranged in "0" to "1023" in the address space indicated by the address counter 4a.
Since the address space can be easily converted by a circuit such as a decoder, it goes without saying that the EEPROM 3 may be arranged in any space. Furthermore, the number of allocations of this address space may correspond to the number of data transferred to the I / O buffer or more. Therefore, the period between the first initial reset signal and the second initial reset signal may be determined accordingly.

[Effects of the Invention] As can be understood from the above description, in the present invention, the first reset signal 12a and the first reset signal 12a are generated by causing the initial reset circuit to generate the first and second initial reset signals having different periods. A non-volatile memory which can be written by an electric signal through a terminal between the reset signal 12b and the second reset signal 12b, for example, an access circuit of the EEPROM is operated to transfer the data stored in the EEPROM to the I / O. So EEPRO
If the M data is externally written and changed beforehand, the data stored in the I / O can be easily changed.

As a result, when I / O has an option, it can be freely set later according to the option.

This makes it possible to freely and efficiently change the contents of the I / O pin when developing a one-chip microcomputer or changing the input / output pin function according to the application later. The one-chip microcomputer can be used without modification, development, or external installation. Therefore, the development period of the application of the one-chip microcomputer can be shortened, and the degree of freedom in changing the application can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a one-chip microcomputer of the present invention, FIG. 2 is an explanatory diagram showing the relationship between an option EEPROM and an I / O buffer, and FIG. 3 is an option input / output terminal. 3 is an explanatory diagram of an internal configuration of the I / O buffer of FIG. 1 ... CPU, 2 ... EEP for storing application program
ROM, 3 ... EEPROM for adding optional functions, 4a ... address counter, 4b ... register for storing write data, 4c ... data line, 4d ... address bus, 5a, 5b, 5n, 6a, 6b, 6m, 7a, 7b, 7 …… I / O buffer, 8 ……
Mode setting terminal, 9 ... Bus, 10 ... One-chip microcomputer, 14 ... Control circuit (circuit that controls EEPROM).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-60-103424 (JP, A) JP-A-1-149158 (JP, A) JP-A-1-154212 (JP, A)

Claims (1)

[Claims] 1. An externally rewritable non-volatile memory and a CPU
In the one-chip microcomputer incorporating the above, the non-volatile memory is a memory that is rewritable by an electric signal input from a terminal, and a first initial reset signal having a first period with a short reset period and An initial reset circuit for generating a second initial reset signal having a second period having a long reset period, an address counter for transmitting a signal for accessing an address of the nonvolatile memory, and a memory in which specific data is set. An I / O buffer having a circuit and operating in accordance with data stored in the memory circuit, wherein the nonvolatile memory, the address counter, and the memory circuit are operable during the first period. Up to the non-volatile memory, the address counter, and the memory during the second period. In a period during which an internal circuit including the CPU other than the path becomes operable, data to be transferred to the storage circuit is written as an electric signal in the nonvolatile memory via the terminal, and the address counter is The count value of the address counter is sequentially updated from the end of the first period when the reset is released by receiving the first initial reset signal from the initial reset circuit to the end of the second period, and this address is updated. Data stored in the non-volatile memory, which is accessed according to the count value of the counter, is transferred to the storage circuit and stored therein, and an internal circuit including the CPU outputs the second initial reset signal from the initial reset circuit. In response to this, the internal circuit including the CPU is operated after the end of the second period when the reset is released. One-chip microcomputer.