JPH0875516A - Phase locked loop and ultrasonic flowmeter - Google Patents

Abstract

PURPOSE: To obtain an inexpensive phase locked loop and an ultrasonic flowmeter having simple circuitry where a special phase comparator is not employed. CONSTITUTION: A phase comparator 101 comprises a sequential circuit 5 for phase comparison having two input terminals receiving an input signal R and a feedback signal V and two output terminals 6, 7 delivering outputs for advancing or delaying the phase of a feedback signal through a loop filter and a voltage controlled oscillator, a charge pump circuit 8 receiving outputs U, D from two output terminals to synthesize a single phase comparator output, detectors 15, 15' connected, respectively, with two output terminals in order to detect convergence or divergence of the output by measuring the duration of '1' and '0' states of output signal, and an operating circuit 16 for subjecting the input signal R or the feedback signal V to a predetermined alteration in logical value based on an output from the detection circuit thus altering the polarity of the output signal from the sequential circuit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a phase locked loop (abbreviated as PLL), and a PL suitable for a PLL type ultrasonic flowmeter.
The present invention relates to a phase comparator for L.

[0002]

2. Description of the Related Art FIG. 7 shows the structure of a general PLL, and FIG.
Shows a circuit diagram of a phase comparator used in a conventional PLL, and its outline will be described below. In FIG. 7, reference numeral 1
Is a phase comparator which receives the input signal R and the feedback signal V of the loop, and gives a frequency difference when the frequencies of the two signals are different, and an output signal corresponding to the phase difference of the two signals when the frequencies are the same. .

Reference numeral 2 is a low pass filter for smoothing the output, and 3 is a voltage controlled oscillator (abbreviated as VCO) whose oscillation frequency is controlled by the output from the low pass filter.
Its oscillation frequency is usually relatively high. Reference numeral 4 is a frequency divider for dividing the frequency of the output from the VCO, and its output becomes a feedback signal V to the phase comparator. The VCO output is often used as the output of the PLL, and the frequency divider 4 may be omitted depending on the application.

FIG. 8 shows a circuit example of the phase comparator 1 normally used in a PLL. The left half of the circuit is composed of a digital sequential circuit 5 for phase comparison, and an on / off output corresponding to the phase difference between the signals R and V is output to a terminal 6 (the signal is abbreviated as U).
And terminals 7 (signals are abbreviated as D), and signals U and D are output from the respective terminals.

The right half indicated by reference numeral 8 is a charge pump section, which synthesizes a single phase comparison output corresponding to each voltage at the terminals 6 and 7 and supplies it to the loop filter at the subsequent stage from the terminal 9.

Since the PLL is constructed in this way,
The feedback signal V first follows the frequency of the input signal R, and when the frequencies become the same, phase tracking starts, and a so-called synchronized state in which the phases of both signals match can be reached.
Therefore, it is effectively used in a wide range such as frequency multiplication and frequency synthesis.

[0007]

However, there are cases where the PLL using the normal phase comparator as described above does not operate effectively, which will be described below. The sequential circuit 5 including the flip-flop outputs only the current R and V signals and outputs U and
It does not determine D, but relates to the past process.

Each of the four signals R, V, U, and D is a logical signal of "1" or "0" that changes with time, and there are 16 combinations, of which 12 are stable. There are directions in which these 12 states can be moved to each other, and FIG. 9 shows this relationship.

Here, the duty of R and V is small,
Further, FIG. 10 shows the correspondence between the waveforms and the states in FIG. 9 when the phase difference between them is smaller than 180 °. However, the phase comparator used is of the type that detects the falling edges of R and V, and the outputs U and D are configured so that the "0" state becomes an effective output through the charge pump 8.

In FIG. 10, when the phase of V is delayed with respect to R, a "0" state appears on the U side to advance the phase of V, so to speak, a so-called converging polarity output state, and conversely, a long state on the D side.
The 0 "state appears, and there is an output form that should be called the divergent polarity, which is to further delay the phase of V, and which form to take depends on the past progress.

In the right half of FIG. 10, a path of convergent polarity is shown by a solid line,
Divergent polarity paths are shown by dashed lines. A similar situation exists when V is ahead of R in phase. In a general PLL application example, since the input signal R is independent of the PLL, even if the phase of the feedback signal V which is delayed due to the output of the divergence polarity mentioned here is further delayed, it is eventually synchronized if it reaches 360 °. You can get into the state and it doesn't matter. Therefore, in general, the polarities of the outputs are not treated separately.

However, a concrete example of the case where the input signal R is affected by the feedback signal V and causes a problem is shown in FIG.
The LL type ultrasonic flowmeter will be described. Reference numeral 1 in FIG.
4 are the same as the components of the PLL shown in FIG. 7,
The description is omitted.

In the figure, reference numeral 10 is a conduit through which a fluid to be measured flows, and 11 and 11 'are a pair of ultrasonic transducers obliquely attached to the conduit. Operates as a receiver.

Further, reference numeral 12 is an excitation circuit that generates a pulse in synchronization with the output of the frequency divider 4 in the PLL and excites one transducer to transmit an ultrasonic wave. Reference numeral 13 is an ultrasonic wave propagated in the fluid. Reference numeral 14 is an amplifier for amplifying an ultrasonic wave reception signal generated when a sound wave is detected by the other vibrator, and 14 is an ultrasonic wave vibrator 11
And a switching device for switching the excitation circuit 12 to switch the propagation direction of ultrasonic waves.

The measuring principle of the PLL type ultrasonic flowmeter is already known and will not be described in detail here, but the point is that it is PL.
In the synchronized state of L, the system self-oscillates at a frequency at which the input signal R, that is, the reception wave of the receiver and the feedback signal V, that is, the transmission wave of the transmitter are in phase, and the oscillation frequency is the ultrasonic propagation time T in the fluid. It is used to be the reciprocal of.

As is apparent from the above description, here, the input signal R of the PLL is electrically equivalent to the feedback signal V obtained through the delay circuit having the delay time T, and is not independent from each other.

Therefore, if a normal phase comparator is used for this PLL, the PLL will be used when its output has the above-mentioned convergent polarity.
Normally reaches the synchronization state, and an output frequency equal to the reciprocal of the desired propagation time is obtained, but in the case of divergent polarity, the phase of the input signal R also changes depending on the phase change of the feedback signal V. There is no opportunity to reach sync.

That is, run-away occurs, and the loop filter output reaches the maximum or minimum value. The synchronization state is not realized here and therefore the measurement purpose is not achieved.

Therefore, in the conventional PLL type ultrasonic flowmeter, it is necessary to develop and use a special phase comparator, or to adopt a specially modified PLL, resulting in a complicated circuit.
It was expensive.

[0020]

The present invention has been made to solve the above problems, and a phase locked loop according to the present invention receives two signals, an input signal and a feedback signal, and outputs the phase of both signals. A phase comparator that gives an output signal corresponding to the phase difference, a loop filter for smoothing the output from this phase comparator, and a voltage-controlled oscillator whose oscillation frequency is controlled by the loop filter output. The phase comparator has two input terminals for receiving the two signals and two output terminals for providing outputs for advancing or delaying the phase of the feedback signal via the loop filter and the voltage controlled oscillator, respectively. And a charge pump circuit for receiving the outputs from these two output terminals and synthesizing a single phase comparator output, and the output connected to each of the two output terminals. A detection circuit for detecting the convergence or divergence polarity of the output by measuring the magnitude relationship between the times of the signals "1" and "0", and the logical value required for the input signal or the feedback signal by the output of this detection circuit. An operation circuit is provided for changing the polarity of the output signal of the sequential circuit by applying a change operation.

Further, the phase-locked ultrasonic flowmeter according to the present invention receives two signals of an input signal and a feedback signal, compares the phases of both signals and gives an output signal according to the phase difference between them. , A loop filter for smoothing the output from this phase comparator, a voltage controlled oscillator whose oscillation frequency is controlled by the loop filter output, and a component for dividing the output of this voltage controlled oscillator into the feedback signal. A phase-locked loop composed of a frequency divider, a pair of ultrasonic transducers diagonally attached to the pipe through which the fluid flows, and one transducer is excited by the output from the frequency divider to generate ultrasonic waves. , An amplifier circuit that amplifies the ultrasonic reception signal generated in the other transducer and uses the output as the input signal of the phase comparator, and a switch that switches between the transmission and reception of the pair of transducers. Equipped with a vessel and above A phase comparator in the synchronization loop,
For a phase comparison having two input terminals for receiving the input signal and the feedback signal and two output terminals for giving an output for advancing or delaying the phase of the feedback signal via the loop filter, the voltage controlled oscillator and the frequency divider, respectively. Sequential circuit, a charge pump circuit that receives outputs from the two output terminals and synthesizes a single phase comparator output, and output signals "1" and "1" connected to the two output terminals, respectively.
A detection circuit that detects the convergence of the output or the divergence polarity of the output by measuring the magnitude relation of the time of the 0 "state, and the above-mentioned sequence by applying a required logical value changing operation to the input signal or the feedback signal by the output of this detection circuit. And an operation circuit for changing the polarity of the output signal of the circuit.

An embodiment of the above means is as follows.

<Embodiment 1> The phase difference between the input signal and the feedback signal is configured to be 180 ° or less, and the detection circuit receives an externally supplied clock signal and outputs the output of the sequential circuit. It counts up in the state of "1" and counts down in the state of "0", and it detects that the time of "0" has exceeded the time of "1" by the zero output of this counter. It has an up-down counter that operates.

<Embodiment 2> The phase difference between the input signal and the feedback signal is configured to be 180 ° or less, and the detection circuit receives an externally supplied clock signal and outputs the output of the sequential circuit. An up counter is provided which counts up during the state of "0" and detects that the time of the state of "0" exceeds the maximum possible value of the time of the state of "1" by the overflow output of this counter.

<Embodiment 3> The duty ratio of the input signal and the feedback signal is small, and the phase difference between the two signals is one.
The operation circuit has a double pulse generation circuit that generates two pulses in response to the output of the detection circuit, and an AND output of the circuit output and an input signal or a feedback signal. To a respective input terminal of the sequential circuit.

[0026]

The detection circuit detects that the output of the sequential circuit for phase comparison has a divergent polarity, and the operation circuit connected to the detection circuit changes the logical value of the input signal or the feedback signal of the sequential circuit. In addition, since the polarity of the output is changed to the convergent polarity, it is possible to prevent the output having the divergent polarity from being given to the loop filter.

In the phase-locked ultrasonic flowmeter, since the output of divergent polarity is not continuously given to the loop filter, the above-mentioned run-away phenomenon is prevented and the synchronized state is always realized. That is, it is effective that an inexpensive ordinary phase comparator having excellent performance can be used.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the first invention will be described below with reference to FIG. Note that, in the figure, reference numerals 1 to 9 correspond to the reference numerals in FIGS.

Reference numerals 15 and 15 'in the figure are connected to the output terminals 6 and 7 of the digital sequential circuit 5 to measure the magnitude relation between the times of the output signals in the "1" and "0" states to converge the outputs. Alternatively, a detection circuit for detecting the divergence polarity, 16 is a detection circuit 1
5 is an operation circuit for changing the polarity of the output signal of the digital sequential circuit 5 by applying a required logical value changing operation to be described later to the input signal R or the feedback signal V by the output of 5.
The phase comparator 101 in the LL is a conventional phase comparator 1 including a digital sequential circuit 5 and a charge pump unit 8.
In addition, the detection circuits 15 and 15 'and the operation circuit 16 are provided.

First, the case where V is delayed with respect to R will be described. As shown in FIG. 9, the output U is "0" in the converging polarity.
The time of the state of "0" of the output D of divergence polarity is longer than the state time. The same feature is that the input signal R and the feedback signal V
Can also be seen when is progressing.

Therefore, for example, focusing on the output U, it can be seen that when the "0" state is longer than the "1" state, the divergent polarity is obtained, and when the state is "1", the convergent polarity is obtained. Ie output U
The divergence polarity can be detected by measuring the magnitude relation between the times in the states of "1" and "0", that is, the ratio or difference between the two. Similarly, D can be detected by a detection circuit 15 'having the same configuration as the detection circuit 15'.

A more detailed example of the detection circuits 15 and 15 'is shown in FIG. 2 and another example is shown in FIG. FIG. 2 shows an example in which an up / down counter is used as the detection circuit 15. Reference numeral 17 is an inverter for inverting the logical value of U, 18 and 1
9 is an AND circuit, 20 is a clock terminal for receiving an externally supplied clock signal, 21 is an up-down counter, 22 is an up-counting clock input terminal, 2
3 is a down count clock input terminal, 24 is a borrow output terminal, and 25 is a one-shot circuit for resetting 21.

When the signal U is "1", the AND circuit 18
A clock signal is applied to the input terminal 22 through the up / down counter 21 to count up. During this time, the AND circuit 19 is in the cutoff state.

Next, when the output signal U becomes "0", the AND circuit 18 is cut off, the clock signal is applied to the input terminal 23 through the AND circuit 19, and the up / down counter 21 counts down. With convergent polarity output, the time of "0" state is short, so borrow output does not occur, but with divergent polarity output, "0" state is long, so that state corresponds to "1" state. After that, the borrow output appears at the borrow output terminal 24 and the output U
Is divergent polarity.

The one-shot circuit 25 generates a pulse when the output U is inverted to "1", and has a function of resetting the up-down counter 21 prior to the up-counting.

Another example of the detection circuit 15 shown in FIG. 3 is shown in FIG.
In the phase-locked ultrasonic flowmeter shown in FIG. 2, a simplified circuit suitable for setting the output frequency range of the voltage controlled oscillator 3 to a relatively narrow range is shown. 26 is an up counter, 27 is its reset input terminal, Reference numeral 28 is a clock terminal for receiving a clock signal given from the outside, and 29 is an output terminal for an overflow signal.

When the output U is "1", the up-counter 26 resets the counter and prohibits the counting operation. However, when the output U is "0", the clock applied to the clock terminal 28 is up-counted.

The number of digits of the up-counter 26 and the frequency of the clock are appropriately selected so that the overflow does not occur at the maximum value of the time of the state of the convergent polarity "0" (this is equal to the time of the state of the divergent polarity "1"). If it does not occur and overflow occurs slightly beyond this, the divergent polarity can be detected, and the convergent polarity output is not adversely affected.

Next, regarding the operation circuit 16 in the present invention,
A specific example of the phase comparator 101 shown in FIG. 4 will be described. In the figure, reference numerals 1 to 26 correspond to the reference numerals in FIGS.

Reference numeral 26 'in the figure is an up counter similar to the up counter 26, which corresponds to the detector 15' of the output D, and 29 'is its overflow output terminal. Reference numeral 30 is a double pulse generation circuit that generates two pulses according to the overflow output appearing at 29 or 29 ', and its configuration is composed of AND circuits 31, 31' and inverters 32, 32 ', and 33, 33. 'Is its output terminal.

Reference numeral 34 is a logic circuit for performing a logical operation on the input signal R or the feedback signal V by the output of the double pulse generation circuit 30, and its configuration is composed of AND circuits 35 and 35 '. The outputs of'are R'and V ', respectively. The operation unit 11 shown in FIG. 1 includes the double pulse generation circuit 30 and the logic circuit 34 described above.

In the example shown in FIG. 4, the waveforms R and V shown in FIG. 10 are used.
It is suitable to be applied to input, and up counters 26, 2
As 6 ', a BCD counter is used and its overflow output has a pulse width of two cycles of the clock signal. Therefore, the AND output of the overflow output and the clock signal obtained from the output terminals 29 and 29 'becomes two pulses of the positive clock.

State # 1 as described in the example of FIG.
When the divergence polarity is detected at 1 or # 3, R or V can be changed to the state of "0" twice, respectively. Therefore, the output of the AND circuits 31, 31 'is inverted by the inverters 32, 32'. The output of the inverter 32 is the AND circuit 3
5 ', the output of the inverter 32' is applied to the AND circuit 35. As a result, the output of the digital sequential circuit 5 shifts from the divergent polarity to the convergent polarity. FIG. 5 shows the waveform of the signal at this time. The signals R and V show the case where the phase of V is delayed with respect to R, and the outputs U and D have divergent polarity waveforms and the borrow output terminal 24 is not operated. The case is shown by a solid line. Since the output of the overflow output terminal 29 outputs a positive overflow pulse corresponding to two pulse widths of the clock at the time when the time when the state of D is "0" exceeds the time width corresponding to the state of "1", it is eventually output. The output waveform of the output terminal 33 'is "
The waveform is such that the state of "1" falls twice to the state of "0".
Further, the AND output R'of this output and R also corresponds to twice and becomes the "0" state. As a result, the state shifts from # 11 to # 6 as described above, where the output D is from "0" to "
After receiving the change to 1 ”and then going through # 7 to # 2, U
Changes from "1" to "0" and the state reaches # 3.
R'and V'at this time are shown in FIG. The waveforms of the outputs U and D after the operation are shown by broken lines. Both U and D become convergent polarity outputs in the subsequent cycles of R and V.

In the example of FIG. 4, the operation unit 16 is a combination of the double pulse generation circuit 30 and the logic circuit 34.
If a pair of shift registers is used instead of the double pulse generation circuit 30, a more complicated logic value changing operation than this example can be performed.

It is also possible to substitute the functions of the detection circuits 15 and 15 'and the operation circuit 16 by a microprocessor. Further, although the output signals U and D are used in the present invention, the output of the charge pump circuit 8 can be used instead. However, it is necessary to determine whether the output used in this case is the output from the output terminal 6 or the output from 7 of the digital sequential circuit 5 by another means.

Next, an ultrasonic flowmeter according to the second invention will be described with reference to FIG. In the figure, reference numerals 1 to 4 and 10 to 14 correspond to the reference numerals in FIG.
Since 5'and 16 correspond to the reference numerals in FIG. 1, their explanations are omitted.

The difference between the present invention and the conventional example of FIG. 11 is that the divergence polarities of the outputs U and D of the sequential circuit 5 of the phase comparator 101 shown in FIG. 1 are changed without the need for a specially developed phase comparator. Since the operation circuit 16 detects the detection circuits 15 and 15 'and applies a required logical value changing operation to the input signal R or the feedback signal V, the divergence polarity is changed to the convergent polarity in a short time. Therefore, the so-called run-away phenomenon does not occur and normal measurement becomes possible.

The phase locked loop according to the present invention can be used for other than the ultrasonic flowmeter. That is, if the electric circuit between the excitation circuit 12 and the amplifier 13 is replaced with an electric delay circuit in FIG. 6, this circuit enables measurement of the delay time (reciprocal number) of the output frequency of the voltage controlled oscillator 3 with high resolution. is there.

Further, in FIG. 6, the speed of sound in the fluid can be measured with high resolution from the output frequency of the voltage controlled oscillator 3 when the flow velocity of the fluid is zero. Further, it is also possible to measure the temperature of the fluid from the velocity of sound with high resolution by using a fluid whose temperature characteristic of the velocity of sound is known.

[0050]

According to the present invention described in claim 1 as described above with reference to the embodiments, the divergence polarity output is detected from the output of the sequential circuit in the phase comparator to detect the phase comparator input or the feedback signal. Since the divergence polarity can be changed to the convergent polarity by the operation, the phase locked loop can be effectively applied in an application example in which the input signal and the feedback signal are not independent of each other.

Further, according to the embodiments shown in the first, second and third embodiments, it is possible to obtain a phase-locked loop having a relatively inexpensive and simple circuit structure, and further, the present invention according to claim 2 According to this, the run-away phenomenon can be prevented and normal measurement can be performed without using a special phase comparator or a modification circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a phase comparator in a phase locked loop according to the present invention.

FIG. 2 is a circuit diagram showing an embodiment of a detection circuit.

FIG. 3 is a circuit diagram showing another embodiment of the detection circuit.

FIG. 4 is a circuit diagram of a phase comparator in a phase locked loop according to the present invention.

FIG. 5 is a waveform diagram of input / output signals.

FIG. 6 is a configuration diagram of a phase-locking ultrasonic flowmeter according to the present invention.

FIG. 7 is a basic configuration diagram of a phase locked loop.

FIG. 8 is a configuration diagram of a comparator used in a conventional phase locked loop.

FIG. 9 is an explanatory diagram of an operating state of a sequential circuit for phase comparison.

FIG. 10 is an explanatory diagram of correspondence between input / output waveforms and operating states.

FIG. 11 is a basic configuration diagram of a phase-locking ultrasonic flowmeter.

[Explanation of symbols]

 1 Phase Comparator 2 Low Pass Filter 3 Voltage Controlled Oscillator 4 Frequency Divider 5 Digital Sequential Circuit 6, 7 ON / OFF Output Terminal 8 Charge Pump Section 9 Phase Comparison Output Terminal 10 Pipeline 11, 11 'Ultrasonic Transducer 12 Excitation Circuit 13 Amplifier 14 Switcher 15 and 15 'Detection circuit 16 Operation circuit 17 Inverter 18, 19 AND circuit 20 Clock terminal 21 Up-down counter 22 Up-counting clock terminal 23 Down-counting clock terminal 24 Borrow output terminal 25 One-shot circuit 26, 26 'Up counter 27 Reset input terminal 28 Clock terminal 29, 29' Overflow output terminal 30 Double pulse generation circuit 31, 31 'AND circuit 32, 32' Inverter 33, 33 'Output terminal 34 Logic circuit 35, 35' AND circuit 01 phase comparator

[Procedure amendment]

[Submission date] October 12, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

Further, reference numeral 12 is an excitation circuit that generates a pulse in synchronization with the output of the frequency divider 4 in the PLL and excites one transducer to transmit an ultrasonic wave. Reference numeral 13 is an ultrasonic wave propagated in the fluid. Reference numeral 14 is an amplifier for amplifying an ultrasonic wave reception signal generated when a sound wave is detected by the other vibrator, and 14 is an ultrasonic wave vibrator 11
And 11 ' for switching the propagation direction of ultrasonic waves.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

[0020]

The present invention has been made to solve the above problems, and a phase locked loop according to the present invention receives two signals, an input signal and a feedback signal, and outputs the phase of both signals. A phase comparator that gives an output signal corresponding to the phase difference, a loop filter for smoothing the output from this phase comparator, and a voltage-controlled oscillator whose oscillation frequency is controlled by the loop filter output. The phase comparator has two input terminals for receiving the two signals and two output terminals for providing outputs for advancing or delaying the phase of the feedback signal via the loop filter and the voltage controlled oscillator, respectively. And a charge pump circuit for receiving the outputs from these two output terminals and synthesizing a single phase comparator output, and the output connected to each of the two output terminals. "1" and "0" and a pair of sensing circuit measures the magnitude of the time of the state for detecting the convergence or divergence polarity of the output of the signal, required to the input signal or the feedback signal by the output of the detection circuit The operation circuit for changing the polarity of the output signal of the sequential circuit is provided by adding the logical value changing operation.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

Further, the phase-locked ultrasonic flowmeter according to the present invention receives two signals of an input signal and a feedback signal, compares the phases of both signals and gives an output signal according to the phase difference between them. , A loop filter for smoothing the output from this phase comparator, a voltage controlled oscillator whose oscillation frequency is controlled by the loop filter output, and a component for dividing the output of this voltage controlled oscillator into the feedback signal. A phase-locked loop composed of a frequency divider, a pair of ultrasonic transducers diagonally attached to the pipe through which the fluid flows, and one transducer is excited by the output from the frequency divider to generate ultrasonic waves. , An amplifier circuit that amplifies the ultrasonic reception signal generated in the other transducer and uses the output as the input signal of the phase comparator, and a switch that switches between the transmission and reception of the pair of transducers. Equipped with a vessel and above A phase comparator in the synchronization loop,
For a phase comparison having two input terminals for receiving the input signal and the feedback signal and two output terminals for giving an output for advancing or delaying the phase of the feedback signal via the loop filter, the voltage controlled oscillator and the frequency divider, respectively. Sequential circuit, a charge pump circuit that receives outputs from the two output terminals and synthesizes a single phase comparator output, and output signals "1" and "1" connected to the two output terminals, respectively.
A pair of detection circuits that detect the convergence of the output or the divergence polarity of the output by measuring the magnitude relation of the time of the 0 "state, and the required logical value changing operation is added to the input signal or the feedback signal by the output of this detection circuit. And an operation circuit for changing the polarity of the output signal of the sequential circuit.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0029

[Correction method] Change

[Correction content]

Reference numerals 15 and 15 'in the figure are connected to the output terminals 6 and 7 of the digital sequential circuit 5 to measure the magnitude relation between the times of the output signals in the "1" and "0" states to converge the outputs. Alternatively, a detection circuit for detecting the divergence polarity, 16 is a detection circuit 1
5 and 15 ' is an operation circuit for changing the polarity of the output signal of the digital sequential circuit 5 by applying a required logical value changing operation to be described later to the input signal R or the feedback signal V, and the phase in the PLL of the present invention. The comparator 101 is the same as the conventional phase comparator 1 composed of the digital sequential circuit 5 and the charge pump unit 8, but also includes the detection circuits 15 and 15 ′ and the operation circuit 1.
6 is provided.

[Procedure correction 6]

[Document name to be amended] Statement

[Name of item to be corrected] 0030

[Correction method] Change

[Correction content]

First, the case where V is delayed with respect to R will be described. As shown in FIG. 9, the state of the output D of the divergent polarity is "0" as compared with the "0" state time of the output U of the convergent polarity. Is long. Similar characteristics can be seen when the feedback signal V leads the input signal R.

Claims (2)

[Claims] (A) (a) receives two signals, an input signal and a feedback signal,
A phase comparator that compares the phases of both signals and gives an output signal according to the phase difference, a loop filter for smoothing the output from this phase comparator, and a voltage whose oscillation frequency is controlled by the loop filter output. A controlled oscillator, and (b) the phase comparator advances or delays the phase of the feedback signal via (b-1) two input terminals for receiving the two signals and the loop filter and the voltage controlled oscillator, respectively. A sequential circuit for phase comparison having two output terminals for giving outputs, (b-2) a charge pump circuit for receiving outputs from these two output terminals and synthesizing a single phase comparator output,
(b-3) A detection circuit which is connected to the above-mentioned two output terminals and detects the convergence or divergence polarity of the output by measuring the magnitude relation of the time of the state of "1" and "0" of the output signal, (b-
4) An operation circuit for changing the polarity of the output signal of the sequential circuit by applying a required logical value changing operation to the input signal or the feedback signal by the output of the detection circuit, . 2. A feedback signal of an input signal and two signals are received,
A phase comparator that compares the phases of both signals and gives an output signal according to the phase difference, a loop filter for smoothing the output from this phase comparator, and a voltage whose oscillation frequency is controlled by the loop filter output. A phase-locked loop consisting of a controlled oscillator and a frequency divider that divides the output of this voltage-controlled oscillator into a feedback signal, (b) A pair of ultrasonic waves diagonally attached facing the fluid flow path. Transducer, (c) Excitation circuit that excites one oscillator by the output from the above frequency divider to transmit ultrasonic waves, (d) Amplifies the ultrasonic reception signal generated in the other oscillator and outputs it An input signal of the phase comparator, (e) a switch for switching between transmission and reception of the pair of transducers,
(F) The phase comparator in the above phase locked loop is (f-1)
A phase having two input terminals for receiving two signals of the input signal and the feedback signal, and two output terminals for giving an output for advancing or delaying the phase of the feedback signal via the loop filter, the voltage controlled oscillator and the frequency divider, respectively. Sequential circuit for comparison, (f-2) Charge pump circuit that receives outputs from these two output terminals and synthesizes a single phase comparator output,
(f-3) A detection circuit which is connected to the above-mentioned two output terminals and detects the convergence or divergence polarity of the output by measuring the magnitude relation of the time of the state of "1" and "0" of the output signal, (f-
4) An operation circuit for changing the polarity of the output signal of the sequential circuit by applying a required logical value changing operation to the input signal or the feedback signal by the output of the detection circuit, Ultrasonic flow meter.