JPH0871216A - Pachinko game machine - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] In a configuration in which a security program that is reset at predetermined time intervals and inspects a control program is executed, and then the control program is executed,
Make sure to execute the control program. SOLUTION: When output of a system reset signal from a system reset signal generation circuit 14 is stopped, a CPU 16 executes a security program stored in a built-in ROM 16a so that a control program stored in a ROM 21 is true. After confirming the existence, the control program is executed and the M1 signal is output. Here, the activation control circuit 19 releases the reset state of the reset signal generation circuit 18 when the M1 signal is output from the CPU 16. As a result, the reset circuit 18 outputs C
Since the reset signal is output to the PU 16 at a constant cycle, the CPU 13 can reliably execute the first control program.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pachinko game machine that completes a series of control operations before being reset at predetermined time intervals.

[0002]

Conventionally, in a pachinko game machine, a CPU (Central Processing Uni
By t), a series of control operations are executed.

By the way, the CPU may run out of control due to electrical noise and may not reliably execute the control operation.
Conventionally, pachinko game machines have taken noise countermeasures so that the runaway does not continue even if the CPU runs out of control. That is, the CPU is reset every predetermined time, and the series of control operations by the CPU is completed before the next reset. Therefore, even if the CPU should run away due to noise,
Will work normally after the next reset, so
It is possible to prevent the runaway state of the CPU from continuing.

FIG. 8 schematically shows the structure of a control device of this type of pachinko game machine. In this FIG.
The power supply monitor 1 outputs a system reset signal to the CPU 2 until the power is turned on. The oscillator circuit 3 outputs a clock signal of a predetermined cycle to the clock terminal of the CPU 2 and the frequency divider circuit 4. The frequency dividing circuit 4 outputs a reset signal of a predetermined cycle to the reset terminal of the CPU 2 by dividing the pulse signal from the oscillation circuit 3 a plurality of times. In this case, the frequency dividing circuit 4 is set to operate from the timing when the output state of the system reset signal from the power supply monitor 1 is released.

A control program is stored in the ROM 5, and the CPU 2 controls various electric devices 7 through the input / output interface 6 in accordance with the control program stored in the ROM 5. Here, the CPU 2 has a built-in R
It has an OM2a, and its built-in ROM2a has a ROM
A security program for checking the authenticity of the control program stored in 5 is stored. When the output of the system reset signal from the power supply monitor 1 is stopped, the CPU 2 executes the security program stored in the built-in ROM 2a to inspect the control program stored in the ROM 5 by a predetermined method. . At this time, when the CPU 2 determines that the control program is different from the one that has been previously certified, it stops the operation without executing the control program, and when it determines that the control program is the one that has been certified. The control program is executed.

Therefore, when the control program stored in the ROM 5 is true, the CPU 2 repeatedly executes the control program each time the reset signal is input from the frequency dividing circuit 4 to execute various control programs through the input / output interface 6. The electric device 7 is controlled.

However, in the above conventional example, C
Since the frequency divider circuit 4 for outputting the reset signal to the PU 2 starts operating at the timing when the output state of the system reset signal from the power supply monitor 1 is stopped, the frequency divider circuit 4 outputs the first reset signal. As shown in FIG. 9, the predetermined time T elapses after the CPU 2 starts executing the security program as the system reset signal is released. Therefore, when the total time of the execution time of the security program and the execution time of the control program is shorter than the output interval of the reset signal from the frequency dividing circuit 4, as shown in FIG. Since the CPU 2 is reset during execution, the first control process is interrupted in the middle of the process, and there is a possibility that subsequent control of the various electric devices 7 cannot be reliably executed.

In this case, the control program may be modified so that the interruption of the first control process does not adversely affect the second and subsequent processes, but under the condition that the program capacity is limited. Correctly modifying the program in this manner is difficult and requires a large amount of development cost.

On the other hand, when an instantaneous blackout occurs, the CPU 2 is immediately reset to prevent runaway of the CPU 2. However, if an instantaneous blackout occurs during execution of the control program by the CPU 2, the control program Will be interrupted on the way, and there is a possibility that the control for the various electric devices 7 cannot be reliably executed. Further, when the reset state for the CPU 2 is immediately released when the instantaneous blackout is released, the CPU 2 is reset by the reset signal from the frequency dividing circuit 4 during the execution of the control program by the CPU 2, and in this case as well, There is a possibility that the control of the electric device 7 cannot be reliably executed.

The present invention has been made in view of the above circumstances, and an object thereof is to execute a control program which is reset every predetermined time and which executes the security program for inspecting the control program. Provided is a pachinko game machine capable of reliably executing a control program with a simple configuration and capable of reliably executing the control program regardless of an abnormality in a power supply in a configuration that is reset every predetermined time. It is in.

[0011]

The pachinko game machine of the present invention is provided with a system reset means for outputting a system reset signal until the power is turned on, and with a reset means for outputting a reset signal at every predetermined time. A storage means storing a control program set so that the execution is completed within an output interval of the reset signal from the means is provided, and a security program for inspecting the authenticity of the control program stored in the storage means is provided. When it is stored in advance and the output state of the system reset signal from the system reset means is released, the security program is executed to confirm that the control program is true, and then the control program is executed. It is reset according to the output of the reset signal from the reset means. The control means is provided, and the start control means is provided for starting the reset means when a start signal is first input in a non-output state of the system reset signal from the system reset means. The start signal is input when the control means starts executing the control program (claim 1).

In this structure, when the power is turned on, the system reset means stops outputting the system reset signal. Then, the control means determines the authenticity of the control program stored in the storage means by executing the security program. At this time, when the control means determines that the control program is true, the control means executes the control program.

Here, when the activation control means inputs the activation signal when the control means starts executing the control program in the non-output state of the system reset signal from the system reset means, the activation control means activates the reset means from the timing. As a result, the reset means outputs the reset signal at every predetermined time from that timing, so that the reset signal is given to the control means at every predetermined time from the execution timing of the control program. Therefore, the control means can surely execute the control program following the execution of the security program until the next reset.

In the above structure, the control means is configured to output a program execution signal during execution of the control program, and the activation control means inputs the program execution signal from the control means as a activation signal. You may do so (Claim 2).

In this structure, the control means outputs the program execution signal during execution of the control program. At this time, since the activation control means inputs the program execution signal from the control means as the activation signal, the reset means can be activated at the start of execution of the control program by the control means.

A start signal output means for outputting a start signal to the start control means in response to a command from the control means is provided, and the control means operates the start signal output means at the end of execution of the security program. You may make it perform (Claim 3).

In this structure, the control means operates the start signal output means at the end of execution of the security program. Then, the activation signal output means outputs the activation signal to the activation control means, so that the reset means can be activated when the control means starts executing the control program.

A start signal output means for outputting a start signal to the start control means in response to a command from the control means is provided, and the control means operates the start signal output means at the start of execution of a control program. You may make it perform (Claim 4).

In this case, the control means operates the start signal output means at the start of execution of the control program. Then, the activation signal output means outputs the activation signal to the activation control means, so that the reset means can be activated when the control means starts executing the control program.

Further, the activation signal output means may be provided in an input / output interface interposed between the control means and a device to be controlled by the control means (claim 5).

In the case of this configuration, by providing the start signal output means in the input / output interface, it is possible to easily output the start signal from the outside.

Further, the pachinko game machine of the present invention is provided with a reset means for outputting a reset signal at every predetermined time, and the control program is set so that the execution is completed within the output interval of the reset signal from the reset means. Is provided with a storage means that stores therein a control means that executes a control program stored in the storage means and that is reset according to the output of a reset signal from the reset means, and detects a power supply abnormality. Providing detection means,
The first reset signal from the reset means when the abnormality detection means stops detecting the abnormality of the power supply after the first reset signal is output from the reset means in the state where the power abnormality detection means detects the abnormality of the power supply. Power supply abnormality resetting means for outputting a reset signal to the control means until is output (claim 6).

In the case of this configuration, when an abnormality such as a momentary power failure or a drop in the power supply voltage occurs, the control means may not be able to reliably execute the control program. At this time, when an abnormality occurs in the power supply, the power supply abnormality detection means detects the abnormality, and therefore the power supply abnormality reset means resets the first reset from the reset means in the state where the power supply abnormality detection means detects the power supply abnormality. When output, a reset signal is output to the control means. As a result, the control means is not immediately stopped when an abnormality occurs in the power supply, so that the control program can be reliably executed without interruption.

Here, the power supply abnormality resetting means continues to output the reset signal until the first reset signal is input from the resetting means in the state where the power supply abnormality detecting means stops detecting the power supply abnormality. As a result, the control means
Since the control program is not immediately started when the abnormality of the power supply is resolved, the control program can be surely executed without interruption.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will now be described with reference to FIG.
It will be described with reference to FIGS. FIG. 2 schematically shows an electrical configuration of a pachinko game machine. In FIG. 2, the power supply device 11 is composed of a smoothing circuit in which a rectifying element and a power storage element are combined, and in a state in which alternating current is converted into direct current, the control device 12 and various electric devices 13 such as electric accessory or lamp.
Power. The control device 12 controls the operation of the various electric devices 13 by operating with power supplied from the power supply device 11.

FIG. 1 schematically shows the controller 12. In FIG. 1, the system reset signal generation circuit 14 as the system reset means is a power supply device 11.
A low-level system reset signal is output to the system reset terminal of the CPU 16 as the control means until the charging voltage of the capacitor 15 becomes equal to or higher than the predetermined voltage in response to the supply of the DC voltage from.

The oscillator circuit 17 outputs a clock signal of a predetermined cycle to the clock terminal of the CPU 16 and the clock terminal of a reset signal generating circuit 18 as a reset means.
The reset signal generating circuit 18 is composed of a frequency dividing circuit, frequency-divides the clock signal from the oscillation circuit 17, and outputs a pulse signal of a predetermined cycle to the reset terminal of the CPU 16. The reset signal generation circuit 18 operates when the reset terminal is in a low level state.

The activation control circuit 19 as the activation control means is composed of a flip-flop, which outputs a high level signal from the inverting output terminal when the input level of the clear terminal is low level, and a clock when the input level of the clear terminal is high level. When a signal is input, the inverted output terminal outputs a signal having a level obtained by inverting the input level of the data terminal. In this case, the clear terminal of the activation control circuit 19 is connected to the output terminal of the system reset circuit 14, the clock terminal is connected to the M1 terminal of the CPU 16 via the inverter 20, and the data terminal is connected to the power supply terminal. There is. The inverting output terminal of the start control circuit 19 is connected to the reset terminal of the reset signal generation circuit 18.

The CPU 16 has a built-in ROM 16a in which a security program is stored. When the input level of the system reset terminal becomes high level, the built-in RO 16a.
The security program stored in M16a is executed. This security program is a program for inspecting the authenticity of the control program stored in the ROM 21 as a storage means.
In this case, the CPU 16 executes the control program after executing the security program when it determines that the control program is true by executing the security program, and executes the control program when it determines that the control program is false. It is designed not to run. Further, the CPU 16 repeatedly executes the control program each time a reset signal is input to the reset terminal. This control program is for controlling the various electric devices 13 through the input / output interface 22 based on the detection states of various sensors (not shown) and for storing the control state in the RAM 23.

In this case, the CP used in this embodiment
When executing the control program stored in the ROM 21, U16 is an M1 signal as a program execution signal from the M1 terminal (a signal output when the Z80 CPU accesses the program, and uses the 68 CPU. When the security program stored in the built-in ROM 16a is executed, the M1 signal is not output when the security program stored in the built-in ROM 16a is executed. Therefore, CPU1
When CPU 6 executes the security program, CPU
No M1 signal is output from 16.

Next, the operation of the above configuration will be described. When the AC power supply is turned on to the power supply device 11, a DC voltage is output from the power supply device 11 to the control device 12. At this time, in the control device 12, the capacitor 15 of the system reset signal generation circuit 14 gradually increases in voltage as it is charged from the discharged state. The output state of the system reset signal continues for the time.
As a result, the CPU 16 does not operate when the power supply voltage is unstable even when the clock signal of a predetermined cycle is input from the oscillator circuit 17.

When the power supply is completely turned on, the system reset signal generating circuit 14 causes the CPU to operate as shown in FIG.
The system reset signal output to 16 is released. Then, the CPU 16 inspects the control program stored in the ROM 21 by executing the security program stored in the built-in ROM 16a. That is, the CPU 16 inspects the control program based on a predetermined method. When the control program is different from the content that has been previously authenticated, the CPU 16 does not execute the control program and the content that the control program is previously authenticated. When it matches with, the control program is executed.

On the other hand, when the output of the system reset signal from the system reset signal generation circuit 14 is stopped as described above, the input level of the clear terminal of the activation control circuit 19 becomes high level, so the activation control circuit 19 is It is ready for operation.

Now, the CPU 16 executes the control program stored in the ROM 21 subsequent to the execution of the security program. This control program is set to end within the output interval of the reset signal from the reset signal generation circuit 18. Then, the CPU 16
By executing the control program, the various electric devices 13 are controlled through the interface 22 and the operating state of the pachinko game machine is stored in the RAM 23.

Here, when executing the control program stored in the ROM 21, the CPU 16 outputs the M1 signal each time the control program is accessed. In this case, when the CPU 16 outputs the first M1 signal to the clock terminal of the activation control circuit 19, the activation control circuit 19
Is set and the output level of the inverting output terminal becomes low level. As a result, the reset state of the reset signal generation circuit 18 is released, so that the reset signal generation circuit 18
Performs a frequency division operation of outputting a reset signal each time the clock signal from the oscillation circuit 17 is frequency-divided a predetermined number of times. At this time, the reset signal generation circuit 18 outputs the reset signal after a predetermined time T has elapsed from the start of the operation as shown in FIG. 3, so that the CPU 16 waits until the reset signal generation circuit 18 outputs the first reset signal. Is the first
Execution of the control program for the second time has ended.

Then, the CPU 16 executes the control operation for the pachinko game machine by repeatedly executing the control program each time the reset signal is output from the reset signal generation circuit 18.

According to the above configuration, the activation control circuit 19 for outputting the reset signal to the CPU 16 has the CP
Since the U16 is configured to operate from the timing of outputting the first M1 signal in response to the execution of the control program following the execution of the security program, the CPU1
Even if 6 is reset at a predetermined cycle by the reset signal from the reset signal generation circuit 18, it is possible to prevent the CPU 16 from being reset during execution of the first control program. Therefore, unlike the conventional example in which the CPU may be reset after a lapse of a predetermined time from the execution of the security program for inspecting the control program, the CPU 16 executes the control program to reliably control the various electric devices 13. be able to.

Further, in the above embodiment, attention is paid to the fact that the CPU 16 is configured to output the M1 signal for the first time when the control program is executed, and the start control circuit 19 resets based on the output of the M1 signal. Since the signal generating circuit 18 is made to operate, it can be realized only by adding the activation control circuit 19 to the configuration of the conventional example. Therefore, since it can be realized without modifying the configuration or the program of the CPU 16 at all, it can be realized at a low cost while exhibiting the excellent effect as described above.

FIGS. 4 and 5 show a second embodiment of the present invention. The same parts as those of the first embodiment are designated by the same reference numerals and the description thereof will be omitted. Only different parts will be described. The second embodiment is characterized in that the activation control circuit 19 is activated by the program control of the CPU 16.

That is, the input / output interface 22 having a function as a start signal output means outputs a start signal to the clock terminal of the start control circuit 19 when the CPU 16 accesses a preset specific address. There is. Then, the CPU 16 is configured to access the input / output interface 22 at a specific address when the execution of the security program ends or the execution of the control program starts.

Now, the CPU 16 accesses a specific address at the end of execution of the security program or at the start of execution of the control program. Then, the activation signal is output from the input / output interface 22 to the activation control circuit 19 (see FIG. 5), and the activation control circuit 19 activates the reset signal generation circuit 18. As a result, the activation signal is output from the reset signal generation circuit 18 to the CPU 16 in a predetermined cycle, so that the CPU 16 is reset in a predetermined cycle. Therefore, as in the first embodiment,
The CPU 16 can surely execute the control program following the security program before the next reset.

The input / output interface 22 has a CP
Since the function of decoding the address from U16 is inherently provided, the configuration for determining whether or not the specific address is accessed from the CPU 16 can be easily implemented.

FIGS. 6 and 7 show a third embodiment of the present invention. The same parts as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. Only different parts will be described. The third embodiment is characterized in that a power supply abnormality detecting means for detecting an abnormality of the power supply device 11 is provided, and when the power supply abnormality detecting means detects a power supply abnormality, it outputs a reset signal to the CPU 16 at an appropriate timing. And

That is, the power supply abnormality detection circuit 24 as the power supply abnormality detection means monitors the voltage on the input side of the power supply device 11, and when the input voltage instantaneously becomes zero (so-called momentary blackout), When the voltage drops from the normal value, a high level signal is output to the power supply abnormality reset signal generation circuit 25 as the power supply abnormality resetting means. The power supply abnormality reset signal generation circuit 25 is used in the power supply abnormality detection circuit 2
When the first reset signal is input from the reset signal generation circuit 18 while the high level signal from 4 is input, N
A reset signal is output to the CPU 16 through the OR circuit 26. In this case, the power supply abnormality reset signal generation circuit 25
In the state where the high level signal from the power supply abnormality detection circuit 24 is cut off, the reset signal output state is continued until the reset signal generation circuit 18 outputs the first reset signal. The reset signal generation circuit 18
Outputs a reset signal to the CPU 16 through the NOR circuit 26.

Now, the commercial power source may momentarily stop due to various abnormalities or the voltage may drop. When the power supply becomes abnormal as described above, the CPU 16 is generally stopped so as not to operate abnormally.
If U16 is immediately stopped, the processing of the control program may be interrupted as shown in FIG. Also,
Even if the CPU 16 is immediately operated at the timing when the power is restored, the processing of the control program may be interrupted as shown in FIG. 7.

Therefore, in this embodiment, even if an abnormality occurs in the power source, the control program can be surely executed as follows. That is, the power supply abnormality detection circuit 24 outputs a high-level signal to the power supply abnormality reset signal generation circuit 25 when detecting the power supply abnormality. Then, the power supply abnormality reset signal generation circuit 25
When the first reset signal is input from the reset signal generation circuit 18 while the high level signal is input from the power supply abnormality detection circuit 24, the reset signal is output at that timing. As a result, the CPU 1 is passed through the NOR circuit 26.
Since the reset signal is output to 6, the CPU 16 is stopped.

In this case, even if an abnormality occurs in the power supply, the power supply state of the power supply device 11 continues for a while, so that the CPU 1
6 can continue to operate. Therefore, even if an abnormality occurs in the power supply, the CPU 16 can reliably execute the control program as shown in FIG.

Further, during the abnormal state of the power supply, the output state of the reset signal from the power supply abnormality reset signal generation circuit 25 to the CPU 16 continues, so that the CPU 16 continues the stopped state.

When the power supply abnormality is resolved and the power supply is restored, the power supply abnormality detection circuit 24 stops outputting the high level signal to the power supply abnormality reset signal generation circuit 25. Then, the power supply abnormality reset circuit 25 outputs to the CPU 16 when the first reset signal is output from the reset signal generation circuit 18 in the state where the input of the high level signal from the power supply abnormality detection circuit 24 is stopped. Since the output of the reset signal is stopped, the CPU 16 can surely execute the control program although the instantaneous blackout is released as shown in FIG.

The present invention is not limited to the above embodiment, but can be modified or expanded as follows. A 68-series CPU may be used as the CPU. The function as the activation signal output means may be provided independently from the input / output interface 22. The activation signal output means may be configured to output an activation signal to the activation control circuit 19 when the head address of the ROM 21 is accessed by the CPU 16.

[0051]

As is apparent from the above description, according to the pachinko game machine of the present invention, the control program is reset after the security program is reset every predetermined time and the control program is executed. In the configuration to be executed, the control program can be surely executed with a simple configuration, and in the configuration reset every predetermined time, the control program can be surely executed regardless of the abnormality of the power supply. It has an excellent effect that the electric device of the game machine can be surely controlled.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing an electrical configuration of a control device according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing the overall electrical configuration.

FIG. 3 is a timing chart showing the operation of the CPU.

FIG. 4 is a view corresponding to FIG. 1 showing a second embodiment of the present invention.

FIG. 5 is a view corresponding to FIG.

FIG. 6 is a view corresponding to FIG. 1 showing a third embodiment of the present invention.

FIG. 7 is a timing chart showing the operation of the CPU.

FIG. 8 is a view corresponding to FIG. 1 showing a conventional example.

FIG. 9 is a view corresponding to FIG.

[Explanation of symbols]

12 is a control device, 14 is a system reset signal generation circuit (system reset means), 16 is a CPU (control means), 18 is a reset signal generation circuit (reset means),
19 is a start control circuit (start control means), 21 is a ROM
(Memory means), 22 is an input / output interface (starting signal output means), 24 is a power supply abnormality detection circuit (power supply abnormality detection means), and 25 is a power supply abnormality reset signal generation circuit (power supply abnormality reset means).

Claims (6)

[Claims] 1. A system reset means for outputting a system reset signal until the power is turned on, a reset means for outputting a reset signal at every predetermined time, and an execution end within an output interval of the reset signal from the reset means. The storage means storing the control program set as described above, and the security program for checking the authenticity of the control program stored in the storage means are stored in advance, and the system reset signal is output from the system reset means. When the state is released, the security program is executed to confirm that the control program is true, and then the control program is executed and reset in accordance with the output of the reset signal from the reset means. Control means and system from said system reset means Startup control means for starting the reset means when the startup signal is first input in the non-output state of the set signal, wherein the startup control means receives the startup signal at the start of execution of the control program by the control means. A pachinko game machine characterized by being configured as follows. 2. The control means is configured to output a program execution signal during execution of a control program, and the activation control means inputs the program execution signal from the control means as an activation signal. The pachinko game machine according to claim 1. 3. A start signal output means for outputting a start signal to the start control means in response to a command from the control means is provided, and the control means operates the start signal output means at the end of execution of a security program. The pachinko game machine according to claim 1, wherein: 4. A start signal output means for outputting a start signal to the start control means in response to a command from the control means is provided, and the control means operates the start signal output means at the start of execution of a control program. Claim 1 characterized by the above.
Pachinko game machine described. 5. The start signal output means is provided in an input / output interface interposed between the control means and a control target device of the control means. Pachinko game machine. 6. Reset means for outputting a reset signal at predetermined time intervals, and storage means for storing a control program set so that the execution is completed within an output interval of the reset signal from the reset means. The control means for executing the control program stored in the storage means and being reset in response to the output of the reset signal from the reset means, the power supply abnormality detection means for detecting the power supply abnormality, and the power supply abnormality detection means The control is performed until the first reset signal is output from the reset means after the first reset signal is output from the reset means in a state where the abnormality is detected, and the abnormality detection means stops detecting the abnormality of the power supply. A pachinko game machine, comprising: a power supply abnormality resetting means for outputting a reset signal to the means.