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JPH0870062A - Electronic parts - Google Patents

Electronic parts

Info

Publication number
JPH0870062A
JPH0870062A JP6205107A JP20510794A JPH0870062A JP H0870062 A JPH0870062 A JP H0870062A JP 6205107 A JP6205107 A JP 6205107A JP 20510794 A JP20510794 A JP 20510794A JP H0870062 A JPH0870062 A JP H0870062A
Authority
JP
Japan
Prior art keywords
bumps
electronic component
chip
bump
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6205107A
Other languages
Japanese (ja)
Other versions
JP3104537B2 (en
Inventor
Hideyuki Yakeyama
英幸 焼山
Tadahiko Sakai
忠彦 境
Seiji Sakami
省二 酒見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP06205107A priority Critical patent/JP3104537B2/en
Publication of JPH0870062A publication Critical patent/JPH0870062A/en
Application granted granted Critical
Publication of JP3104537B2 publication Critical patent/JP3104537B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To provide an electronic component with bumps capable of coping with thermal breakdown which is to be caused by repetition of thermal expansion and thermal contraction. CONSTITUTION: In an electronic component 10 wherein a chip 3 is mounted on the one surface of a board 2, and bumps 4 are formed on the other surface, bumps formed at the positions corresponding with the end surfaces (a) of the chip 3 are made dummy bumps 4b. Thereby, when the dummy bumps 4b are thermally broken down, the life of the electronic component 10 is not affected, because the dummy bumps 4 are meaningless from the circuit viewpoint.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、バンプを有する電子部
品に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component having bumps.

【0002】[0002]

【従来の技術】近年、各種電子機器には、バンプ(突出
電極)を有する電子部品が次第に広範に用いられるよう
になってきている。図6は、主基板に実装された従来の
電子部品と歪振幅の分布を示す説明図である。この電子
部品1は、基板2の上面にチップ3を搭載し、下面に半
田より成るバンプ4をマトリクス状に多数個形成して構
成されている。チップ3の表面に形成された回路パター
ンの電極(図示せず)は、図示しない導電手段によりバ
ンプ4に電気的に接続されている。チップ3はボンド5
により基板2の表面に固着されており、また基板2の上
面にはチップ3を保護するためのモールド体6が形成さ
れている。この電子部品1は、主基板9の電極(図示せ
ず)にバンプ4によって固定されている。
2. Description of the Related Art In recent years, electronic parts having bumps (protruding electrodes) have been gradually and widely used in various electronic devices. FIG. 6 is an explanatory diagram showing a conventional electronic component mounted on a main board and a strain amplitude distribution. This electronic component 1 is configured by mounting a chip 3 on the upper surface of a substrate 2 and forming a large number of bumps 4 made of solder in a matrix on the lower surface. The circuit pattern electrodes (not shown) formed on the surface of the chip 3 are electrically connected to the bumps 4 by a conductive means (not shown). Chip 3 is bond 5
Is fixed to the surface of the substrate 2, and a mold body 6 for protecting the chip 3 is formed on the upper surface of the substrate 2. The electronic component 1 is fixed to the electrodes (not shown) of the main substrate 9 by the bumps 4.

【0003】図6の下部に歪振幅の分布図を示してい
る。この電子部品1を電子機器に組み込み、チップ3の
回路パターンに電流を流してチップ3を駆動させると、
チップ3は内部抵抗により発熱する。この発熱は、基板
2やモールド体6へ伝熱され、電子部品1は熱歪みを生
じる。図6はこの熱歪みを示すものであって、本発明者
がFEM(有限要素法)解析により解析して入手したも
のである。
A distortion amplitude distribution chart is shown at the bottom of FIG. When this electronic component 1 is incorporated into an electronic device and a current is applied to the circuit pattern of the chip 3 to drive the chip 3,
The chip 3 generates heat due to internal resistance. This heat is transferred to the substrate 2 and the mold body 6, and the electronic component 1 is thermally distorted. FIG. 6 shows this thermal strain, which the present inventor analyzed and obtained by FEM (finite element method) analysis.

【0004】この分布図から明らかなように、チップ3
の端面aの直下に対応するバンプ4aにおいて、歪振幅
は最も著しい。これは、チップ3に対して基板2やモー
ルド体6の熱膨張係数が著しく相違することに起因す
る。因みに、例えばガラエポ基板やモールド体の熱膨張
係数は20〜60×10-6/℃であるのに対し、チップ
3のそれは3〜4×10-6/℃であり、前者は後者の約
10倍である。
As is clear from this distribution chart, the chip 3
In the bump 4a corresponding to just below the end surface a of the strain amplitude, the strain amplitude is most remarkable. This is because the thermal expansion coefficient of the substrate 2 and the mold body 6 is significantly different from that of the chip 3. Incidentally, for example, the thermal expansion coefficient of a glass epoxy substrate or a molded body is 20 to 60 × 10 −6 / ° C., whereas that of the chip 3 is 3 to 4 × 10 −6 / ° C., and the former is about 10% of the latter. Double.

【0005】[0005]

【発明が解決しようとする課題】以上のことから、チッ
プ3の端面aに対応する位置のバンプ4aは、熱膨張と
熱収縮が繰り返されることにより疲労破壊が発生しやす
く、電子部品1と主基板9との電気的な接続の寿命が短
くなるという問題点があった。
From the above, the bump 4a at the position corresponding to the end face a of the chip 3 is liable to cause fatigue fracture due to repeated thermal expansion and thermal contraction, and thus the bumps 4a and the electronic component 1 There is a problem that the life of electrical connection with the substrate 9 is shortened.

【0006】そこで本発明は上記の点を勘案してなされ
たものであって、熱膨張と熱収縮の繰り返しに対処し、
電子部品と主基板との電気的な接続の長寿命化を図れる
電子部品を提供することを目的とする。
Therefore, the present invention has been made in consideration of the above points, and copes with repeated thermal expansion and thermal contraction,
An object of the present invention is to provide an electronic component capable of extending the life of electrical connection between the electronic component and the main board.

【0007】[0007]

【課題を解決するための手段】このために本発明は、基
板の一方の面にチップを搭載し、他方の面にバンプを形
成して成る電子部品において、チップの端面に対応する
位置に形成されるバンプをダミーバンプとするものであ
る。
To this end, the present invention provides an electronic component in which a chip is mounted on one surface of a substrate and bumps are formed on the other surface of the substrate at a position corresponding to the end surface of the chip. The bumps to be used are dummy bumps.

【0008】また基板の一方の面にチップを搭載し、他
方の面にバンプを形成して成る電子部品において、チッ
プの端面に対応する位置に形成されるバンプを他のバン
プよりも強固に固着される補強バンプとするものであ
る。
Further, in an electronic component in which a chip is mounted on one surface of a substrate and bumps are formed on the other surface, the bump formed at a position corresponding to the end surface of the chip is fixed more firmly than the other bumps. It is used as a reinforcement bump.

【0009】[0009]

【作用】上記構成において、ダミーバンプは疲労破壊し
ても電子部品と主基板との電気的な接続の寿命には影響
しない。
In the above structure, even if the dummy bumps are broken by fatigue, they do not affect the life of electrical connection between the electronic components and the main substrate.

【0010】また補強バンプは疲労破壊をしにくく、電
子部品と主基板との電気的な接続の寿命は長くなる。
Further, the reinforcing bumps are less likely to be damaged by fatigue, and the life of electrical connection between the electronic component and the main board is extended.

【0011】[0011]

【実施例】次に、図面を参照しながら本発明の実施例を
説明する。図1は本発明の第一実施例の電子部品の断面
図、図2は同底面図、図3は同部分断面図である。図6
に示す従来例と同一のものには同一符号を付すことによ
り、説明は省略する。
Embodiments of the present invention will now be described with reference to the drawings. 1 is a sectional view of an electronic component according to a first embodiment of the present invention, FIG. 2 is a bottom view of the same, and FIG. 3 is a partial sectional view of the same. Figure 6
The same parts as those of the conventional example shown in FIG.

【0012】図1および図2において、電子部品10の
基板2の下面にはバンプ4がマトリクス状に多数個形成
されているが、このうちチップ3の端面aに対応する位
置のバンプはダミーバンプ4bになっている(ダミーバ
ンプ4bは黒く塗りつぶしている)。ダミーバンプ4b
とは、チップ3の表面に形成された回路パターンの電極
と電気的に接続されていないものであって、回路的には
無意味なものである。
1 and 2, a large number of bumps 4 are formed in a matrix on the lower surface of the substrate 2 of the electronic component 10. Of these, the bumps at the positions corresponding to the end face a of the chip 3 are dummy bumps 4b. (The dummy bumps 4b are painted black). Dummy bump 4b
Means that it is not electrically connected to the electrodes of the circuit pattern formed on the surface of the chip 3, and is meaningless in terms of the circuit.

【0013】図6を参照して説明したように、チップ3
の端面aに対応するダミーバンプ4bは歪振幅が大き
く、熱膨張・熱収縮が繰り返されることにより疲労破壊
を生じるが、ダミーバンプ4bは回路的には無意味であ
り、したがって疲労破壊をしても主基板と電子部品10
の電気的な接続の寿命には影響を及ぼさない。
As described with reference to FIG. 6, the chip 3
The dummy bump 4b corresponding to the end face a of the has a large strain amplitude, and fatigue destruction occurs due to repeated thermal expansion and contraction, but the dummy bump 4b is meaningless in terms of a circuit, and therefore, even if fatigue fracture occurs, Board and electronic component 10
Does not affect the life of the electrical connection of.

【0014】図3に示すように、本実施例のダミーバン
プ4bは、熱伝導性の高い金属線などの伝熱材7により
チップ3に接続されている。したがってチップ3の発熱
は、伝熱材7を通してダミーバンプ4bに伝熱され、ダ
ミーバンプ4bから放熱される。すなわちこのダミーバ
ンプ4bは、放熱作用を有しており、ダミーバンプ4b
から放熱することにより、チップ3の発熱から電子部品
10を保護できる。
As shown in FIG. 3, the dummy bump 4b of this embodiment is connected to the chip 3 by a heat transfer material 7 such as a metal wire having a high thermal conductivity. Therefore, the heat generated by the chip 3 is transferred to the dummy bumps 4b through the heat transfer material 7 and radiated from the dummy bumps 4b. That is, this dummy bump 4b has a heat dissipation effect, and the dummy bump 4b
The electronic component 10 can be protected from heat generation of the chip 3 by radiating heat from the electronic component 10.

【0015】図4は本発明の第二実施例の電子部品の断
面図である。この電子部品20は、チップ3の端面aに
対応する位置には補強バンプ4cが形成されている。こ
の補強バンプ4cは、他のバンプ4よりも大形であっ
て、基板2の下面に強固に固着されており、したがって
上述した熱膨張と熱収縮が繰り返されても疲労破壊を生
じにくく、電子部品20と主基板との接続を大巾に長寿
命化することができる。
FIG. 4 is a sectional view of an electronic component according to the second embodiment of the present invention. In this electronic component 20, reinforcing bumps 4c are formed at positions corresponding to the end surface a of the chip 3. The reinforcing bumps 4c are larger than the other bumps 4 and are firmly fixed to the lower surface of the substrate 2. Therefore, even if the above-described thermal expansion and thermal contraction are repeated, fatigue fracture is unlikely to occur, and The life of the connection between the component 20 and the main board can be greatly extended.

【0016】次に、補強バンプ4cの形成方法の一例を
説明する。図5(a)(b)(c)は本発明の第二実施
例の補強バンプの形成方法の説明図である。図5(a)
は基板2の部分平面図、図5(b)は同部分側面図であ
って、基板2の上面に形成された電極8上には半田ボー
ル4’が搭載されている。ここで、通常のバンプ4が形
成される電極8上には1個の半田ボール4’が搭載され
ているが、補強バンプ4cが形成される大形の電極8’
上には複数個(本例では2個)の半田ボール4’が搭載
されている。
Next, an example of a method of forming the reinforcing bumps 4c will be described. 5 (a), (b) and (c) are explanatory views of the method for forming the reinforcing bumps according to the second embodiment of the present invention. FIG. 5 (a)
Is a partial plan view of the substrate 2, and FIG. 5B is a partial side view of the same. The solder balls 4 ′ are mounted on the electrodes 8 formed on the upper surface of the substrate 2. Here, one solder ball 4'is mounted on the electrode 8 on which the normal bump 4 is formed, but a large electrode 8'on which the reinforcing bump 4c is formed.
A plurality of (two in this example) solder balls 4'are mounted on the top.

【0017】この基板2を加熱炉で加熱して半田ボール
4’を溶融させた後、冷却して固化させると、図5
(c)に示すように電極8及び8’上には半球状のバン
プ4と補強バンプ4cが形成される。この補強バンプ4
cは、2個の半田ボール4’が融合してできたものであ
る。図5(c)に示すように、補強バンプ4cは通常の
バンプ4よりも扁平であって、より広面積で強固に電極
8’や基板2の上面に固着されており、したがって疲労
破壊を生じにくいものである。
When the substrate 2 is heated in a heating furnace to melt the solder balls 4'and then cooled to be solidified, FIG.
As shown in (c), hemispherical bumps 4 and reinforcing bumps 4c are formed on the electrodes 8 and 8 '. This reinforcement bump 4
The c is formed by fusing two solder balls 4 '. As shown in FIG. 5 (c), the reinforcing bumps 4c are flatter than the normal bumps 4, and are firmly fixed to the electrodes 8'and the upper surface of the substrate 2 in a wider area, so that fatigue fracture occurs. It's difficult.

【0018】[0018]

【発明の効果】以上説明したように本発明によれば、チ
ップの端面に対応する位置のバンプをダミーバンプや補
強バンプにするというきわめて簡単な手段により、熱膨
張と熱収縮の繰り返しによる疲労破壊に対処し、電子部
品と主基板の接続の長寿命化を図ることができる。
As described above, according to the present invention, it is possible to prevent fatigue damage due to repeated thermal expansion and thermal contraction by the extremely simple means of forming the bumps at the positions corresponding to the end faces of the chips as dummy bumps or reinforcing bumps. As a result, the life of the connection between the electronic component and the main board can be extended.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第一実施例の電子部品の断面図FIG. 1 is a sectional view of an electronic component according to a first embodiment of the present invention.

【図2】本発明の第一実施例の電子部品の底面図FIG. 2 is a bottom view of the electronic component according to the first embodiment of the present invention.

【図3】本発明の第一実施例の電子部品の部分断面図FIG. 3 is a partial sectional view of an electronic component according to a first embodiment of the present invention.

【図4】本発明の第二実施例の電子部品の断面図FIG. 4 is a sectional view of an electronic component according to a second embodiment of the present invention.

【図5】(a)本発明の第二実施例の補強バンプの形成
方法の説明図 (b)本発明の第二実施例の補強バンプの形成方法の説
明図 (c)本発明の第二実施例の補強バンプの形成方法の説
明図
5A is an explanatory diagram of a method for forming a reinforcing bump according to a second embodiment of the present invention. FIG. 5B is an explanatory diagram of a method for forming a reinforcing bump according to a second embodiment of the present invention. Explanatory drawing of the formation method of the reinforcement bump of an Example.

【図6】従来の電子部品と歪振幅の分布を示す説明図FIG. 6 is an explanatory diagram showing a conventional electronic component and strain amplitude distribution.

【符号の説明】[Explanation of symbols]

2 基板 3 チップ 4 バンプ 4b ダミーバンプ 4c 補強バンプ 10,20 電子部品 2 substrate 3 chip 4 bump 4b dummy bump 4c reinforcing bump 10, 20 electronic component

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】基板の一方の面にチップを搭載し、他方の
面にバンプを形成して成る電子部品において、前記チッ
プの端面に対応する位置に形成されるバンプをダミーバ
ンプとすることを特徴とする電子部品。
1. An electronic component having a chip mounted on one surface of a substrate and bumps formed on the other surface, wherein a bump formed at a position corresponding to an end surface of the chip is a dummy bump. And electronic components.
【請求項2】基板の一方の面にチップを搭載し、他方の
面にバンプを形成して成る電子部品において、前記チッ
プの端面に対応する位置に形成されるバンプを他のバン
プよりも強固に固着される補強バンプとすることを特徴
とする電子部品。
2. In an electronic component having a chip mounted on one surface of a substrate and bumps formed on the other surface, a bump formed at a position corresponding to an end surface of the chip is stronger than other bumps. An electronic component characterized by being a reinforcing bump fixed to the.
【請求項3】前記補強バンプが、複数の半田ボールを融
合させて形成されることを特徴とする請求項2記載の電
子部品。
3. The electronic component according to claim 2, wherein the reinforcing bump is formed by fusing a plurality of solder balls.
JP06205107A 1994-08-30 1994-08-30 Electronic components Expired - Fee Related JP3104537B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP06205107A JP3104537B2 (en) 1994-08-30 1994-08-30 Electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP06205107A JP3104537B2 (en) 1994-08-30 1994-08-30 Electronic components

Publications (2)

Publication Number Publication Date
JPH0870062A true JPH0870062A (en) 1996-03-12
JP3104537B2 JP3104537B2 (en) 2000-10-30

Family

ID=16501541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP06205107A Expired - Fee Related JP3104537B2 (en) 1994-08-30 1994-08-30 Electronic components

Country Status (1)

Country Link
JP (1) JP3104537B2 (en)

Cited By (13)

* Cited by examiner, † Cited by third party
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KR100349561B1 (en) * 1998-08-11 2002-08-21 후지쯔 가부시끼가이샤 Lsi package and inner lead wiring method thereof
US6642083B2 (en) 1996-03-22 2003-11-04 Hitachi, Ltd. Semiconductor device and manufacturing method thereof
US7091620B2 (en) 1996-03-22 2006-08-15 Renesas Technology Corp. Semiconductor device and manufacturing method thereof
US7123480B1 (en) 1998-08-18 2006-10-17 Oki Electric Industry Co., Ltd. Package structure for a semiconductor device
JP2007165420A (en) * 2005-12-12 2007-06-28 Matsushita Electric Ind Co Ltd Semiconductor device
JP2007317754A (en) * 2006-05-24 2007-12-06 Matsushita Electric Ind Co Ltd Semiconductor device
US7421283B2 (en) 1996-11-27 2008-09-02 Hitachi Communication Technologies, Ltd. Transmission power control method and apparatus for mobile communication system
WO2009116517A1 (en) * 2008-03-17 2009-09-24 日本電気株式会社 Electronic device and method for manufacturing the same
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JP2011160009A (en) * 1996-03-28 2011-08-18 Intel Corp Method of reducing stress due to thermal expansion difference between board and integrated circuit die mounted on first surface of the same
JP2012063279A (en) * 2010-09-16 2012-03-29 Toshiba Corp Solder joint part life prediction method, solder joint part life prediction device, and electronic apparatus
JP2015106617A (en) * 2013-11-29 2015-06-08 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation Substrate bonding method, bump forming method, and semiconductor device

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642083B2 (en) 1996-03-22 2003-11-04 Hitachi, Ltd. Semiconductor device and manufacturing method thereof
US6664135B2 (en) 1996-03-22 2003-12-16 Renesas Technology Corporation Method of manufacturing a ball grid array type semiconductor package
US7091620B2 (en) 1996-03-22 2006-08-15 Renesas Technology Corp. Semiconductor device and manufacturing method thereof
US7420284B2 (en) 1996-03-22 2008-09-02 Renesas Technology Corp. Semiconductor device and manufacturing method thereof
JP2011160009A (en) * 1996-03-28 2011-08-18 Intel Corp Method of reducing stress due to thermal expansion difference between board and integrated circuit die mounted on first surface of the same
JP2014187410A (en) * 1996-03-28 2014-10-02 Intel Corp Method for reducing stress due to thermal expansion difference between board and integrated circuit die mounted on first surface of the board
US7421283B2 (en) 1996-11-27 2008-09-02 Hitachi Communication Technologies, Ltd. Transmission power control method and apparatus for mobile communication system
KR100349561B1 (en) * 1998-08-11 2002-08-21 후지쯔 가부시끼가이샤 Lsi package and inner lead wiring method thereof
US7123480B1 (en) 1998-08-18 2006-10-17 Oki Electric Industry Co., Ltd. Package structure for a semiconductor device
US7514768B2 (en) 1998-08-18 2009-04-07 Oki Electric Industry Co., Ltd. Package structure for a semiconductor device incorporating enhanced solder bump structure
JP2007165420A (en) * 2005-12-12 2007-06-28 Matsushita Electric Ind Co Ltd Semiconductor device
JP2007317754A (en) * 2006-05-24 2007-12-06 Matsushita Electric Ind Co Ltd Semiconductor device
WO2009116517A1 (en) * 2008-03-17 2009-09-24 日本電気株式会社 Electronic device and method for manufacturing the same
US8525333B2 (en) 2008-03-17 2013-09-03 Renesas Electronics Corporation Electronic device and manufacturing method therefor
CN101615649A (en) * 2008-06-27 2009-12-30 斯坦雷电气株式会社 Optical semiconductor device
JP2010223859A (en) * 2009-03-25 2010-10-07 Toshiba Corp Monitoring device and monitoring method
JP2012063279A (en) * 2010-09-16 2012-03-29 Toshiba Corp Solder joint part life prediction method, solder joint part life prediction device, and electronic apparatus
US8965712B2 (en) 2010-09-16 2015-02-24 Kabushiki Kaisha Toshiba Life predicting method for solder joint, life predicting apparatus for solder joint and electronic device
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