JPH0869696A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Purpose] Enables page read and random read,
To provide a semiconductor memory device capable of particularly smooth page reading and high-speed writing. An array in which a plurality of word lines WL and a plurality of bit lines BL orthogonal to each other are arranged, and a rewritable memory cell M is arranged at each intersection of the word lines WL and the bit lines BL is provided. In a semiconductor memory device divided into two sub-arrays 1 and r, an array-divided word line WL is sequentially selected one by one in a read operation, and two array-divided word lines WL are simultaneously selected in a write operation. It is characterized by doing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device capable of random read and page read, and more particularly to a semiconductor memory device in which the number of word lines selected in a read operation and a write operation is changed.

[0002]

2. Description of the Related Art Among electrically rewritable non-volatile semiconductor devices (EEPROMs), a NAND type EEPROM is known as one that can be highly integrated. This EE
In a PROM, one memory cell is a FETMOS in which a floating gate and a control gate are laminated on a substrate with an insulating film interposed.
A plurality of memory cells having a structure are connected in series in such a manner that their sources and drains are shared by adjacent ones.
It constitutes an AND cell.

The drain on one end side of the NAND cell is connected to the bit line via the select gate, and the source on the other end side is also connected to the common source line via the select gate. The control gates of the memory cells are continuously connected in the row direction to form word lines. Usually, a set of memory cells connected to the same word line is called a page, and a set of pages sandwiched by a set of drain side and source side select gates is 1NA.
It is called an ND block or simply one block. The memory cell array is usually formed in a p-type well formed in an n-type semiconductor substrate.

The operation of the NAND type EEPROM is as follows. Data writing is performed in order from the memory cell farther from the bit line. The boosted write potential Vpp (= about 20V) is applied to the control gate of the selected memory cell.
Is applied to the control gates and select gates of the other non-selected memory cells, and an intermediate potential (= about 10V) is applied to the bit lines. “Write” is applied. At this time, the potential of the bit line is transmitted to the selected memory cell. Data “0”
At this time, a high voltage is applied between the floating gate of the selected memory cell and the substrate, and electrons are tunnel-injected from the substrate to the floating gate to shift the threshold value in the positive direction. When the data is "1", the threshold value does not change.

Data erasing is performed on all the memory cells in the NAND cell almost at the same time. That is, all control gates and select gates are set to 0V, and the boosted erase potential VppE (about 20V) is applied to the p-type well and the n-type substrate. As a result, in all the memory cells, electrons in the floating gate are emitted to the well, and the threshold value moves in the negative direction.

For data reading, the control gate of the selected memory cell is set to 0 V, and the control gate and the selection gate of the other memory cells are set to the power supply potential Vcc to detect whether or not a current flows in the selected memory cell. Done by.

In the NAND type EEPROM, since the memory cells are connected in series, the cell current is small and it takes several μs to discharge the bit line. Therefore, random read takes about 10 μs. Data for one page is latched by the sense amplifier / data latch circuit. Page read only reads this latched data, so about 10
It can be read in 0 ns. For example, if the page length is 256 bytes, it takes 10 + 0.1 × 255 to 35 μs for one random read and 255 page reads to read one page of data. Therefore, when reading the data over a plurality of pages, the page switching unit requires a random read operation of 10 μs.

As a method of eliminating the random read operation at the time of page switching and reading data of a plurality of pages in an apparent page read cycle, for example, the memory cell array and the sense amplifier / latch circuit are divided into two, and the random read and the page read are simultaneously performed. There is a way to do it (Japanese Patent Application No. 4)
-157831). In this method, the page read operation is performed while the page read operation is performed on the one side of the memory cell array divided into two, and the random read operation is not performed at the switching point of the pages by performing the random read operation on the other side. It is possible to read data over multiple pages while maintaining the same.

Thus, by dividing the memory cell array into a plurality of sub-arrays and eliminating the dead time at the time of page switching, smooth serial reading can be realized. Therefore, as the density of semiconductor memory devices increases,
In order to realize high-speed and smooth reading, there is a trend toward promoting sub-arraying, dividing word lines, and reducing page size.

However, when the page size is reduced, there is a problem that writing takes time. For example, the write time per byte is compared between a case where the NAND type EEPROM having a page length of 256 bytes has a page length of 256 bytes and a case where the page length is divided into four 64 bytes.

First, if the page length is 256 bytes, the data load time is 50 ns × 256 = 12.8 μs, and if the write time for word line selection including the write confirmation read is 300 μs, the write time for 256 bytes per page is , 12.8 + 300 = 312.8 μs, and the write time per byte is 1.22 μs.
Becomes

However, if one page is divided into 4 bytes by 64 bytes, the data load time is 50 ns × 64 = 3.2 μs, and the write time for word line selection including the write confirmation read is 300 μs. Write time for word line selection including this write confirmation read is 300μ
s and the page size are the same regardless of the page size because writing and reading confirmation are performed collectively for one page. Therefore, the write time per page of 64 bytes is 3.2 + 300 = 303.2 μs, and the write time per byte is 4.74 μs.
Becomes

As described above, when the page size is divided, the writing time per byte becomes longer according to the number of divisions. For example, when the page size is divided into 4,
There was a problem that the writing time per byte was about four times.

[0014]

As described above, in the conventional semiconductor memory device, the memory cell array is arranged so that the serial read can be smoothly performed without interruption during the random read time at the time of page switching. It is divided into a plurality of sub-arrays, and while one sub-array is performing a page read operation, another sub-array is performing a random read operation. However, by dividing the memory cell array into a plurality of sub-arrays, there is a problem that the page size for writing is shortened at the same time and the writing time per byte increases.

The present invention has been made in view of the above problems, and an object of the present invention is to enable a page read and a random read, and in particular, a semiconductor memory device capable of smooth page read and high-speed writing. To provide.

[0016]

In order to solve the above problems, the present invention employs the following configurations. That is, according to the present invention, an array in which a plurality of word lines and a plurality of bit lines intersect each other are arranged, and a rewritable memory cell is arranged at each intersection of these word lines and bit lines is divided into a plurality of sub-arrays. In the semiconductor memory device described above, the number of selected word lines is different between the read operation and the write operation. More specifically, it is characterized in that a means for changing the number of word lines selected in one operation, that is, the page size, is provided for the read operation and the write operation.

The preferred embodiments of the present invention are as follows. (1) The number of word lines selected in one operation during the read operation or the write operation must be at most one in each sub-array. (2) More than the number of word lines selected by the read operation,
Increasing the number of word lines selected in write operation. In other words, the page size for write operation is larger than the page size for read operation. (3) In read operation, the array-divided word line is set to 1
Select the lines one by one, and in the write operation, simultaneously select a plurality of array-divided word lines. (4) The rewritable memory cell must be a non-volatile memory cell that can be written with a tunnel current. (5) A plurality of electrically rewritable nonvolatile memory cells are connected in series to form a NAND cell.

[0018]

According to the present invention, since word lines divided into arrays are sequentially selected during a read operation, random read time during page switching is apparently wasted when continuously reading data for a plurality of pages. As a result, smooth page reading can be realized. Further, since a plurality of array-divided word lines are selected at the same time during the write operation, the page size during the write operation becomes longer than the page size during the read operation, which allows high-speed writing.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram of a memory array of a semiconductor memory device according to an embodiment of the present invention. In the figure,
WL1l to WLml, WL1r to WLmr are word lines, R / D1
-R / Dm is a row decoder, M11l-Mmnl, M11r-
Mmnr is a memory cell, LA1l to LAnl, LA1r to LAnr
Is a sense amplifier and data latch circuit, and the memory cell array is divided into two subarrays l and r. Although not shown in the figure, bit lines BL are arranged in a direction orthogonal to the word lines WL, and a sense amplifier / data latch circuit LA is connected to each bit line BL.

The memory cell M has one transistor /
A one-capacitor DRAM or a static RAM can be used, a non-volatile ROM having a control gate and a floating gate, and a NAND cell in which these are connected in series can also be used. Here, a DRAM will be described.

FIG. 2 shows the read operation of the memory cell array of FIG. 1. When the word line WL1l is first selected, random read is performed on WL1l and the stored data of the memory cells M11l to M1nl are sensed. The data is transferred to the amplifier / data latch circuits LA1l to LAnl. Next, while the data transferred to the sense amplifier / data latch circuit is sequentially page-read, the next word line WL1r is selected, the random read is performed with respect to WL1r, and the storage data of the memory cells M11r to M1nr are stored. The data is transferred to the sense amplifier / data latch circuits LA1r to LAnr and LA1l to LAnr.
When LAnl page read ends, LA1r to LA are continuously
Nr page read is performed.

Then, the word line WL2l and then W
L2r is selected, and the page data of the sub-array 1 and the sub-array r are alternately read serially without interruption. Further, when switching between pages, a row address RA for selecting a word line may be input as shown in FIG. In this case, for example, first the word line WL (m-
1) 1 is selected, and then page data of sub-array 1 and sub-array r are alternately read serially, such as WL1r, WL3l, and WL (m-2) r, but word lines in the sub-array are selected. Is performed according to the input row address.

Further, as shown in FIG. 4, the row address RA for selecting the word line may not be input at the time of switching between pages, but may be collectively input at the beginning of reading.

FIG. 5 shows a write operation of the memory cell array of FIG. Pages of data are loaded. Next, for example, when the word lines WL1l and WL1r are selected at the same time, the memory cells M11l to M11l
The data loaded in the sense amplifier / data latch circuits LA1l-LAnl and LA1r-LAnr are simultaneously written in 1nl and M11r-M1nr.

In this case, regarding the sub-array 1 and the sub-array r, the selected word lines are WL1l and WL1r, so that the row address input at the time of writing is only "1" address, for example. Even if there is no row address for distinguishing from r, the row decoder R /
The pair of word lines WL1l and WL1r is selected by D1.

Further, as shown in FIG. 6, the sub-array l
For the sub-array r and the sub-array r, any one word line may be selected by inputting the row address RA.
In this case, the address "3l" is input to the sub-array l and the address "(m-2) r" is input to the sub-array r. LAnl and LA
When two pages of data are loaded into 1r to LAnr, the word lines WL3l and WL (m-2) r are simultaneously selected, and the memory cells M31l to M3nl and M (m-2) 1r to M (m- 2) nr is a sense amplifier and data latch circuit LA1l to LAnl and LA1r to L
The data loaded in Anr is written at the same time.

As described above, according to the present embodiment, the memory cell array is divided into two sub-arrays l and r, and the array-divided word lines WL are sequentially selected during continuous reading of data for a plurality of pages. Random read time when switching pages is apparently not wasted, which allows smooth page reading. In addition, since two array-divided word lines WL are selected at the same time during the write operation, the page size during the write operation becomes longer than the page size during the read operation, which allows high-speed writing. (Embodiment 2) FIG. 7 shows a case where the memory cell array is divided into four. In the figure, 1 is a sub array, 2 is a sense amplifier / data latch circuit, 3 is a row decoder, 4 is a column decoder, and 5 is a data input / output buffer. The memory cell array is divided into four subarrays A to D, and a sense amplifier / data latch circuit 2 (A to D) and a column decoder 4 are provided for each subarray 1 (A to D).
(A to D) are provided. The row decoder 3 is provided between the sub arrays A and B and between the sub arrays C and D.

Also in this embodiment, word lines are selected one by one at the time of reading. For example, as shown in FIG. 8, the row address R input by the word lines A, B, C, D is input.
It is sequentially selected according to A, and smooth serial reading is performed.

Further, as shown in FIG. 9, at the time of writing,
The write data is sense amplifier and data latch circuit A to
After being loaded into D, four word lines A to D are simultaneously selected according to the input row address RA,
The data loaded in the sense amplifier / data latch circuits A to D are written in the memory cells related to D to D.

Therefore, by the row decoder AB and the row decoder CD, the word line A and the word line B,
Also, the word line C and the word line D can be selected separately, and the word lines A to D can be simultaneously selected at the time of writing. (Embodiment 3) The embodiment has been described with respect to a general rewritable memory including DRAM and SRAM, but the present invention is not limited to this, and has a control gate and a floating gate (charge storage layer). It can also be applied to a non-volatile memory. However, considering access over a long page, it is desirable to be able to write with a tunnel current. A memory cell unit formed by connecting a plurality of memory cells is a NAND cell in which memory cells are connected in series.
Type, OR type in which a plurality of memory cells are connected in parallel, AND type in which a plurality of memory cells are connected in parallel, and select gates are provided at both ends thereof, a plurality of memory cells are connected in parallel, and a select gate is provided at one end thereof. It may be a DINOR type provided.

The read and write word line voltages in these flash EEPROMs depend on the respective devices. For example, in the case of a NAND type EEPROM, at the time of reading, the word line (control gate) of the selected memory cell is set to 0V, the word lines and select gates of the other memory cells are set to the power supply potential Vcc, and a current flows in the selected memory cell. It is carried out by detecting whether or not it flows.

At the time of writing, the boosted write potential Vpp (= about 20 V) is applied to the word line (control gate) of the selected memory cell, and is applied to the control gate and the select gate of other non-selected memory cells. Is an intermediate potential (= 10
(Approx. V) is applied, and 0 V is applied to the bit line according to the data.
(“0” writing) or intermediate potential (“1” writing) is applied. At this time, the potential of the bit line is transmitted to the selected memory cell.

When the data is "0", a high voltage is applied between the floating gate of the selected memory cell and the substrate, electrons are tunnel-injected from the substrate to the floating gate, and the threshold value moves in the positive direction. When the data is "1", the threshold value does not change.

Data erasing is performed on all the memory cells in the NAND cell almost at the same time. That is, all control gates and select gates are set to 0V, and the boosted erase potential VppE (about 20V) is applied to the p-type well and the n-type substrate. As a result, in all the memory cells, electrons in the floating gate are emitted to the well, and the threshold value moves in the negative direction.

Even in such an embodiment, the same effect as that of the first embodiment can be obtained, but the operation of simultaneously selecting and writing a plurality of word lines is a NAND type EEPRO.
This is particularly effective for a word line selection time such as M that has a long write time for word line selection.

The present invention is not limited to the above embodiment. The number of divisions of the memory cell array is 2 or 4.
The number is not limited to one, and can be changed appropriately according to the specifications. The number of word lines selected in one operation is
The number of word lines selected in the write operation is larger than the number of word lines selected in the read operation, which is a maximum of one in each sub-array. Generally, in the read operation, the array-divided word lines may be sequentially selected one by one, and in the write operation, the array-divided word lines may be simultaneously selected. In addition, various modifications can be made without departing from the scope of the present invention.

[0037]

As described in detail above, according to the present invention, since the array-divided word lines are sequentially selected during the read operation, the random read is performed by switching the page when the data for a plurality of pages is continuously read. The read time is apparently not wasted, and smooth page reading can be realized. In addition, since a plurality of array-divided word lines are selected at the same time during the write operation, the page size during the write operation becomes longer than the page size during the read operation, and high-speed write can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a semiconductor memory device according to a first embodiment.

FIG. 2 is a signal waveform diagram showing a read operation of the memory cell array of FIG.

FIG. 3 is a signal waveform diagram showing a read operation of the memory cell array of FIG.

FIG. 4 is a signal waveform diagram showing a read operation of the memory cell array of FIG.

5 is a signal waveform diagram showing a write operation of the memory cell array of FIG.

FIG. 6 is a signal waveform diagram showing a write operation of the memory cell array of FIG.

FIG. 7 is a block diagram showing a basic configuration of a semiconductor memory device according to a second embodiment.

FIG. 8 is a signal waveform diagram showing a read operation of the memory cell array of FIG.

9 is a signal waveform diagram showing a write operation of the memory cell array of FIG. 7.

[Explanation of symbols]

1, l, r ... Sub-array 2, LA1l to LAnl, LA1r to LAnr ... Sense amplifier / data latch circuit 3, R / D1 to R / Dm ... Row decoder 4 ... Column decoder 5 ... Data input / output buffer WL1l to WLml, WL1r -WLmr ... Word line M11l-Mmnl, M11r-Mmnr ... Memory cell

Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H01L 29/788 29/792 H01L 27/10 434 29/78 371 (72) Inventor Fujio Masuoka Kawasaki City, Kanagawa Prefecture Komukai-Toshiba-cho 1-ku, Toshiba Research & Development Center

Claims (6)

[Claims] 1. An array in which a plurality of word lines and a plurality of bit lines intersecting each other are arranged, and a rewritable memory cell is arranged at each intersection of the word lines and the bit lines is divided into a plurality of sub-arrays. In the semiconductor memory device described above, the number of selected word lines is different between the read operation and the write operation. 2. The semiconductor memory device according to claim 1, wherein in the read operation or the write operation, the number of word lines selected in one operation is one at a maximum in each sub-array. 3. The semiconductor memory device according to claim 1, wherein the number of word lines selected in the write operation is larger than the number of word lines selected in the read operation. 4. The read operation sequentially selects the array-divided word lines one by one, and the write operation simultaneously selects a plurality of array-divided word lines. The semiconductor memory device described. 5. The semiconductor memory device according to claim 1, wherein the rewritable memory cell is a non-volatile memory cell capable of being written by a tunnel current. 6. The semiconductor memory device according to claim 5, wherein a plurality of electrically rewritable nonvolatile memory cells are connected in series to form a NAND cell.