JPH0864631A - Bonding pad - Google Patents
Bonding padInfo
- Publication number
- JPH0864631A JPH0864631A JP6200987A JP20098794A JPH0864631A JP H0864631 A JPH0864631 A JP H0864631A JP 6200987 A JP6200987 A JP 6200987A JP 20098794 A JP20098794 A JP 20098794A JP H0864631 A JPH0864631 A JP H0864631A
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- wiring
- bonding
- wiring portion
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 230000000694 effects Effects 0.000 abstract description 13
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 229910001111 Fine metal Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05551—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05557—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体チップに形成
された回路とパッケージのリードとを接続するために半
導体チップに設けられるボンディングパッドに関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bonding pad provided on a semiconductor chip for connecting a circuit formed on the semiconductor chip and a lead of a package.
【０００２】[0002]
【従来の技術】半導体装置の製造工程の１つとして、回
路が作り込まれた半導体チップの電極であるボンディン
グパッドと半導体チップが実装されるパッケージのリー
ド電極との間を、金やアルミニウム等の細線を使用して
接続するワイヤボンディング工程がある。2. Description of the Related Art As one of the steps of manufacturing a semiconductor device, a metal such as gold or aluminum is provided between a bonding pad which is an electrode of a semiconductor chip in which a circuit is formed and a lead electrode of a package in which the semiconductor chip is mounted. There is a wire bonding process for connecting using fine wires.
【０００３】図９及び図１０は、例えば特開平3-285338
号に示された従来の半導体装置における半導体チップ上
のボンディングパッドである。図９は、ボンディングパ
ッドとその周辺部を示す図であり、３ａ，３ｂはボンデ
ィングパッド１２ａ，１２ｂとリード電極６ａ，６ｂと
を接続する金属細線、４ａ，４ｂはワイヤの先端に形成
されたボールボンド、５ａ，５ｂはパッケージ８の外部
の電極となるリード、６ａ，６ｂはリード５ａ，５ｂと
接続されたパッケージ８のリード電極、７は回路が形成
された半導体チップ（半導体デバイス）である。ここで
いう半導体チップとは本番デバイスあるいはＴＥＧ（te
st element group：電気特性からプロセスデバイスを評
価するテストパターン群）のことである。ＴＥＧは実際
のＬＳＩと同一もしくは部分的な工程で作られる。ＴＥ
Ｇによる評価の特徴はデバイスに即した形での評価が可
能であることと、物理的な分析手段に比べると感度が良
いことである。9 and 10 show, for example, Japanese Patent Laid-Open No. 3-285338.
7 is a bonding pad on a semiconductor chip in the conventional semiconductor device shown in FIG. FIG. 9 is a view showing a bonding pad and its peripheral portion. 3a and 3b are thin metal wires connecting the bonding pads 12a and 12b and the lead electrodes 6a and 6b, and 4a and 4b are balls formed at the tips of the wires. Bonds, 5a and 5b are leads serving as electrodes outside the package 8, 6a and 6b are lead electrodes of the package 8 connected to the leads 5a and 5b, and 7 is a semiconductor chip (semiconductor device) on which a circuit is formed. The semiconductor chip mentioned here is a production device or TEG (te
st element group: A group of test patterns that evaluate process devices from electrical characteristics. The TEG is manufactured in the same or partial process as the actual LSI. TE
The characteristics of the evaluation by G are that the evaluation can be performed in a form suitable for the device and that the sensitivity is higher than that of the physical analysis means.
【０００４】８は半導体チップ７、リード５ａ，５ｂ等
を固定するパッケージ、１２ａ，１２ｂは半導体チップ
７に形成されたボンディングパッド、１３ａ，１３ｂは
ボンディングパッド１２ａ，１２ｂを回路の所定の部分
に接続する配線である。また、図１０は、ボンディング
パッド１２及び配線１３の拡大図である。Reference numeral 8 is a package for fixing the semiconductor chip 7, leads 5a, 5b and the like, 12a and 12b are bonding pads formed on the semiconductor chip 7, and 13a and 13b are bonding pads 12a and 12b connected to predetermined portions of the circuit. Wiring. Further, FIG. 10 is an enlarged view of the bonding pad 12 and the wiring 13.
【０００５】なお、図９及び図１０のボンディングパッ
ド１２ａ、１２ｂは、その面積を減らして寄生容量によ
る悪影響を低減するため、格子状に構成されている。The bonding pads 12a and 12b shown in FIGS. 9 and 10 are formed in a lattice shape in order to reduce the area thereof and reduce the adverse effect of parasitic capacitance.
【０００６】[0006]
【発明が解決しようとする課題】ところで、半導体デバ
イスの生成プロセスの１つであるプラズマ工程におい
て、プラズマ中で発生した電荷がボンディングパッド１
２で集められ、配線１３を介して半導体デバイスのゲー
ト酸化膜等に蓄積されることがある。この電荷によりゲ
ート酸化膜等にストレスが加えられることになるので、
半導体デバイスの素子特性が劣化することがある（これ
を「アンテナ効果」という。参考文献：Ｈ.Ｓhin，Ｃ.
Ｋing，Ｃ.Ｈu Ｐｒｏｃ．ＩＥＥＥ ＩＲＰＳ，pp37-
41,1992）。By the way, in the plasma step which is one of the production processes of the semiconductor device, the electric charges generated in the plasma are generated in the bonding pad 1.
2 and may be accumulated in the gate oxide film or the like of the semiconductor device via the wiring 13. Since this charge will add stress to the gate oxide film etc.,
The element characteristics of a semiconductor device may be deteriorated (this is called "antenna effect". Reference: H. Shin, C.
King, C. Hu Proc. IEEE IRPS, pp37-
41, 1992).
【０００７】このアンテナ効果によるプラズマダメージ
は、ボンディングパッドの面積及びプラズマにさらされ
る時間に比例して大きくなる。したがって、回路のゲー
ト酸化膜等に接続されるボンディングパッド１２の面積
が小さければ小さいほど、受けるダメージは少なくな
る。一方、ボンディングパッド１２の面積が小さすぎる
とワイヤボンディング装置の位置決め精度を高めなけれ
ばならず、装置が高価になるとともにボンディングに時
間がかかるようになり、コストアップにつながる。ま
た、ボンディングパッド１２を、図１０に示すように格
子状にすればこの点は改善されるが、その面積の低減に
は限界があり、アンテナ効果によるプラズマダメージを
十分に低減することは困難である。Plasma damage due to the antenna effect increases in proportion to the area of the bonding pad and the time of exposure to plasma. Therefore, the smaller the area of the bonding pad 12 connected to the gate oxide film or the like of the circuit is, the less damage is received. On the other hand, if the area of the bonding pad 12 is too small, the positioning accuracy of the wire bonding apparatus must be increased, which makes the apparatus expensive and requires a long time for bonding, which leads to an increase in cost. Although this point can be improved by forming the bonding pad 12 in a lattice shape as shown in FIG. 10, there is a limit to the reduction of the area, and it is difficult to sufficiently reduce the plasma damage due to the antenna effect. is there.
【０００８】この発明は、上述のような課題を解決する
ためになされたもので、ボンディングパッドの面積を小
さくしてアンテナ効果によるプラズマダメージを低減す
るとともに、ボンディング工程のコストアップを抑える
ことができるボンディングパッドを提供するものであ
る。The present invention has been made in order to solve the above-mentioned problems, and it is possible to reduce the area of the bonding pad to reduce the plasma damage due to the antenna effect and to suppress the cost increase of the bonding process. A bonding pad is provided.
【０００９】[0009]
【課題を解決するための手段】請求項１に係るボンディ
ングパッドは、半導体チップに形成された回路に接続さ
れた配線部分と、上記配線部分に隣接して形成され、上
記配線部分より大きな面積のワイヤ接続部分とからな
り、ボンディングの際に導電部材により上記配線部分と
上記ワイヤ接続部分とが接続されるように構成されたも
のである。A bonding pad according to claim 1 is formed adjacent to a wiring portion connected to a circuit formed on a semiconductor chip, and has a larger area than the wiring portion. And a wire connecting portion, which is configured to connect the wiring portion and the wire connecting portion by a conductive member during bonding.
【００１０】請求項２に係るボンディングパッドは、上
記配線部分と上記ワイヤ接続部分とが同じ層に形成さ
れ、上記配線部分と上記ワイヤ接続部分との間に隙間を
設けることにより分離されているものである。In the bonding pad according to a second aspect of the present invention, the wiring portion and the wire connecting portion are formed in the same layer, and are separated by providing a gap between the wiring portion and the wire connecting portion. Is.
【００１１】請求項３に係るボンディングパッドは、上
記配線部分と上記ワイヤ接続部分とが接続電極であるバ
ンプにより接続されるものである。According to a third aspect of the bonding pad, the wiring portion and the wire connecting portion are connected by a bump which is a connecting electrode.
【００１２】請求項４に係るボンディングパッドは、上
記ワイヤ接続部分に凹部を備え、上記配線部分が上記凹
部に設けられるとともに、上記凹部において上記配線部
分が他の部分より大きく形成されたものである。According to a fourth aspect of the present invention, there is provided a bonding pad in which the wire connecting portion has a recess, the wiring portion is provided in the recess, and the wiring portion is formed larger than the other portions in the recess. .
【００１３】[0013]
【作用】請求項１の発明においては、プラズマ工程にお
いて配線部分とワイヤ接続部分とが分離されており、配
線部分から注入される電荷量は少なく、回路に対するプ
ラズマダメージが低減される。一方、ボンディングの際
には上記配線部分と上記ワイヤ接続部分とが導電部材に
より接続されてパッケージのリードと回路とが接続され
る。According to the first aspect of the present invention, the wiring portion and the wire connection portion are separated in the plasma process, the amount of charges injected from the wiring portion is small, and plasma damage to the circuit is reduced. On the other hand, at the time of bonding, the wiring portion and the wire connecting portion are connected by a conductive member to connect the package lead and the circuit.
【００１４】請求項２の発明においては、上記配線部分
と上記ワイヤ接続部分とが同じ層に形成され、上記配線
部分と上記ワイヤ接続部分との間に隙間を設けることに
より分離されている。In the invention of claim 2, the wiring portion and the wire connecting portion are formed in the same layer, and are separated by providing a gap between the wiring portion and the wire connecting portion.
【００１５】請求項３の発明においては、上記配線部分
と上記ワイヤ接続部分とが接続電極であるバンプにより
接続される。According to the third aspect of the invention, the wiring portion and the wire connecting portion are connected by the bump which is the connecting electrode.
【００１６】請求項４の発明においては、上記ワイヤ接
続部分に凹部を備え、上記配線部分が上記凹部に設けら
れるとともに、上記凹部において上記配線部分が他の部
分より大きく形成される。In the invention of claim 4, the wire connecting portion is provided with a concave portion, the wiring portion is provided in the concave portion, and the wiring portion is formed larger than other portions in the concave portion.
【００１７】[0017]
実施例１．以下、この発明の一実施例を図について説明
する。図１は、ボンディングパッドとその周辺部を示す
図であり、１ａ，１ｂは、半導体チップ７に形成された
ワイヤの接続部であるボンディングパッド２ａ，２ｂを
回路の所定の部分に接続するアルミ（Ａｌ）等による配
線であり、半導体チップの回路を形成するときに同時に
形成される。なお、従来は同図の１ａ，１ｂの一部と２
ａ，２ｂとを併せてボンディングパッドと言っていた
が、以下において説明の便宜上、ワイヤが接続される部
分であり、配線１ａ，１ｂを含まない部分をボンディン
グパッド２ａ，２ｂと記すことにする。３ａ，３ｂはボ
ンディングパッド２ａ，２ｂとリード電極６ａ，６ｂと
を接続する金属細線、４ａ，４ｂは金属細線の先端に形
成されたボールボンド、５ａ，５ｂはパッケージ８の外
部の電極となるリード、６ａ，６ｂはリード５ａ，５ｂ
と接続されたリード電極、７は回路が形成された半導体
チップ（半導体デバイス）である。ここでいう半導体チ
ップとは本番デバイスあるいはＴＥＧのことである。８
は半導体チップ７、リード５ａ，５ｂ等を固定するパッ
ケージである。Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a view showing a bonding pad and its peripheral portion. Reference numerals 1a and 1b denote aluminum pads (1a and 1b) for connecting the bonding pads 2a and 2b, which are connection portions of wires formed on the semiconductor chip 7, to predetermined portions of the circuit. The wiring is made of Al) or the like and is formed at the same time when the circuit of the semiconductor chip is formed. Incidentally, in the past, a part of 1a and 1b in FIG.
Although a and 2b have been collectively referred to as bonding pads, for convenience of description, the portions to which wires are connected and the wirings 1a and 1b are not included will be referred to as bonding pads 2a and 2b. 3a and 3b are fine metal wires connecting the bonding pads 2a and 2b and the lead electrodes 6a and 6b, 4a and 4b are ball bonds formed at the tips of the fine metal wires, and 5a and 5b are leads serving as external electrodes of the package 8. , 6a, 6b are leads 5a, 5b
The lead electrode 7 connected to is a semiconductor chip (semiconductor device) on which a circuit is formed. The semiconductor chip mentioned here is a production device or TEG. 8
Is a package for fixing the semiconductor chip 7, the leads 5a, 5b, and the like.
【００１８】また、図２は、配線１ａ及びボンディング
パッド２ａの拡大図であり、図３は、図２のＡ−Ａ’矢
視断面図である。配線１ａ及びボンディングパッド２ａ
は同じ層に形成されるとともに、シリコン（Ｓｉ）基板
１０の上に形成されたシリコン酸化膜（ＳｉＯ2）９に
重ねて形成されている。FIG. 2 is an enlarged view of the wiring 1a and the bonding pad 2a, and FIG. 3 is a sectional view taken along the line AA 'of FIG. Wiring 1a and bonding pad 2a
Are formed in the same layer and are formed so as to overlap the silicon oxide film (SiO 2 ) 9 formed on the silicon (Si) substrate 10.
【００１９】これらの図からわかるように、直線状の配
線１ａの面積はボンディングパッド２ａの面積に比べ非
常に小さい。そして、ボンディングパッド２ａは「コ」
の字型をしていて、配線１ａはボンディングパッド２ａ
の凹部にはまり込むように形成されている。しかし、配
線１ａとボンディングパッド２ａとは隙間２１により隔
てられているので、これらは電気的に接続されていな
い。ここで、配線１ａと隙間２１との合計の幅は、ボー
ルボンド４ａの直径よりも小さくなるように定められ
る。As can be seen from these figures, the area of the linear wiring 1a is much smaller than the area of the bonding pad 2a. Then, the bonding pad 2a is "ko".
The wiring 1a is shaped like a square and the bonding pad 2a
Is formed so as to fit in the concave portion of the. However, since the wiring 1a and the bonding pad 2a are separated by the gap 21, they are not electrically connected. Here, the total width of the wiring 1a and the gap 21 is set to be smaller than the diameter of the ball bond 4a.
【００２０】配線１ａとボンディングパッド２ａとが以
上のように形成されていることから、半導体デバイスの
生成プロセスのプラズマ工程において、アンテナ効果に
よるストレスを殆ど受けない。なぜなら、ボンディング
パッド２ａで集められたプラズマによる電荷は、隙間２
１によりボンディングパッド２ａと配線１ａとが絶縁さ
れているため回路の半導体デバイスに流れ込むことがな
く、また、回路に接続されている配線１ａの面積は非常
に小さいからプラズマによる電荷は殆ど蓄積されないか
らである。したがってプラズマダメージによる半導体素
子の特性の劣化は最小限に抑えることができる。Since the wiring 1a and the bonding pad 2a are formed as described above, the stress due to the antenna effect is scarcely received in the plasma step of the semiconductor device production process. Because the electric charge due to the plasma collected at the bonding pad 2a is
Since the bonding pad 2a and the wiring 1a are insulated by 1, they do not flow into the semiconductor device of the circuit, and since the area of the wiring 1a connected to the circuit is very small, almost no electric charge is accumulated by the plasma. Is. Therefore, the deterioration of the characteristics of the semiconductor element due to plasma damage can be suppressed to a minimum.
【００２１】一方、ボンディングワイヤ３ａが接続され
ると、図４及び図５に示すように、そのボールボンド４
ａにより隙間２１が埋められて配線１ａ及びボンディン
グパッド２ａとが接続される。したがって、リード５
ａ，５ｂは、リード電極６ａ，６ｂ、ボンディングワイ
ヤ３ａ，３ｂ，ボールボンド４ａ，４ｂ、ボンディング
パッド２ａ，２ｂ，配線１ａ，１ｂを介して、半導体チ
ップ７上の回路の所定の部分に電気的に接続される。配
線１ａと隙間２１の合計の幅はボールボンド４ａの直径
よりも小さいから、ボールボンド４ａの位置が多少ずれ
ても配線１ａとボンディングパッド２ａとを接続するこ
とができる。したがって、ボンディングに際しては従来
と同じ程度の位置決め精度でよく、歩留まりが高いボン
ディングを行うことができる。On the other hand, when the bonding wire 3a is connected, as shown in FIGS. 4 and 5, the ball bond 4 is formed.
The gap 21 is filled with a to connect the wiring 1a and the bonding pad 2a. Therefore, lead 5
a and 5b are electrically connected to predetermined portions of the circuit on the semiconductor chip 7 through the lead electrodes 6a and 6b, the bonding wires 3a and 3b, the ball bonds 4a and 4b, the bonding pads 2a and 2b, and the wirings 1a and 1b. Connected to. Since the total width of the wiring 1a and the gap 21 is smaller than the diameter of the ball bond 4a, the wiring 1a and the bonding pad 2a can be connected even if the position of the ball bond 4a is slightly displaced. Therefore, the bonding can be performed with the same positioning accuracy as the conventional one, and the bonding with high yield can be performed.
【００２２】なお、ワイヤボンディング時には、図４に
示すように配線１ａとボンディングパッド２ａとを覆う
ようにボンディングすることによって、ボンディングの
接着力を下げることなく配線へのオーミック（低接触抵
抗：接触抵抗が低く無視できるレベルである状態）な圧
着が可能になる。At the time of wire bonding, as shown in FIG. 4, by bonding so as to cover the wiring 1a and the bonding pad 2a, ohmic (low contact resistance: contact resistance) to the wiring can be achieved without lowering the bonding strength of the bonding. It is possible to perform crimping with a low value and a level that can be ignored.
【００２３】以上のように、この実施例１によれば、配
線と、隙間によりこれと絶縁されたボンディングパッド
とからボンディングパッドを構成し、ボールボンドによ
り配線とボンディングパッドとを接続するようにしたの
で、アンテナ効果によるプラズマダメージを低減するこ
とができる。また、ボンディングの位置決めに高い精度
を必要とすることがないので、ボンディング工程の歩留
まりが向上する。As described above, according to the first embodiment, the bonding pad is composed of the wiring and the bonding pad insulated from the wiring by the gap, and the wiring and the bonding pad are connected by ball bonding. Therefore, plasma damage due to the antenna effect can be reduced. In addition, since the positioning of the bonding does not require high accuracy, the yield of the bonding process is improved.
【００２４】また、配線とボンディングパッドとの間に
隙間を設けることにより両者を分離しているので、分離
膜により分離する場合と比べ、ワイヤボンディング時に
クラックを発生させたり、熱膨張率の違いにより剥離を
生じさせることがなく、信頼性が高くなる。Further, since a gap is provided between the wiring and the bonding pad to separate the two from each other, cracks are generated during wire bonding or due to a difference in thermal expansion coefficient, as compared with the case where they are separated by a separation film. The peeling does not occur, and the reliability is high.
【００２５】また、配線とボンディングパッドとを同じ
層に形成しているので両者を接続するためのスルーホー
ルを形成する必要がなく、異なる層に形成した場合と比
べてスルーホールをエッチングする工程が不要であり、
工程が簡単になるとともにこのエッチングにおけるプラ
ズマダメージを低減することができる。Further, since the wiring and the bonding pad are formed in the same layer, it is not necessary to form a through hole for connecting the two, and the step of etching the through hole is different from the case of forming in a different layer. Unnecessary,
The process can be simplified and the plasma damage in this etching can be reduced.
【００２６】実施例２．上記実施例１は、ボールボンド
４の圧着によるボンディングの場合を示しているが、ボ
ンディングパッドに電極（バンプ）を形成した後に、導
体のリードと半導体チップの電極の対応する部分とを重
ね合わせて接合するＴＡＢ（tape automated bonding）
により圧着するようにしてもよい。Example 2. Although the above-mentioned Example 1 shows the case of bonding by pressure bonding of the ball bond 4, after forming electrodes (bumps) on the bonding pads, the leads of the conductor and the corresponding portions of the electrodes of the semiconductor chip are superposed. TAB (tape automated bonding)
You may make it crimp by.
【００２７】すなわち、図６に示すように、配線１ａ及
びボンディングパッド２ａ上に、接続電極であるバンプ
６を形成し、配線１ａとボンディングパッド２ａとを接
続する。その後にＴＡＢにより圧着する。That is, as shown in FIG. 6, bumps 6 serving as connection electrodes are formed on the wiring 1a and the bonding pad 2a to connect the wiring 1a and the bonding pad 2a. After that, pressure bonding is performed by TAB.
【００２８】この実施例２によれば、実施例１の場合と
同様に、従来と同じ程度の位置決め精度で歩留まりが高
いボンディングを行いつつ、アンテナ効果によるプラズ
マダメージを低減できるとともに、バンプにおいて接続
される配線の部分の面積が、実施例１の場合に比べ増え
るのでボンディング時の接着力が向上するという効果を
奏する。According to the second embodiment, similarly to the first embodiment, it is possible to reduce the plasma damage due to the antenna effect and perform the bonding at the bump while performing the high-yield bonding with the same positioning accuracy as the conventional one. Since the area of the wiring portion is increased as compared with the case of the first embodiment, there is an effect that the adhesive force at the time of bonding is improved.
【００２９】実施例３．なお、実施例１では、配線１ａ
とボンディングパッド２ａとの間に、直線で構成された
「コ」の字型の隙間２１を設けて配線１ａとボンディン
グパッド２ａとを絶縁したが、隙間２１の形状はこれに
限るものではない。Example 3. In the first embodiment, the wiring 1a
The bonding pad 2a and the bonding pad 2a are provided with a linear U-shaped gap 21 to insulate the wiring 1a and the bonding pad 2a, but the shape of the gap 21 is not limited to this.
【００３０】例えば、図７に示すように、配線１ｃの端
部（ボンディングパッド２ｃの凹部に嵌め込まれている
部分）を円形に構成し、これに沿ってその周囲に隙間２
２を設けるようにしてもよい。また、図８に示すように
配線１ｄの端部を十字状に構成し、これに沿ってその周
囲に隙間２３を設けるようにしてもよい。For example, as shown in FIG. 7, the end portion of the wiring 1c (the portion fitted in the concave portion of the bonding pad 2c) is formed in a circular shape, and along this, a gap 2 is formed around the end portion.
Two may be provided. Alternatively, as shown in FIG. 8, the end portion of the wiring 1d may be formed in a cross shape, and the gap 23 may be provided along the periphery thereof.
【００３１】この実施例３によれば、実施例１の場合と
同様に、従来と同じ程度の位置決め精度で歩留まりが高
いボンディングを行いつつ、アンテナ効果によるプラズ
マダメージを低減できるとともに、ボールボンドあるい
はバンプにおいて接続される配線の部分の面積が実施例
１の場合に比べ増えるのでボンディング時の接着力が高
まり、信頼性が向上するという効果を奏する。According to the third embodiment, similarly to the first embodiment, it is possible to reduce the plasma damage due to the antenna effect and perform the ball bond or the bump while performing the high yield bonding with the same positioning accuracy as the conventional one. Since the area of the wiring portion connected in 1 is increased as compared with the case of the first embodiment, the adhesive force at the time of bonding is increased, and the reliability is improved.
【００３２】[0032]
【発明の効果】以上のように、請求項１の発明によれ
ば、上記半導体チップに形成された回路に接続された配
線部分と、上記配線部分に隣接して形成され、上記配線
部分より大きな面積のワイヤ接続部分とからなり、ボン
ディングの際に導電部材により上記配線部分と上記ワイ
ヤ接続部分とが接続されるように構成したので、プラズ
マ工程においてボンディングパッドの面積を小さくして
アンテナ効果によるプラズマダメージを低減するととも
に、位置決め精度を高くすることなくボンディングでき
てコストアップを抑えることができる。As described above, according to the first aspect of the invention, the wiring portion connected to the circuit formed on the semiconductor chip and the wiring portion formed adjacent to the wiring portion are larger than the wiring portion. Since the wiring portion and the wire connecting portion are configured to be connected by a conductive member at the time of bonding, the area of the bonding pad is reduced in the plasma process and the plasma due to the antenna effect is formed. The damage can be reduced, and the bonding can be performed without increasing the positioning accuracy, and the cost increase can be suppressed.
【００３３】また、請求項２の発明によれば、上記配線
部分と上記ワイヤ接続部分とが同じ層に形成され、上記
配線部分と上記ワイヤ接続部分との間に隙間を設けるこ
とにより分離し、分離膜により分離していないので、工
程が簡単になるとともに、クラックが発生せず、信頼性
が高くなる。According to the invention of claim 2, the wiring portion and the wire connecting portion are formed in the same layer, and are separated by providing a gap between the wiring portion and the wire connecting portion, Since it is not separated by the separation film, the process is simplified, cracks do not occur, and reliability is improved.
【００３４】また、請求項３の発明によれば、上記配線
部分と上記ワイヤ接続部分とが接続電極であるバンプに
より接続されるので、広い面積で接続されてボンディン
グ時の接着力が増す。Further, according to the invention of claim 3, since the wiring portion and the wire connecting portion are connected by the bumps which are the connecting electrodes, the connecting portions are connected in a wide area and the adhesive force at the time of bonding is increased.
【００３５】また、請求項４の発明によれば、上記ワイ
ヤ接続部分に凹部を備え、上記配線部分が上記凹部に設
けられるとともに、上記凹部において上記配線部分が他
の部分より大きく形成されるので、配線の接続部分の面
積が増えてボンディング時の接着力が増すとともに接触
抵抗が小さくなり、信頼性及び性能が向上する。Further, according to the invention of claim 4, the wire connecting portion is provided with a concave portion, the wiring portion is provided in the concave portion, and the wiring portion is formed larger than other portions in the concave portion. The area of the connecting portion of the wiring increases, the adhesive force at the time of bonding increases, the contact resistance decreases, and the reliability and performance improve.
【図１】 この発明の実施例１のボンディングパッドと
その周辺部分を示す平面図である。FIG. 1 is a plan view showing a bonding pad and its peripheral portion according to a first embodiment of the present invention.
【図２】 この発明の実施例１の配線とボンディングパ
ッドの平面図である。FIG. 2 is a plan view of wirings and bonding pads according to the first embodiment of the present invention.
【図３】 この発明の実施例１の配線とボンディングパ
ッドの断面図である。FIG. 3 is a cross-sectional view of the wiring and the bonding pad according to the first embodiment of the present invention.
【図４】 この発明の実施例１の配線及びボンディング
パッドと金属細線及びボールボンドとの接続を示す平面
図である。FIG. 4 is a plan view showing the connection between the wiring and the bonding pad, the metal fine wire and the ball bond according to the first embodiment of the present invention.
【図５】 この発明の実施例１の配線及びボンディング
パッドと金属細線及びボールボンドとの接続を示す断面
図である。FIG. 5 is a cross-sectional view showing the connection between the wiring and the bonding pad and the metal fine wire and the ball bond according to the first embodiment of the present invention.
【図６】 この発明の実施例２の配線及びボンディング
パッドとバンプとの接続を示す平面図である。FIG. 6 is a plan view showing a wiring and a connection between a bonding pad and a bump according to a second embodiment of the present invention.
【図７】 この発明の実施例３の配線とボンディングパ
ッドの平面図である。FIG. 7 is a plan view of wirings and bonding pads according to a third embodiment of the present invention.
【図８】 この発明の実施例３の他の配線とボンディン
グパッドの平面図である。FIG. 8 is a plan view of another wiring and bonding pad according to the third embodiment of the present invention.
【図９】 従来のボンディングパッドとその周辺部分を
示す平面図である。FIG. 9 is a plan view showing a conventional bonding pad and its peripheral portion.
【図１０】 従来の配線とボンディングパッドの平面図
である。FIG. 10 is a plan view of a conventional wiring and a bonding pad.
１ 配線、２ ボンディングパッド、３ 金属細線、４
ボールボンド、５リード、６ リード電極、７ 半導
体チップ、８ パッケージ、１１ バンプ、２１ 隙
間、２２ 隙間、２３ 隙間。1 wiring, 2 bonding pad, 3 thin metal wire, 4
Ball bond, 5 leads, 6 lead electrodes, 7 semiconductor chips, 8 packages, 11 bumps, 21 gaps, 22 gaps, 23 gaps.
Claims (4)
チップが実装されるパッケージのリードとの間をワイヤ
により接続するためのボンディングパッドにおいて、 上記半導体チップに形成された回路に接続された配線部
分と、上記配線部分に隣接して形成され、上記配線部分
より大きな面積のワイヤ接続部分とからなり、ボンディ
ングの際に導電部材により上記配線部分と上記ワイヤ接
続部分とが接続されるように構成されたことを特徴とす
るボンディングパッド。1. A bonding pad provided on a semiconductor chip for connecting with a lead of a package on which the semiconductor chip is mounted by a wire, which is a wiring portion connected to a circuit formed on the semiconductor chip. And a wire connecting portion formed adjacent to the wiring portion and having a larger area than the wiring portion, and configured to connect the wiring portion and the wire connecting portion by a conductive member during bonding. Bonding pad characterized by that.
同じ層に形成され、上記配線部分と上記ワイヤ接続部分
との間に隙間を設けることにより分離されていることを
特徴とする請求項１記載のボンディングパッド。2. The wiring portion and the wire connecting portion are formed in the same layer, and are separated by providing a gap between the wiring portion and the wire connecting portion. Bonding pad as described.
接続電極であるバンプにより接続されることを特徴とす
る請求項２記載のボンディングパッド。3. The bonding pad according to claim 2, wherein the wiring portion and the wire connection portion are connected by a bump which is a connection electrode.
配線部分が上記凹部に設けられるとともに、上記凹部に
おいて上記配線部分が他の部分より大きく形成されたこ
とを特徴とする請求項２記載のボンディングパッド。4. The wire connecting portion is provided with a concave portion, the wiring portion is provided in the concave portion, and the wiring portion is formed to be larger than other portions in the concave portion. Bonding pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6200987A JPH0864631A (en) | 1994-08-25 | 1994-08-25 | Bonding pad |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6200987A JPH0864631A (en) | 1994-08-25 | 1994-08-25 | Bonding pad |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0864631A true JPH0864631A (en) | 1996-03-08 |
Family
ID=16433628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6200987A Pending JPH0864631A (en) | 1994-08-25 | 1994-08-25 | Bonding pad |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0864631A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002334935A (en) * | 2001-05-08 | 2002-11-22 | Mitsubishi Electric Corp | High-frequency circuit chip, high-frequency circuit device having the chip, and method of manufacturing the same |
| JP2006202993A (en) * | 2005-01-20 | 2006-08-03 | Hamamatsu Photonics Kk | Solid-state imaging device, manufacturing method thereof, and charge accumulation preventing structure |
-
1994
- 1994-08-25 JP JP6200987A patent/JPH0864631A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002334935A (en) * | 2001-05-08 | 2002-11-22 | Mitsubishi Electric Corp | High-frequency circuit chip, high-frequency circuit device having the chip, and method of manufacturing the same |
| JP2006202993A (en) * | 2005-01-20 | 2006-08-03 | Hamamatsu Photonics Kk | Solid-state imaging device, manufacturing method thereof, and charge accumulation preventing structure |
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