JPH0863989A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE: To prevent prolonging a discharge time of a bit line due to leak and to perform pre-charge at high speed by applying preventing voltage for bit line discharge to a bit line preceding pre-charge of an EEPROM in which a NAND CELL is arranged in a matrix state. CONSTITUTION: Preventing voltage for bit line discharge of power supply voltage VCC and the like is applied to, for example, bit line BLOA and the like through a pre-charge circuit at the time of turning on a power supply and the like. Thereby, even when D type, E type selecting MOS transistors D, E, E' of which sources are connected to a NAND cell are turned on, current leak of the bit line BLDA and the like through a floating gate of a non-selection NAND cell block is prevented. Prolonging a discharge time of a bit line also is prevented with this preventing voltage, pre-charge of a bit line can be performed at high speed. Further, leak of a bit line does not occur also at the time of verify-read, and over erasing can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art In recent years, a NAND cell type EEPROM has been proposed as one of electrically rewritable non-volatile semiconductor devices (EEPROMs). This EEPROM
Is, for example, a plurality of memory cells having an n-channel FETMOS structure in which a floating gate and a control gate as a charge storage layer are stacked, connected in series such that their sources and drains are shared by adjacent ones. It is connected to the bit line as a unit.

29 (a) and 29 (b) are a plan view and an equivalent circuit diagram of one NAND cell portion of the memory cell array. 30 (a) and 30 (b) are respectively A- of FIG. 29 (a).
It is an A'and BB 'sectional drawing.

A memory cell array composed of a plurality of NAND cells is formed on a p-type silicon substrate (or p-type well) 11 surrounded by an element isolation oxide film 12. One N
Explaining by focusing on the AND cell, in this embodiment, 8
Memory cells M1 to M8 are connected in series to form one NA
It constitutes an ND cell. Each memory cell has a floating gate 14 on a substrate 11 via a tunnel insulating film 13.
(14 ₁ , 14 _{2 to} 14 ₈ ) are formed, and the control gate 16 (16 ₁ , 16 ₂ ) is formed thereon with the gate insulating film 15 interposed therebetween.
˜16 ₈ ) are formed and configured. The n-type diffusion layers 19 which are the source and drain of these memory cells,
Adjacent ones are connected in a shared manner, whereby a plurality of memory cells are connected in series.

First selection gates 14 ₉ and 16 ₉ and second selection gates 14 ₁₀ and 16 ₁₀ formed simultaneously with the floating gate and control gate of the memory cell are provided on the drain side and the source side of the NAND cell, respectively. It is provided. The substrate on which the elements are formed is covered with the CVD oxide film 17, and the bit line 18 is disposed on the CVD oxide film 17. The control gates 14 of the NAND cells are commonly arranged as control gates CG1 and CG2 to CG8. These control gate lines become word lines. The select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ are also arranged continuously in the row direction as select gates SG1, SG2.

FIG. 31 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix. The source line is connected to a reference potential wiring such as Al or poly-Si via a contact at one location for every 64 bit lines, for example. This reference potential wiring is connected to the peripheral circuit. The control gate of the memory cell and the first and second selection gates are continuously arranged in the row direction. Usually, a set of memory cells connected to a control gate is called one page, and a set of pages sandwiched by a set of drain-side (first select gate) and source-side (second select gate) select gates is one NAND. It is called a block or simply one block.

The operation of the NAND cell type EEPROM is as follows. Data writing is performed in order from the memory cell farther from the bit line. A boosted write voltage Vpp (= about 20V) is applied to the control gate of the selected memory cell, and an intermediate potential (about 10V) is applied to the control gates of the other non-selected memory cells and the first select gate. Then, 0 V (“0” write) or an intermediate potential (“1” write) is applied to the bit line according to the data. At this time, the potential of the bit line is transmitted to the selected memory cell.
When the data is "0", a high voltage is applied between the floating gate of the selected memory cell and the substrate, and electrons are tunnel-injected from the substrate to the floating gate to shift the threshold voltage in the positive direction. When the data is "1", the threshold voltage does not change.

Data erasing is performed in block units at substantially the same time. That is, all the control gates and select gates of the block to be erased are set to 0V, and the boosted potential VppE (about 20V) is applied to the p-type well and the n-type substrate.
VppE is also applied to the control gate and select gate of the block that is not erased. As a result, in the memory cell of the block to be erased, electrons in the floating gate are emitted to the well, and the threshold voltage moves in the negative direction.

In the data read operation, the bit lines are precharged and then floated, the control gates of the selected memory cells are set to 0V, and the control gates and select gates of the other memory cells are set to the power supply voltage Vcc (for example, 3V) and the source. This is performed by setting the line to 0 V and detecting in the bit line whether or not a current flows in the selected memory cell. That is,
If the data written in the memory cell is "0" (threshold value Vth> 0 of the memory cell), the memory cell is turned off, so the bit line maintains the precharge potential, but the data is "1" (memory cell If the threshold value Vth <0), the memory cell is turned on and the bit line drops from the precharge potential by ΔV. The data of the memory cell is read by detecting these bit line potentials with a sense amplifier.

In the NAND cell type EEPROM, since a plurality of memory cells are connected in cascade, the cell current during reading is small. Further, since the control gate of the memory cell and the first and second selection gates are continuously arranged in the row direction, data for one page is read out to the bit line at the same time.

On the other hand, the present inventors provided two selection MOS transistors on the bit line side as shown in FIGS.
A memory cell array is proposed in which two adjacent NAND strings share a bit line. In the memory cell array of FIG. 1, three selection MOS transistors are provided for each NAND cell column to form a memory cell unit. Two selection MOS transistors connected in series are of E type (threshold Vth1> 0) and D type (threshold Vth2 <0.
0).

When the memory cell unit (1) is read out, SG1 is set to Vsgh1 (Vsgh1> Vth3: Vth3 is a threshold value of an E'type transistor), SG2 is set to 0V and SG3 is set.
To Vsgh2 (Vsgh2> Vth1). When reading the memory cell unit (2), SG1 is set to Vsgh1 (Vsg
h1> Vth3: Vth3 is the threshold of an E'type transistor), SG3 is 0V, SG2 is Vsgh2 (Vsgh2> Vth)
You can set it to 1). In this memory cell array, select M
Since the number of OS transistors is three per NAND column, the area of the memory cell array is increased, but the number of bit lines is half that of the conventional memory cell array, which has the advantage of facilitating the processing of the bit lines. .

Further, a memory cell array as shown in FIG. 3 is also proposed. In this memory cell array, unlike the conventional memory cell array (FIGS. 29 and 30), the source side select gate is not connected to the source line of the n-type diffusion layer but is in contact with the bit line. Also, one bit line contact has two NANDs in the conventional memory cell array.
Although shared by the columns, in the memory cell array of this embodiment, the number of bit line contacts in the entire memory cell array does not increase from that of the conventional memory cell array because the four NAND cell columns share the same.

In this memory cell array, one NAN
The threshold values of the two selection MOS transistors connecting the D cell column and the bit line are set to Vth1 and Vth2 (Vth1> Vth2).
There are two types. High threshold Vth1 (eg 2
A selection MOS transistor having V) will be referred to as an E type, and a selection MOS transistor having a low threshold Vth2 (for example, 0.5 V) will be referred to as an I type. The voltage applied to the select gate is a voltage Vsgh (for example, 3V) at which both the I-type and E-type transistors are turned on (Vsgh> Vt1, Vt2),
The voltage Vsgl (for example 1.5V) that turns on the I-type transistor and turns off the E-type transistor
(Vt1>Vsgl> Vt2).

As described above, by providing two types of threshold values of the selection MOS transistor and setting two types of voltages to be applied to the selection gate, when writing or reading,
One of the adjacent NAND cell columns can be made conductive with the bit line and the other can be made non-conductive. For example, the selection gate SG
When 1 is set to Vsgh and SG2 is set to Vsgl, the memory cell unit (2) of FIG. 3 is connected to the bit lines on both ends, but the memory cell unit 1 is connected to the bit lines on one end side, but the other end side. It becomes non-conductive with the bit line. Select gate S
When G1 is set to Vsgl and SG2 is set to Vsgh, the memory cell unit 1 in FIG. 3 is connected to the bit lines on both ends, but the memory cell unit 2 is connected to the bit lines on one end side, but the bits on the other end side are connected. It becomes non-conductive with the line.

In this memory cell array, the source line formed by the high resistance n-type diffusion layer is eliminated, and the source line is substituted by the bit line formed of a low resistance metal (for example, Al). The line is Icell ・ R (I
cell: current flowing through the memory cell, R: resistance of the source line)
By only floating from the ground potential, the problem that the cell current does not easily flow and the read time becomes long is solved.

FIG. 4 shows another example in which two types of selection MOS transistors, E type and I type, are provided. FIG.
Realizes a folded bit line configuration without increasing the memory cell array.

The conventional memory cell structure and the new memory cell structure described above have the following problems.

Select M as shown in FIGS. 1, 2, 3 and 4 above.
By providing a plurality of OS transistor thresholds,
Among the memory cells of the same page (memory cell unit sharing the same selection gate and control gate), when reading one memory cell, the other memory cell is deselected. Such a memory cell array has the following problems. (Problem 1) As described above, the bit line is set to the read precharge potential (1.8
V) and an intermediate potential (about 10V). At that time, the selection gates and control gates of the non-selected blocks are grounded. FIG. 5 shows a memory cell connected to one bit line in FIGS. 1 and 2, and FIG. 6 shows a structure of a selection MOS transistor (C1, C2; overlap capacitance between diffusion layer and selection gate). , Sum of surrounding capacitances, C3; capacitance between the select gate and the substrate, and when the select MOS transistor forms an inversion layer, C3 = Cox (oxide film capacitance). When charging the bit line when reading or writing,
The D type selection MOS transistor of the non-selected block is turned on. As a result, the select gates SG1 to SG255 of the non-selected blocks in FIG. 5 receive noise rising from 0V due to the capacitive coupling from C1, C2 and C3 in FIG.

Also in the E type selection MOS transistor, since the diffusion layer connected to the bit line contact is charged, the selection gates (SG1 to SG1) are formed by the capacitance C2 in FIG.
G255) receives noise rising from 0V. The size of the select gates (SG1 to SG255) raised by this noise depends on the size of the resistance of the select gates. That is, FIG.
If one end of the select gate is grounded through the row decoder as in the memory cell array of FIG.
As shown in (b), the selection MOS transistor farther from the row decoder (for example, 3 in FIGS. 7A and 7B) has a larger resistance to the grounded node (row decoder). Become.

The threshold (VthSG) of the E type selection gate of FIG. 5 is also shown in FIG. 7B, but as shown in FIG. 7B, the selection gate of the non-selected block is selected MOS by capacitive coupling. When it becomes larger than the threshold value of the transistor, D connected in series with the E type selection MOS transistor
Since the type selection MOS transistor (see FIGS. 1 and 2) is on even when it is not selected, the charge charged in the bit line is E
It leaks to the NAND cell column of the non-selected block through the type selection MOS transistor and the D type selection MOS transistor.

When an I type transistor is used as the selection MOS transistor as shown in FIGS.
In a conventional memory cell array such as the one shown in FIG.
Not, so the gate-substrate capacitive coupling (C3 in Figure 6)
However, the selection gate does not float from the ground potential, but the selection gate floats due to capacitive coupling due to the overlap capacitance and the sneak capacitance (C2 in FIG. 6) between the diffusion layer and the gate. As a result, the charge on the bit line leaks to the NAND cell column of the non-selected block.

The potential of the bit line drops due to the leakage of the charge charged in the bit line. In order to avoid erroneous writing and erroneous reading, it is necessary to further precharge the lowered bit line, which requires a long bit line charging time. (Problem 2) In the NAND cell type EEPROM, a verify read operation is performed to check whether or not writing has been sufficiently performed (Japanese Patent Application No. 3-343363). That is, the bit line is precharged as in normal reading (time t1 in FIG. 19) and then brought into a floating state. After that, when a verify voltage (for example, 0.5 V) is applied to the control gate of the memory cell in which the writing is performed, the bit line maintains the precharge potential in the memory cell in which "0" is written in the memory cell and "1" is written in the memory cell. The bit line is discharged in the memory cell and the memory cell in which the "0" write is insufficient. After that, the bit line connected to the memory cell in which “1” is written is recharged (verify recharge) (FIG. 1).
9 time t4).

As shown in FIG. 8, for example, when "0" is sufficiently written in the memory cell farthest from the row decoder and "1" is written in all the other memory cells, the bit line BLj Bit lines other than the above will be subjected to verify recharge to Vcc, for example. As a result, the select gate of the non-selected block floats from 0V as in the case of the above-mentioned read.

As the select gate floats, the charge on the floating bit line BLj leaks and the bit line BLj drops from the precharge potential. Bit line BLj that should keep "H" precharge (eg 1.8V)
Is lowered by the above-mentioned leak and becomes lower than the potential of the dummy bit line (for example, 1.5V) (for example, 1V).
Then, the bit line BLj is read as "L" level,
Although the "0" write is sufficient, the "0" write is read as insufficient (FIG. 20). As a result, even if the memory cell is sufficiently written, the memory cell is further written, so that the threshold value becomes large and the threshold distribution of the memory cell becomes large. Further, when the threshold value of the memory cell becomes equal to or higher than the power supply voltage Vcc due to this overwriting, this memory cell becomes a defective cell.

[0026]

As described above, the conventional NA is used.
In the ND cell type EEPROM, the select gate of the non-selected block floats and the bit line leaks, so that the bit line discharge time becomes longer and the precharge time becomes longer. Further, in the conventional write (or erase) method, at the time of verify read for checking whether the write (or erase) is sufficient after the write (or erase), as shown in FIG. 20, a select gate connected to the bit line contact of the non-selected block ( For example, SG4) floats, and as a result, the bit line (BL1A in FIG. 20) sufficient for writing "0" is discharged and falls below the potential of the dummy bit line (BL1B in FIG. 20).
"0" is read as insufficiently written, rewritten, and overwritten.

The present invention has been made in consideration of the above circumstances, and an object thereof is to prevent the bit line discharge time from becoming long due to the leak of the bit line and to speed up the precharge. A non-volatile semiconductor memory device that can be scaled is provided.

Another object of the present invention is to provide a non-volatile semiconductor memory device capable of suppressing a leak of a bit line at the time of verify read and preventing overwriting.

[0029]

In order to solve the above problems, the present invention employs the following configurations.

That is, the present invention provides a nonvolatile semiconductor memory device comprising a memory cell array in which one or a plurality of nonvolatile memory cells are arranged in a matrix, and a signal line connected to the memory cell array. It is characterized in that the signal line discharge prevention voltage is applied to the signal line before the desired signal line operating voltage is applied to the signal line.

The present invention also provides a nonvolatile semiconductor memory device comprising a memory cell array in which one or a plurality of nonvolatile memory cells are arranged in a matrix, and a signal line connected to the memory cell array. Prior to applying a desired signal line operating voltage to the signal line, a signal line discharge prevention voltage is applied to the signal line, and at least one gate electrode of the signal line discharge prevention transistor whose drain is connected to the signal line, A feature is that a signal line discharge prevention gate voltage is applied so that the discharge prevention transistor becomes conductive.

The preferred embodiments of the present invention are as follows. (1) The signal line is a so-called bit line that outputs the write data of the nonvolatile memory cell when reading the nonvolatile memory cell. (2) In the discharge prevention transistor, the drain is connected to the signal line and the source is connected to the nonvolatile memory cell.
Must be an S-transistor. (3) The selection MOS transistor is an n-channel MOS transistor formed on the p-type semiconductor layer, and the threshold voltage of the transistor is a negative voltage. (4) The selection MOS transistor is a p-channel MOS transistor formed on the n-type semiconductor layer, and the threshold voltage of the transistor is a positive voltage. (5) The discharge prevention transistor is a memory cell transistor that constitutes a non-volatile memory cell. (6) The signal line operating voltage is the read precharge voltage applied to the signal line during the read operation. (7) The signal line operating voltage is the write precharge voltage or the erase precharge voltage applied to the signal line at the time of writing or erasing. (8) Write verify read precharge voltage or erase applied to the signal line during write verify read or erase verify read, which checks whether the signal line operating voltage has been sufficiently written or erased after writing or erasing Verify Read Precharge voltage. (9) The signal line discharge prevention voltage is the power supply voltage or the power supply voltage in the chip. (10) The signal line discharge prevention gate voltage is the power supply voltage or the power supply voltage in the chip. (11) The signal line discharge prevention gate voltage is a signal line discharge prevention potential transfer voltage such that the signal line discharge prevention voltage is transferred from the drain to the source of the signal line discharge prevention transistor. (12) Apply the signal line discharge prevention voltage when the power is turned on or when the chip activation signal is input. (13) Apply the signal line discharge prevention gate voltage when the power is turned on or when the chip activation signal is input. (14) Apply the signal line discharge prevention voltage periodically after turning on the power or inputting the chip activation signal. (15) Apply the signal line discharge prevention gate voltage periodically after turning on the power or inputting the chip activation signal. (16) The nonvolatile memory cell is an electrically rewritable nonvolatile memory cell. (17) A non-volatile memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and a plurality of memory cells adjacent to each other are connected in series to share a source and drain to form a NAND cell. To do. (18) A non-volatile memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer and connecting one or a plurality of memory cells in parallel in such a manner that all source and drain are shared. To do.

[0033]

According to the present invention, the signal line discharge prevention voltage is applied to the signal line before the desired signal line operating voltage is applied to the signal line, for example, the bit line is precharged before the bit line is precharged. By precharging and discharging the line to Vcc, it is possible to prevent the bit line discharge time from being lengthened due to the leak of the bit line and speed up the precharge.
Further, by pre-charging the select gate connected to the bit line contact of the non-selected block, the bit line does not leak at the time of verify read, so that overwriting can be prevented.

[0034]

Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the present invention will be described by taking the memory cell array of FIG. 1 as an example. (Embodiment 1) FIG. 9 is a block diagram showing the configuration of a NAND cell type EEPROM according to this embodiment. In the figure, 1
Is a memory cell array as a memory means. Reference numeral 2 is a sense amplifier circuit as a latch means for writing and reading data. 3 is a row decoder for selecting word lines, 4 is a column decoder for selecting bit lines,
Reference numeral 5 is an address buffer, 6 is an I / O sense amplifier, 7 is a data input / output buffer, and 8 is a substrate potential control circuit.

FIG. 10 shows an example of the sense amplifier. The memory cell array of this embodiment is shown in FIG. 1, for example.

FIG. 11 is a timing chart showing the read operation of this embodiment. FIG. 11 shows data over three pages (for example, the first page is the control gate CG of FIGS. 1 and 2).
A memory cell of a memory cell unit (1) having a gate electrode of 1; a second page, a memory cell of a memory cell unit (2) having a gate electrode of CG1; and a third page a memory cell unit of a memory cell unit having a gate electrode of CG2 ( 1) Memory cell)
It is a timing chart at the time of reading. The timing for reading the data of the first page in FIG. 11 is shown in FIG.

As can be seen from FIG. 11, according to this embodiment, the bit line is charged toward a constant potential (for example, power supply voltage Vcc) prior to the read operation. At that time, as shown in FIG. 11, the selection MOS transistor having the selection gate as its gate electrode is turned on to the selection gate (for example, SG4) connected to the bit line contact of the non-selected block (that is, the block where reading is not performed). A certain voltage (for example, Vcc) may be applied. Source of the E type selection MOS transistor of the non-selected block (VSGS1, VSGS in FIG. 5)
2, VSGS3 ...) After being charged to Voff, the select gate (eg SG4) connected to the bit line contact of the unselected block is grounded. After SG4 is grounded, the bit line and the dummy bit line are discharged. Voff is read,
The voltage is such that when the bit line is precharged at the time of writing, the E type selection MOS transistor of the non-selected block is turned off even if the selection gate floats (for example, up to Vcc). Voff may be Vcc, for example.

In this embodiment, the source of the E-type selection MOS transistor whose drain is connected to the bit line contact of the non-selected block may be charged prior to reading, so that the selection gate (eg SG) of the non-selected block is charged.
4) is not set to a constant potential (for example, Vcc) higher than 0V, the select gate (for example, SG4) of the non-selected block is grounded, and the select gate floats due to capacitive coupling as the bit line is charged. The source of the E type selection MOS transistor connected to the bit line contact of the block may be charged.

The operation of reading the memory cell MC11 of FIG. 1 will be described with reference to the timing chart of FIG. First, before the read operation of FIG. 12, as shown in FIG. 11, the source of the selection MOS transistor connected to the bit line contact of the non-selected block is charged. Time t
The bit line BL1A is precharged to 1, for example, 1.8V, and the dummy bit line BL1B is precharged to, for example, 1.5V.
At time t2, a predetermined read voltage is applied to the selection gate and the control gate. That is, the selection gates SG1 and SG3 are Vcc (for example, 3V), SG2 is 0V, and the control gate CG1.
Is 0V, CG2 to CG8 is 3V, other control gates,
The select gate is set to 0V.

The data written in the memory cell is "0".
Then, since the memory cell is turned off, the bit line BL1A maintains the precharge potential. On the other hand, in the case of "1" read, the bit line BL1A is discharged to a lower potential (1.2 V, for example) than the dummy bit line BL1B through the memory cell. After the selection gate and the control gate are set to 0 V at time t3, the sense amplifier is activated at time t4 to activate the bit line B.
The potential difference between L1A and the dummy bit line BL1B is amplified.

As described in [Problems to be Solved by the Invention], in the conventional reading method, the reading process shown in FIG.
Select gates of unselected blocks such as 3 (eg SG
4) floats, and as a result, the charge leaks from the bit line (for example, BL1A) and the dummy bit line (for example, BL1B), and there is a problem that it takes time to precharge.

On the other hand, in this embodiment, as shown in FIG. 11, the E type selection MO of the non-selected block is preceded by the reading.
Source of S-transistor (eg VSGS1, VSGS in FIG. 5)
2, VSGS3 ...) is charged, the E-type selection MOS transistor is turned off even if the selection gate of the non-selected block floats, so that the bit line does not leak.

The source of the E type selection MOS transistor of the non-selected block shown in FIG. 11 may be charged from, for example, VA1 of FIG. 10 through the power supply voltage (Vcc) wiring.

As described above, in this embodiment, for example, the sense amplifier circuit VA1 in FIG. 10 may be charged to the bit line, for example, to Vcc. For reading, writing, erasing, etc., a bit line from the peripheral circuit, for example, 0.9V, 1.5V,
When charging to 1.8V or the like, charging is performed by the resistance R from the peripheral circuit to the bit line and the total capacity C of the bit line (the number of bit lines NBL × CBL (one bit line capacity) to be charged simultaneously). It takes a precharge time of about RC.
R is about 100Ω and the capacitance C per bit line
BL = 3 pF, NBL = 2000 to C = 6 nF. Therefore, the bit line precharge time is about RC = 0.6 μs.

In the conventional method, when the selection gate floats and the capacitance CBL of the bit line becomes 4.5 pF, for example,
Bit line precharge time is RC = 0.9μs,
The precharge time increases by about 50%.

On the other hand, as in this embodiment, the bit line is first set to V
When charging to cc and then discharging to Vss, the time required to charge / discharge the bit line is CBL × RBL (RBL; the resistance of the bit line is 300Ω), or CBL / gm (gm; 10 TR1) conductance)
Therefore, 10 ns to 50 n including the operation margin
It is about s. Therefore, even if the bit line is charged / discharged to Vcc before reading as in the present embodiment, the increase in the bit line precharge time is sufficiently smaller than the entire bit line precharge time and is 10% or less. .

Therefore, as described in [Prior Art],
Compared with the conventional precharge method in which the selection gate of the non-selected block floats and the bit line leaks, the bit line discharge time becomes longer. In this embodiment, the bit line is charged / discharged to Vcc in advance. You can precharge the line.

The structure of the memory cell array is shown in FIGS.
Not limited to For example, the memory cell arrays shown in FIGS. 3, 4, 14, 15, and 31 may be used.

Further, in FIG. 11, the bit line is charged / discharged to Vcc to charge the source of the selection MOS transistor connected to the bit line contact of the non-selected block prior to the read operation. The source of the E-type selection MOS transistor in the non-selected block may be charged at the same time as the pre-charging. At that time, FIG.
Select gates (eg, SG4 in FIG. 1, SG1, SG2, ... In FIG. 5) connected to the bit line contacts of the non-selected block (that is, the block in which reading is not performed) as described above.
In addition, a certain voltage (for example, Vcc) may be applied so that the selection MOS transistor having this selection gate as a gate electrode is turned on. Alternatively, the selection gate of the non-selected block is grounded and selected with bit line charging. By floating the gate by capacitive coupling, the source of the selection MOS transistor connected to the bit line contact of the non-selected block may be charged.

The source of the E type selection MOS transistor of the unselected block (SG4 in FIG. 1, VSGS1 and VSG in FIG. 5)
After S2, VSGS3 ...) Are charged to Voff, the select gate of the unselected block (eg SG4 in FIG. 1) is grounded. After the select gate (eg SG4 in FIG. 1) of the non-selected block is grounded, the bit line and the dummy bit line are discharged to the read precharge potential. As a circuit for discharging the bit line from Vcc to a precharge potential (for example, 1.8 V, 1.5 V, etc.), a circuit as shown in FIG. 17 can be considered.

As described above, after the source of the selection MOS transistor connected to the bit line contact of the non-selected block is charged, the bit line is not discharged to 0V but the precharge potential (for example, 1.5V, 1.8V) is shown. In the method of discharging with a circuit such as 17, the precharge becomes faster than the method of discharging the bit line to 0V and then charging to the precharge potential.

In the present embodiment, since the source of the E type selection MOS transistor connected to the bit line contact of the non-selected block may be charged, the E type selection MOS of the non-selected block is simultaneously charged with the precharge of the bit line.
In the method of charging the source of the transistor (Fig. 16),
The select gate (eg SG4) of the non-selected block is not set to a constant potential (eg Vcc) higher than 0V, the select gate (eg SG4) of the non-selected block is grounded, and the select gate is cupped as the bit line is charged. The source of the E type selection MOS transistor connected to the bit line contact of the non-selected block may be charged by floating by the ring.

In FIG. 11, the source of the E type selection MOS transistor connected to the bit line contact of the non-selected block is charged once before reading the first page in FIG. 11, but it is charged once. Not limited to
For example, it may be performed every time before reading one page at a time, or may be performed every time when reading three pages, for example.

In the above embodiment, the charging of the source of the E type selection MOS transistor connected to the bit line contact of the non-selected block is described, but the I type or E type selection MOS connected to the bit line contact of the non-selected block is described. I connected to the bit line contact of the selected block in the same procedure as charging the source of the transistor
The source of the type or E type selection MOS transistor may be charged. This can prevent the bit line from leaking through the E-type selection MOS transistor of the selected block. That is, for example, when reading the memory cell unit (1) in FIG.
(2) can be prevented from leaking.

In the above embodiment, when the source of the E type selection MOS transistor connected to the bit line contact is charged from the bit line, the selection gate is grounded to 0V or the power supply voltage Vcc, but the bit line potential is changed. In order to transfer without threshold drop, a voltage higher than Vcc is applied to the select gate (for example, when the threshold of the E type select MOS transistor is VthE, Vcc + VthE, Vcc + 2).
VthE) may be applied. The voltage applied to the select gate may be generated by the on-chip booster circuit. Further, Vcc in this embodiment may be an on-chip Vcc that is stepped down or boosted from an external Vcc within the chip. (Embodiment 2) The memory cell array of this embodiment is similar to that of (Embodiment 1), for example, as shown in FIGS. Writing (or erasing) is similar to reading, as shown in FIG.
As shown in 8, the source of the E type selection MOS transistor connected to the bit line contact of the non-selected block in advance is V
Charge it to'off '. As described in (Example 1), the select gate (for example, SG4 in FIG. 1) of the non-selected block may be grounded during this charging. FIG. 19
FIG. 6 is a timing chart when writing data for one page. The bit line to be written with "1" is precharged with an intermediate potential. However, if the source of the E type selection MOS transistor of the non-selected block is charged in advance, the bit line will not leak at the time of precharging the bit line. .

As described in [Problems to be Solved by the Invention], in the verify read for checking whether the writing (or erasing) is sufficient after the writing (or erasing) in the conventional writing (or erasing) method, the verify read shown in FIG. As described above, the select gate (for example, SG4) connected to the bit line contact of the non-selected block floats, and as a result, the bit line (BL1A in FIG. 20) sufficient to write “0” is discharged, and the potential of the dummy bit line (see FIG. 20 BL1B) and below,
"0" is read as insufficiently written, rewritten, and overwritten. On the other hand, in the present embodiment, since the select gate connected to the bit line contact of the non-selected block is charged in advance, the bit line does not leak at the time of verify read, so that such overwriting does not occur.

The timing of charging the source of the E type selection MOS transistor connected to the bit line contact of the non-selected block is arbitrary. For example, as shown in FIG. 21, after the data writing (or erasing) for one page is performed and before the write (or erasing) verify read is performed, the connection E to the bit line contact of the non-selected block is made.
The source of the type selection MOS transistor may be charged.

Further, the charging of the source of the E type selection MOS transistor connected to the bit line contact of the non-selected block is performed before writing (or erasing) the first page and writing (or erasing) the first page in FIGS. Or erase) It is performed once before verification, but the number of charging times is 1.
Not limited to degrees. Also, the timing of charging is arbitrary. For example, it may be performed each time before writing (or erasing) each page, or may be performed each time before verify reading for writing (or erasing) each page. Further, it may be performed every two pages of writing (or erasing) or every two pages of writing (or erasing) verify. Alternatively, it may be performed once before writing (or erasing) the first page and once before writing (erasing) verifying the first page. It may be performed once before the writing (or erasing) of the first page and once before the writing (erasing) verification of the third page. (Embodiment 3) The source of the E type selection MOS transistor connected to the bit line contact need not be charged after the read and write operation commands are input as in the above embodiment. For example, after a chip activation signal (chip enable) that activates the nonvolatile semiconductor memory device from the standby state is input to the nonvolatile semiconductor memory device, commands such as read, write, and erase are issued. The source of the E type selection MOS transistor connected to the bit line contact may be automatically charged without inputting. Furthermore, it may be performed periodically (for example, every 2 ms or every 1 second) after the chip activation signal is input.

As described above, the timing for charging the source of the E type selection MOS transistor connected to the bit line contact is highly arbitrary. In some cases,
It may be performed when the power is turned on. (Embodiment 4) The gist of the present invention will be described with reference to FIG.
According to the present invention, when the signal line 1 of FIG. 22 is precharged with a desired voltage during a read operation, a write operation, an erase operation, a write verify operation, an erase verify operation, or the like, the drain has the signal line 1. In order to prevent the electric charge of the signal line 1 from leaking even if the gate voltage (the voltage VMS of the memory cell selection line in FIG. 22) of the transistor (transistor TR in FIG. 22) connected to the node floats from 0V, the node NTR is set to a predetermined voltage in advance. To charge the VTR.

When the node NTR is charged to VTR, not only the voltage between the source and the gate (VMS-VTR) decreases but also the potential of the source increases from 0V, so that the substrate bias effect causes the transistor TR to be increased. The gate voltage V at which the threshold value becomes large and the transistor TR turns on
MS grows. As a result, even if the memory cell selection line floats from the ground potential due to capacitive coupling or the like, the charge on the signal line 1 does not leak through the transistor TR.

The node NTR can be charged at high speed by charging the signal line 1 to the power supply voltage or the power supply voltage in the chip.

In the first to third embodiments, the present invention has been described by taking the memory cell array of FIG. 1 as an example.
The memory cell to which the present invention is effective is not limited to this. A memory cell array to which the present invention is effective is shown in FIG.
23 (b) and FIG. 24, and the memory cell units of FIGS. 23 and 24 are shown in FIGS. 25 (a) (b) and 26 (a), for example.
The memory cell portions shown in (b), FIG. 27, and FIGS. 25 to 27 may be, for example, those shown in FIGS. 28 (a) (b) (c). As described above, there are various variations of the memory cell array to which the present invention can be applied. For example, FIG. 2, FIG. 3, FIG. 4, FIG.
5, FIG. 31 may be used.

The memory cell unit is not always shown in FIG.
The selection MOS transistor is not required as in 5-27, and the memory cells of FIGS. 23 and 24 are configured by using the memory cell unit of FIGS. 28A, 28B and 28C as a memory cell unit. Good. In the case of a memory cell array having no selection MOS transistor or selection gate, according to the present invention, at the time of read, write (or erase), write (or erase) verify read, the word line of the non-selected memory cell (see FIG. 28) is used. It is possible to eliminate the leak of the bit line due to the floating of (WL).

Further, in the above-mentioned embodiment, the case where the bit line is charged to a constant potential at the time of reading, writing and erasing is described. For example, the source line of FIGS. 23 (a) and 23 (b) is charged to a constant potential. Read, write, and erase by doing so (for example, NOR type, DINOR type, AND type EE
PROM read, write, erase, known example; T.Take
shima et al. ISSCC Dig. of Tech. Papers (1994), H. Ono
da et al. IEDM Dig. of Tech. Papers (1992), H. Kume et
al.IEDM Dig. of Tech. Papers (1992), A. Baker et al. I
The present invention can also be applied to SSCC Dig. Of Tech. Papers (1994)). In this case, the source (drain) of the transistor whose drain is connected to the source line (selection MOS transistor, memory cell, etc.) is charged in advance as described in the above embodiment, so that the cutoff characteristic of this transistor is reduced. The source line can be prevented from leaking at the time of reading, writing and erasing.

In the present invention, a transistor (selection MOS) whose drain is connected to a signal line (bit line, source line, etc.)
By pre-charging the source of a transistor or memory cell, the signal line is prevented from leaking through this transistor when the signal line is charged to a constant potential at the time of reading, writing and erasing. As described above, the signal line for carrying out is very arbitrary.

In addition, various modifications can be made without departing from the scope of the present invention.

[0067]

As described above, according to the present invention, the signal line discharge prevention voltage is applied to the signal line (the drain is connected to the signal line before the desired signal line operating voltage is applied to the signal line). A signal line discharge prevention gate voltage may be applied to at least one gate electrode of the signal line discharge prevention transistor to be connected so that the discharge prevention transistor becomes conductive. Realization of a non-volatile semiconductor memory device capable of preventing a long bit line discharge time, speeding up precharge, suppressing bit line leakage during verify read, and preventing overwriting. It becomes possible to do.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a memory cell array configuration for explaining the present invention.

FIG. 2 is a diagram showing an example of a memory cell array configuration for explaining the present invention.

FIG. 3 is a diagram showing an example of a memory cell array configuration for explaining the present invention.

FIG. 4 is a diagram showing an example of a memory cell array configuration for explaining the present invention.

FIG. 5 is a diagram showing a configuration of a bit line, a selection gate, and a selection MOS transistor for explaining the present invention.

FIG. 6 is a cross-sectional view showing the configuration of a selection MOS transistor.

FIG. 7 is a schematic diagram for explaining floating of a select gate from a ground potential.

FIG. 8 is another diagram for explaining floating of the select gate from the ground potential.

FIG. 9 is a NAND cell type EEPR according to the first embodiment.
The block diagram which shows the structure of OM.

FIG. 10 is a circuit diagram of a sense amplifier according to the first embodiment.

FIG. 11 is a timing chart for explaining the first embodiment.

FIG. 12 is a timing chart for explaining the first embodiment.

FIG. 13 is a timing chart for explaining the first embodiment.

FIG. 14 is a diagram showing a configuration example of a memory cell array for explaining the present invention.

FIG. 15 is a diagram showing a configuration example of a memory cell array for explaining the present invention.

FIG. 16 is a timing chart for explaining the first embodiment.

FIG. 17 is a circuit configuration diagram of a bit line precharge circuit in the first embodiment.

FIG. 18 is a timing chart for explaining the second embodiment.

FIG. 19 is a timing chart for explaining the second embodiment.

FIG. 20 is a timing chart for explaining a second embodiment.

FIG. 21 is a timing chart for explaining the second embodiment.

FIG. 22 is a diagram for explaining the gist of the present invention.

FIG. 23 is a diagram showing a configuration example of a memory cell array for explaining a fourth embodiment.

FIG. 24 is a diagram showing a configuration example of a memory cell array for explaining a fourth embodiment.

FIG. 25 is a diagram showing a configuration example of a memory cell unit for explaining a fourth embodiment.

FIG. 26 is a diagram showing a configuration example of a memory cell unit for explaining a fourth embodiment.

FIG. 27 is a diagram showing a configuration example of a memory cell unit for explaining a fourth embodiment.

FIG. 28 is a diagram showing a configuration example of a memory cell portion for explaining a fourth embodiment.

FIG. 29 is a plan view and an equivalent circuit diagram showing a cell configuration of a conventional NAND type EEPROM.

FIG. 30 is a cross-sectional view taken along the line AA ′ and the line BB ′ of FIG.

FIG. 31 is an equivalent circuit diagram of a memory cell array of a conventional NAND cell type EEPROM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory cell array 2 ... Sense amplifier circuit 3 ... Row decoder 4 ... Column decoder 5 ... Address buffer 6 ... I / O sense amplifier 7 ... Data input / output buffer 8 ... Substrate potential control circuit

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical indication location H01L 29/788 29/792 H01L 27/10 434 29/78 371

Claims (2)

[Claims] 1. A memory cell array having one or a plurality of non-volatile memory cells arranged in a matrix and a signal line connected to the memory cell array, wherein a desired signal line operating voltage is applied to the signal line. A non-volatile semiconductor memory device, wherein a signal line discharge prevention voltage is applied to the signal line prior to application. 2. A memory cell array having one or a plurality of non-volatile memory cells arranged in a matrix and a signal line connected to the memory cell array, wherein a desired signal line operating voltage is applied to the signal line. Prior to applying, a signal line discharge prevention voltage is applied to the signal line so that the discharge prevention transistor is conductive to at least one gate electrode of the signal line discharge prevention transistor whose drain is connected to the signal line. A non-volatile semiconductor memory device, characterized in that a signal line discharge prevention gate voltage is applied to.