JPH0863968A - Sram device - Google Patents

Abstract

PURPOSE: To enable batch writing of the same data by providing a batch circuit composed of OR gates between the row decoder and the word lines and providing access to the memory cell array by impressing batch control signals. CONSTITUTION: A batch circuit 7 is composed of OR gates, 71 to 76, between the row decoder 2 and the word lines, 51 to 56, in the memory cell array 1 in which the memory cells are matrixed. When a batch control signal S1 is impressed on each of the gates, 71 to 76, of the circuit 7, the array 1 is subjected to batch access and the same data is subjected to batch writing in a short period in accordance with the column address signals from the row address decoder 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SRAM (static type random access memory) device capable of batch writing.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing an outline of a conventional SRAM device. As shown in the figure, the SRAM device has a memory cell array 1 in which memory cells are arranged in a matrix, a row decoder 2 and a column decoder 4 for selecting arbitrary memory cells based on an address signal, and outputs to a bit line. Amplifier 3 for amplifying the data signal to be reproduced
And an input / output circuit for inputting / outputting a data signal. A more detailed description will be given with reference to FIG. 7. The memory cell array 1 includes memory cells (M ₁₁ , M ₁₂ , M ₁₃ , ..., M ₂₁ ,
M ₂₂ , M ₂₃ , ...) Are arranged in a matrix.
The selection lines of the memory cells in the row direction are commonly connected and connected to the word lines 51, 52, ..., And the memory cells M ₁₁ , M ₂₁ , M _31, M _41, ... In the column direction are connected to the bit lines D1, D2. Has been done. The respective pair of bit lines D1, D2 column selection transistors T _11, T _12, ... are respectively connected to, and is connected sense amplifier 3 _0, 3 ₁ ... to.

The row decoder 2 has AND gates 21, 22, 22.
And address signals A0, A0 *, A1, A
By 1 * (* means inversion) a given word line
To be selected. The column decoder 4 includes AND gates 41 to 44.
Column selection transistor T₁₁~ T ₁₄, T_{twenty one}~ T_{twenty four}, ... from
Address signal B0, which is generated and input to the column decoder 4,
Any column selection transistor by B0 *, B1, B1 *
Data is selected, and any pair of bit lines D1 and D2 are selected
And any memory cell is connected to the sense amplifier 3,
Read / write is performed.

Next, the write operation of the SRAM device will be described with reference to FIG. 8 when writing "0" data to the memory cell M ₁₁ . First, a write signal (write enable) WE * (“L” level) is applied to the inverter I and the buffer A2 via the inverter,
The inverter I and the buffer A2 are in operation. on the other hand,
The read signal (output enable) OE * is maintained at "H" level, and the "L" level signal is supplied to the buffer A1 via the inverter. Since buffer A1 is held in the cutoff state, the sense amplifier 3 ₀ consisting of the comparator CMP is maintained in the cutoff state.

In the above-described state, "0" data is input from the data input terminal and supplied to the buffer A2 and the inverter I respectively, the output of the buffer A2 is at "L" level, and the inverter I is An "H" level signal is output. Output of buffer A2 (“L” level)
Is applied to the bit line D1 via the column select transistor T11. The output (“H” level) of the inverter I is transmitted through the column selection transistor T11 of the column decoder 4 to the bit line D2.
Is applied to On the other hand, the AND gate 21 of the row decoder 2
An “H” level signal is applied to the word line 51 of the memory cell M ₁₁ via the. Transfer transistors Q3, Q4 of the memory cell M ₁₁ is turned on to "L" level is applied to the bit lines D1, since "H" level to the bit line D2 is applied, the driving transistor Q1 is turned on, The drive transistor Q2 is turned off. The potential of the storage node N1 is set to the "L" level, and the storage node N2
Potential becomes "H" level and "0" is applied to the memory cell M _11.
Data is written. Also, "1" from the data input terminal
When data is input, the potential of the bit line D1 becomes "H" level and the potential of the bit line D2 becomes "L" level. Therefore, the potential of the storage node N1 becomes "H" level,
The potential of the storage node N2 becomes the "L" level, so that "1" data is written into the memory cell M _11.

[0006]

As described above, in the conventional SRAM, when the same data is accessed in all the memory cells of the memory cell array 1 of FIG. 6, the bit lines are sequentially arranged for each word line. The data must be written in each memory cell by selecting. Therefore, SR
The AM device has a drawback that it takes time to write the same data, and has a drawback that its application is limited. Also, SRA
The M device has a disadvantage that it is disadvantageous as compared with the flash memory when high speed operation is required to write the same data. The present invention has been made in view of the above problems, and it is possible to perform batch writing of the same data in an S
It is an object to provide a RAM device.

[0007]

In order to solve the above-mentioned problems, the first SRAM device according to the present invention has a memory cell array arranged in a matrix in which the memory cells in the row direction are arranged in the word lines and in the column direction. Bit lines are provided respectively, each of which is provided with a voltage supply means for applying a write voltage to all of the word lines and a selection means for sequentially selecting the bit lines. The voltage supply means and the selection means enable the memory. The SRAM device is characterized in that the same data is written in each memory cell of the cell array. The second SRAM device according to the present invention has word lines in the memory cells arranged in a matrix in the row direction of the memory cell array.
Bit lines are provided in the column direction, respectively, and each of the bit lines is provided with a selection means for selecting all of the bit lines and a voltage supply means for sequentially applying a write voltage to the word line. The SRAM device is characterized in that the same data is written in each memory cell of the memory cell array by the selection means.

Further, a third SRAM device according to the present invention is
Word lines are provided in the row direction and bit lines are provided in the column direction of the memory cell array arranged in a matrix,
An SRAM device comprising: a voltage supply unit that supplies a write voltage to all of the word lines; and a setting unit that sets all of the bit lines to a selected state.
A third SRAM device is provided with a timing setting unit that sequentially operates one of the voltage supply unit and the setting unit to write the same data.

[0009]

In the SRAM device of the present invention, one of the word lines and the bit lines connected to the memory cell array is all selected, and the memory cells of each row or each column are collectively loaded with the same data. The memory cells are written in a short time. In addition, the SRAM device of the present invention includes the voltage supply means for supplying a signal to all the word lines and the setting means for setting all the column selection transistors for selecting the bit lines to the same data at once. Then, the time for writing the same data is shortened. Further, the batch writing as described above is performed for each chip according to the chip selection signal.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.
Explain. (Embodiment 1) FIG. 1 shows an embodiment of the SRAM device of the present invention.
It is a circuit diagram showing. In the figure, 1 is an SRAM cell
Memory cell array arranged in a matrix
And the memory cells (M₁₁, M₁₂, M₁₃,…),
(M_{twenty one}, M_{twenty two}, M_{twenty three},…),… Are arranged, and memos are written in the column direction.
Resel (M₁₁, M_{twenty one}, M₃₁,…), (M ₁₂, M_{twenty two}, M₃₂,
…),… Are arranged. Memory cells in the row direction (M₁₁,
M₁₂, M₁₃,…), (M_{twenty one}, M_{twenty two}, M_{twenty three},…),… Are line by line
To the word lines 51 to 56 ...
6 are connected to the output terminals of the OR gates 71 to 76
It One input terminal of each of the OR gates 71 to 76
Output terminals of the AND gates 21 to 26 of the row decoder 21
, And the other input terminals are commonly connected and write all at once
It is connected to the control terminal C1. OR gates 71 to 76
Form a collective write control circuit 7.

The memory cells in the column direction (M ₁₁ , M ₂₁ , M ₃₁ ,
...) is connected between the bit lines D1 and D2, and the memory cells (M ₁₂ , M ₂₂ , M ₃₂ , ...) Also have adjacent bit lines D1 and D1.
It is connected between D2. The pair of bit lines D1 and D2 are respectively connected to column selection transistors (T ₁₁ , T ₂₁ ), (T ₁₂ ,
T ₂₂₎ is connected ... to and is connected to the sense amplifier 3 _0, 3 _1. Column select transistors (T ₁₁ , T ₂₁ ),
The gate electrodes of (T ₁₂ , T ₂₂ ) ... Are AND gates 4
Are connected to the output terminals of 1, 42, 43, .... Address signals A0, A0 *, A1, A1 * are input to the row decoder 2, and address signals B1 *, B are input to the column decoder 4.
1, B0 *, B0 are input.

FIG. 2 is a circuit diagram showing a main part of FIG. In the figure, reference numeral 1 is an SRAM memory cell including drive transistors Q1 and Q2, transfer transistors Q3 and Q4, and load resistors R1 and R2. Transfer transistors Q3, Q
The control gate of 4 is connected to the word line 51. The bit lines D1 and D2 are connected to the drain electrodes of the transfer transistors Q3 and Q4, respectively.
Connected to the first electrode of. The gate electrode of the column selection transistor T11 is connected to the output terminal of the AND gate 41. Each second electrode of the column selection transistor T11 is connected to the input terminal of the comparator CPM, and its output terminal is connected to the input terminal of the buffer circuit A1. Furthermore,
Each second electrode of the column selection transistor T11 is connected to the buffer circuit A2 and the output terminal of the inverter I, and the buffer circuit A2 and the input terminal of the inverter I and the output terminal of the buffer circuit A1 are commonly connected.

Next, the collective write operation will be described with reference to FIG. 2 showing the main part of FIG. An address signal is applied to the row decoder 2 and the AND gate 21 of the row decoder 2
When the output of is at "H" level, the "H" level signal is applied to the word line 51 through the OR gate 71.
Also, if the output of the AND gate 21 is at "L" level, it becomes O
The output of the R gate 71 remains at "L" level. Now, even if the output of the AND gate 21 is at "L" level, the collective control signal ("H" level) is at the control terminal C1.
When applied to the other input terminal of the OR gate 71 via, the output of the OR gate 71 becomes "H" level. That is, the word line 51 becomes "H" level. Memory cell M
_An "H" level voltage is applied to the gates of the ₁₁ transfer transistors Q3 and Q4 to turn them on. On the other hand, assuming that the write signal (write enable signal) WE * is at "L" level, the buffer A2 and the inverter I are in the operating state via the inverter. The read signal (output enable signal) OE * is held at "H" level, and the buffer A1 is set to the cutoff state via the inverter.

If "0" data is input to the data input / output terminal after setting in such a state, a "L" level signal is output from the buffer A2 to the column selection transistor T1.
1 is applied to the drain of the transfer transistor Q3. Further, an "H" level signal is applied to the drain of the transfer transistor Q4 from the inverter I via the column selection transistor T11. The drive transistor Q1 is turned on and the drive transistor Q2 is turned off. The potential of the storage node N1 is "L" level, the potential of the storage node N2 becomes the "H" level, the memory cell M ₁₁ "0" data is written.

In the embodiment of FIG. 1, the row decoder 2
When the collective control signal S1 is input via the control terminal C1, no matter what the state of the address signals input from the word lines 51 to 56 to the OR gates 71 to 7 is.
The outputs of 6 are all at "H" level, and the word lines 51 to
56 is applied. Each memory cell M _11, M _12, ..., M _{21 ,}
The transfer transistors of M ₂₂ ... Are set to the ON state.
On the other hand, each column selection transistor (T11,
T21), (T12, T22), (T13, T23) ...
Are sequentially selected, and the same "0" data is sequentially written to the memory cells.

Further, in the embodiment of FIG. 3, delay circuits 81 to 83 are connected to one input terminal side of each of the OR gates 71 to 74 ... In the embodiment of FIG. When the collective control signal S1 is applied, the OR gates 71 to
The "H" level signal is output from 74 at the timing of one point, and the word lines are sequentially selected. Such a delay circuit is a timing setting means, which is added so that the "H" level signal is sequentially applied to the word lines and the write operation is accomplished within a predetermined time. It is possible to eliminate the occurrence of current concentration. The delay circuits 81 to 83 do not necessarily have to be provided as long as the power supply line is not blown even if a relatively large current flows.
Further, a logic circuit such as a ring counter may be used as the timing generating means without using the delay circuit as described above. In that case, by applying a pulse-shaped collective control signal, “H” is sequentially applied to the OR gates 71 to 74.
Applying the level signal at high speed, the word lines 51, 52, 5
By setting the potentials of 3 ... to "H" level, the same data can be written to each memory cell in a short time.

(Embodiment 2) FIG. 4 shows an SRA according to the present invention.
9 shows another embodiment of the M device. As shown in FIG. 4, unlike the embodiment of FIG. 1, in this embodiment, a collective control circuit 9 for collective control is provided on the column decoder side. In the figure, the column decoder 4 includes an AND gate 4
1 to 44 and column selection transistors (T11, T21),
(T12, T22), (T13, T23), (T14,
A collective control circuit 9 including OR gates 91 to 94 is provided between the gates of T24). OR gates 91 to 94
One input terminal is commonly connected to the control terminal C2, and the other input terminals of the OR gates 91 to 94 are ANDed.
It is connected to the output terminals of the gates 41 to 44. The output terminals of the OR gates 91 to 94 are column selection transistors (T
11, T21), (T12, T22), (T13, T2
3) and (T14, T24) are connected to the commonly connected gates, respectively.

As in the embodiment of FIG. 1, the row decoder 2 is A
ND gates 21 to 26, whose output terminals are
Connected to the power lines 51 to 56. Also, a pair of bit lines
Each of D1 and D2 is a column selection transistor (T11 to T2).
14) and (T21 to T24) on their first electrodes, respectively.
Their second electrodes are connected to the sense amplifier 3₀, 3 ₁
…It is connected to the. Next, its operation will be briefly explained.
When the collective control signal S1 is applied to the control terminal C2,
An “H” level signal is output through the OR gates 91 to 94.
Select transistors (T11 to T14), (T21 to T2
4) All gates of ... Are input and turned on. This
The input data can be written like
Depending on the output from the coder 2, the word lines 51 to 56 are ordered.
Input the next write signal (“H” level signal), and
The same data is written in the next memory cell. Each
The write operation of the memory cell is almost the same as that of the embodiment of FIG.
Done by

(Embodiment 3) FIG. 5 shows an SRA according to the present invention.
9 shows another embodiment of the M device. In the figure,
OR gates 71 to 76 are provided between the row decoder 2 and the memory cell 1.
The collective control circuit 7 and the timing setting circuit 10 are connected. The column decoder 4 has OR gates 91 to 94.
A collective control circuit 9 is provided. Since the connection of the collective control circuits 7 and 9 is the same as that of the above-mentioned embodiment, the description thereof will be omitted. Next, the write operation will be briefly described. When the control signal S1 is applied to the control terminal C1, all memory cells in the row and column directions are set to a selectable state. The control signal S2 is applied to the control terminal C3, the timing setting circuit 10 is operated, and the word line 5 is sequentially operated.
The same data is written by selecting 1 to 56.
When the control signal S2 is not applied, the timing setting circuit 10 is set to the through state, and the signal according to the address signal is input to each word line.

It is obvious that the timing setting circuit 10 may be provided on the column side, and the delay circuit of the embodiment of FIG. 3 may be used instead of using the timing setting circuit 10. Further, in the embodiment of FIG. 5, the write signal (“H” level) is directly applied to the word line from the collective write circuit 7 without passing through the timing setting circuit 10.
The same data may be written to all the memory cells of the memory cell array 1 at once. In that case, since a relatively large current flows as an operating current, it is necessary to use a wiring having a sufficient capacity so that a wiring such as a power supply line does not melt. In the above embodiment, the description has been made on a chip unit basis in which the memory cell array is integrated. However, each chip unit memory cell array has a terminal to which the chip selection signal CE * is input, and when a plurality of chips are used. The same data described in the above embodiment may be written in synchronization with the chip selection signal CE *.

[0021]

As described above, in the SRAM device of the present invention, a forced write signal is input to each memory cell of the memory cell array irrespective of the address signal input to the row and column decoders, either collectively or shortly. The same data is written in all the memory cells in time, and S
It is extremely effective for expanding the applications of RAM devices, and
This contributes to high-speed operation. Also, claim 1 or 2
In the SRAM device, the word line and the bit line connected to the memory cell array are all selected, and the memory cells in each row or column are collectively loaded with the same data in all the memory cells. There is an advantage that writing can be done in a short time. The SRAM device according to claim 3 is
By providing voltage supply means for supplying a signal to all of the word lines and setting means for setting all of the column selection transistors for selecting the bit lines, the same data can be collectively written or the same data can be written. There is an advantage that the data writing time can be shortened. In addition, the SRAM device according to the fourth aspect has the advantage that the increase in the wiring length can be eliminated because the wiring width can be made the same as the conventional one by including the timing setting circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an SRAM device according to the present invention.

FIG. 2 is a circuit diagram showing a main part of the SRAM device of FIG.

FIG. 3 is a circuit diagram showing an embodiment in which a write timing is controlled by a delay circuit.

FIG. 4 is a circuit diagram showing another embodiment of the SRAM device according to the present invention.

FIG. 5 is a circuit diagram showing another embodiment of the SRAM device according to the present invention.

FIG. 6 is a block diagram of a conventional SRAM device.

FIG. 7 is a circuit diagram showing an example of a conventional SRAM device.

8 is a circuit diagram showing a main part of the SRAM device of FIG.

[Description of sign]

1 memory cell array 2 row decoder 3, 3 ₀ , 3 ₁ sense amplifier 4 column decoder 7, 9 batch control circuit 10 timing setting circuit 21-26, 41-44 AND gate 51-56 word line 71-76, 91-94 OR gate _{T 11 ~T 14, T 21 ~T} 24 column selecting transistors

Claims (4)

[Claims] 1. In an SRAM device in which word lines are provided in a row direction and bit lines are provided in a column direction of a memory cell array arranged in a matrix, a voltage supply means for applying a write voltage to all of the word lines. And a selecting means for sequentially selecting the bit lines, wherein the same data is written in each memory cell of the memory cell array by the voltage supplying means and the selecting means. 2. An SRAM device in which word lines are provided in the row direction and bit lines are provided in the column direction of a memory cell array arranged in a matrix, and a selection means for bringing all of the bit lines into a selected state, A SRAM device comprising: a voltage supply unit that sequentially applies a write voltage to the word line, wherein the same data is written to each memory cell of the memory cell array by the voltage supply unit and the selection unit. 3. An SRAM device in which word lines are provided in a row direction and bit lines are provided in a column direction of a memory cell array arranged in a matrix, and a voltage supply for supplying a write voltage to all of the word lines is provided. An SRAM device comprising: means and setting means for setting all of the bit lines to a selected state. 4. The SRAM device according to claim 3, further comprising a timing setting unit that sequentially operates one of the voltage supply unit and the setting unit to write the same data.